clk: rockchip: rk3288: always enable gpll_ddr for ddrc.

When ddr frequency scanning, need to switch to gpll for saving
times.

Change-Id: Ibb7e4ed1fa4babaf65e1d98c8a0891766cea63de
Signed-off-by: Tang Yun ping <typ@rock-chips.com>

diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
index 6c2e24b0e7b7c768fa47b612a87b89dde3eb5ffa..d89b1706121eb640f11fb247536f901555678f6c 100644 (file)
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -306,7 +306,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
 
        GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED,
                        RK3288_CLKGATE_CON(0), 8, GFLAGS),
-       GATE(0, "gpll_ddr", "gpll", 0,
+       GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED,
                        RK3288_CLKGATE_CON(0), 9, GFLAGS),
        COMPOSITE_DDRCLK(SCLK_DDRCLK, "sclk_ddrc", mux_ddrphy_p, 0,
                         RK3288_CLKSEL_CON(26), 2, 1, 0, 0,