ARM: b.L: assume aliasing I-cache

To deal with the I-cache discrepancy between Cortex-A15 and Cortex-A7,
let's assume aliasing I-cache in both cases.

Note: this might need to be refined i.e. detect a big.LITTLE system
somehow by probing all CPUs not only the boot one.

Signed-off-by: Nicolas Pitre <nico@linaro.org>

diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index b4b1d397592b3d6435c0a503541c37d3fffcc016..b79d8f74e5b2f084e12ffe358ed7f3755e5b2e2b 100644 (file)
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -261,6 +261,19 @@ static int cpu_has_aliasing_icache(unsigned int arch)
        int aliasing_icache;
        unsigned int id_reg, num_sets, line_size;
 
+#ifdef CONFIG_BIG_LITTLE
+       /*
+        * We expect a combination of Cortex-A15 and Cortex-A7 cores.
+        * A7 = VIPT aliasing I-cache
+        * A15 = PIPT (non-aliasing) I-cache
+        * To cater for this discrepancy, let's assume aliasing I-cache
+        * all the time.  This means unneeded extra work on the A15 but
+        * only ptrace is affected which is not performance critical.
+        */
+       if ((read_cpuid_id() & 0xff0ffff0) == 0x410fc0f0)
+               return 1;
+#endif
+
        /* PIPT caches never alias. */
        if (icache_is_pipt())
                return 0;