drm/i915: Changes related to the sequence port no for

From now on for both DSI Ports A & C, the seq_port value has been
set to 0. seq_port value is parsed from Sequence block#53 of VBT.
So, for packets that needs to be read/write for DSI single link on
Port A and Port C will now be based on the DVO port from VBT block 2,
instead of seq_port.

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index f8c2269c434ce26e641d4492c230d4a15c500e8e..5493aef5a6a320ed43f1f8fc5e00ba51bba46975 100644 (file)
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -110,7 +110,15 @@ static u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi, u8 *data)
        vc = (byte >> MIPI_VIRTUAL_CHANNEL_SHIFT) & 0x3;
        seq_port = (byte >> MIPI_PORT_SHIFT) & 0x3;
 
-       port = intel_dsi_seq_port_to_port(seq_port);
+       /* For DSI single link on Port A & C, the seq_port value which is
+        * parsed from Sequence Block#53 of VBT has been set to 0
+        * Now, read/write of packets for the DSI single link on Port A and
+        * Port C will based on the DVO port from VBT block 2.
+        */
+       if (intel_dsi->ports == (1 << PORT_C))
+               port = PORT_C;
+       else
+               port = intel_dsi_seq_port_to_port(seq_port);
        /* LP or HS mode */
        intel_dsi->hs = mode;