Silencing several "enumeral and non-enumeral type in conditional expression" warnings...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234314 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp b/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
index 904d25632c839c56c9b3037250b10f6ae043bce9..590d72f8fe32516f54649f123c5d2d9f98d62732 100644 (file)
--- a/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
+++ b/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
@@ -160,13 +160,13 @@ unsigned ARMAsmBackend::getRelaxedOpcode(unsigned Op) const {
   default:
     return Op;
   case ARM::tBcc:
-    return HasThumb2 ? ARM::t2Bcc : Op;
+    return HasThumb2 ? (unsigned)ARM::t2Bcc : Op;
   case ARM::tLDRpci:
-    return HasThumb2 ? ARM::t2LDRpci : Op;
+    return HasThumb2 ? (unsigned)ARM::t2LDRpci : Op;
   case ARM::tADR:
-    return HasThumb2 ? ARM::t2ADR : Op;
+    return HasThumb2 ? (unsigned)ARM::t2ADR : Op;
   case ARM::tB:
-    return HasThumb2 ? ARM::t2B : Op;
+    return HasThumb2 ? (unsigned)ARM::t2B : Op;
   case ARM::tCBZ:
     return ARM::tHINT;
   case ARM::tCBNZ: