help
Support for Rockchip's RK29xx SoCs.
+config ARCH_RK30
+ bool "Rockchip RK30xx"
+ select PLAT_RK
+ select CPU_V7
+ select ARM_GIC
+ select PL330
+ select HAVE_SMP
+ select MIGHT_HAVE_CACHE_L2X0
+ help
+ Support for Rockchip's RK30xx SoCs.
+
config PLAT_SPEAR
bool "ST SPEAr"
select ARM_AMBA
source "arch/arm/plat-rk/Kconfig"
source "arch/arm/mach-rk29/Kconfig"
+source "arch/arm/mach-rk30/Kconfig"
source "arch/arm/mach-sa1100/Kconfig"
machine-$(CONFIG_ARCH_PXA) := pxa
machine-$(CONFIG_ARCH_REALVIEW) := realview
machine-$(CONFIG_ARCH_RK29) := rk29
+machine-$(CONFIG_ARCH_RK30) := rk30
machine-$(CONFIG_ARCH_RPC) := rpc
machine-$(CONFIG_ARCH_S3C2410) := s3c2410 s3c2400 s3c2412 s3c2416 s3c2440 s3c2443
machine-$(CONFIG_ARCH_S3C24A0) := s3c24a0
.equ swapper_pg_dir, KERNEL_RAM_VADDR - 0x4000
.macro pgtbl, rd, phys
-#ifdef CONFIG_ARCH_RK29
+#if defined(CONFIG_ARCH_RK29) || defined(CONFIG_ARCH_RK30)
add \rd, \phys, #((TEXT_OFFSET - 0x4000) & 0xffff0000)
add \rd, \rd, #((TEXT_OFFSET - 0x4000) & 0x0000ffff)
#else
--- /dev/null
+if ARCH_RK30
+
+choice
+ prompt "RK30xx Board Type"
+ default MACH_RK30_SDK
+
+config MACH_RK30_SDK
+ bool "RK30 SDK board"
+
+endchoice
+
+endif
--- /dev/null
+obj-y += clock.o
+obj-y += common.o
+obj-y += io.o
+obj-y += reset.o
+obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
+obj-$(CONFIG_MACH_RK30_SDK) += board-rk30-sdk.o
--- /dev/null
+ zreladdr-y := 0x60408000
+params_phys-y := 0x60088000
+initrd_phys-y := 0x60800000
--- /dev/null
+/* arch/arm/mach-rk30/board-rk30-sdk.c
+ *
+ * Copyright (C) 2012 ROCKCHIP, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/input.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/i2c.h>
+#include <linux/skbuff.h>
+#include <linux/spi/spi.h>
+#include <linux/mmc/host.h>
+#include <linux/ion.h>
+
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/flash.h>
+#include <asm/hardware/gic.h>
+
+#include <mach/board.h>
+#include <mach/hardware.h>
+
+MACHINE_START(RK30, "RK30board")
+ .boot_params = PLAT_PHYS_OFFSET + 0x800,
+ .fixup = rk30_fixup,
+ .map_io = rk30_map_io,
+ .init_irq = rk30_init_irq,
+MACHINE_END
--- /dev/null
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+
+int clk_enable(struct clk *clk)
+{
+ int ret = 0;
+
+ if (clk == NULL || IS_ERR(clk))
+ return -EINVAL;
+
+ return ret;
+}
+EXPORT_SYMBOL(clk_enable);
+
+void clk_disable(struct clk *clk)
+{
+ if (clk == NULL || IS_ERR(clk))
+ return;
+}
+EXPORT_SYMBOL(clk_disable);
--- /dev/null
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+
+#include <asm/hardware/gic.h>
+#include <asm/mach/arch.h>
+
+#include <mach/board.h>
+#include <mach/gpio.h>
+
+void __init rk30_init_irq(void)
+{
+ gic_init(0, IRQ_LOCALTIMER, RK30_GICD_BASE, RK30_GICC_BASE);
+}
+
+void __init rk30_map_io(void)
+{
+ rk30_map_common_io();
+}
+
+void __init rk30_fixup(struct machine_desc *desc, struct tag *tags,
+ char **cmdline, struct meminfo *mi)
+{
+ mi->nr_banks = 1;
+ mi->bank[0].start = PLAT_PHYS_OFFSET;
+ mi->bank[0].size = SZ_128M;
+}
--- /dev/null
+#ifndef __MACH_BOARD_H
+#define __MACH_BOARD_H
+
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/i2c.h>
+#include <linux/types.h>
+#include <linux/timer.h>
+#include <linux/notifier.h>
+#include <asm/setup.h>
+#include <plat/board.h>
+
+void __init rk30_map_common_io(void);
+void __init rk30_init_irq(void);
+void __init rk30_map_io(void);
+struct machine_desc;
+void __init rk30_fixup(struct machine_desc *desc, struct tag *tags, char **cmdline, struct meminfo *mi);
+
+#endif
--- /dev/null
+#ifndef __MACH_CLKDEV_H
+#define __MACH_CLKDEV_H
+
+static inline int __clk_get(struct clk *clk)
+{
+ return 1;
+}
+
+static inline void __clk_put(struct clk *clk)
+{
+}
+
+#endif
--- /dev/null
+/* arch/arm/mach-rk30/include/mach/debug-macro.S
+ *
+ * Copyright (C) 2012 ROCKCHIP, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <mach/io.h>
+
+ .macro addruart, rp, rv
+ ldr \rp, = RK30_UART1_PHYS
+ ldr \rv, = RK30_UART1_BASE
+ .endm
+
+#define UART_SHIFT 2
+#include <asm/hardware/debug-8250.S>
--- /dev/null
+#include <mach/io.h>
+
+#define HAVE_GET_IRQNR_PREAMBLE
+#include <asm/hardware/entry-macro-gic.S>
+
+ .macro disable_fiq
+ .endm
+
+ .macro get_irqnr_preamble, base, tmp
+ ldr \base, =RK30_GICC_BASE
+ .endm
+
+ .macro arch_ret_to_user, tmp1, tmp2
+ .endm
--- /dev/null
+#ifndef __MACH_GPIO_H
+#define __MACH_GPIO_H
+
+#include <mach/irqs.h>
+
+#define ARCH_NR_GPIOS NR_GPIO_IRQS
+#define PIN_BASE NR_GIC_IRQS
+
+#include <asm/errno.h>
+#include <asm-generic/gpio.h> /* cansleep wrappers */
+
+#define gpio_get_value __gpio_get_value
+#define gpio_set_value __gpio_set_value
+#define gpio_cansleep __gpio_cansleep
+
+static inline int gpio_to_irq(unsigned gpio)
+{
+ return gpio - PIN_BASE + NR_GIC_IRQS;
+}
+
+static inline int irq_to_gpio(unsigned irq)
+{
+ return irq - NR_GIC_IRQS + PIN_BASE;
+}
+
+#endif
--- /dev/null
+#ifndef __MACH_HARDWARE_H
+#define __MACH_HARDWARE_H
+
+#endif
--- /dev/null
+#ifndef __MACH_IO_H
+#define __MACH_IO_H
+
+#define IO_SPACE_LIMIT 0xffffffff
+
+#define __io(a) __typesafe_io(a)
+#define __mem_pci(a) (a)
+
+#ifdef __ASSEMBLER__
+#define IOMEM(x) (x)
+#else
+#define IOMEM(x) ((void __force __iomem *)(x))
+#endif
+
+/*
+ * RK30 IO memory map:
+ *
+ * Virt Phys Size What
+ * ---------------------------------------------------------------------------
+ * FEA00000 10000000 1M
+ * FEB00000 10100000 1M
+ * FEC00000 10200000 176K
+ * 10300000 1M Peri AXI BUS
+ * FEC80000 10500000 16K NANDC
+ * FECE0000 1FFE0000 128K CPU Debug
+ * FED00000 20000000 640K
+ * FEF00000 10080000/0 64K SRAM
+ */
+
+#define RK30_IO_TO_VIRT0(pa) IOMEM(pa + (0xFEA00000 - 0x10000000))
+#define RK30_IO_TO_VIRT1(pa) IOMEM(pa + (0xFED00000 - 0x20000000))
+
+#define RK30_L2MEM_PHYS 0x10000000
+#define RK30_L2MEM_SIZE SZ_512K
+#define RK30_IMEM_PHYS 0x10080000
+#define RK30_IMEM_SIZE SZ_64K
+#define RK30_GPU_PHYS 0x10090000
+#define RK30_GPU_SIZE SZ_64K
+
+#define RK30_ROM_PHYS 0x10100000
+#define RK30_ROM_SIZE SZ_16K
+#define RK30_VCODEC_PHYS 0x10104000
+#define RK30_VCODEC_SIZE SZ_16K
+#define RK30_CIF0_PHYS 0x10108000
+#define RK30_CIF0_SIZE SZ_8K
+#define RK30_CIF1_PHYS 0x1010a000
+#define RK30_CIF1_SIZE SZ_8K
+#define RK30_LCDC0_PHYS 0x1010c000
+#define RK30_LCDC0_SIZE SZ_8K
+#define RK30_LCDC1_PHYS 0x1010e000
+#define RK30_LCDC1_SIZE SZ_8K
+#define RK30_IPP_PHYS 0x10110000
+#define RK30_IPP_SIZE SZ_16K
+#define RK30_RGA_PHYS 0x10114000
+#define RK30_RGA_SIZE SZ_8K
+#define RK30_HDMI_PHYS 0x10116000
+#define RK30_HDMI_SIZE SZ_8K
+#define RK30_I2S0_8CH_PHYS 0x10118000
+#define RK30_I2S0_8CH_SIZE SZ_8K
+#define RK30_I2S1_2CH_PHYS 0x1011a000
+#define RK30_I2S1_2CH_SIZE SZ_8K
+#define RK30_I2S2_2CH_PHYS 0x1011c000
+#define RK30_I2S2_2CH_SIZE SZ_8K
+#define RK30_SPDIF_PHYS 0x1011e000
+#define RK30_SPDIF_SIZE SZ_8K
+
+#define RK30_UART0_PHYS 0x10124000
+#define RK30_UART0_BASE RK30_IO_TO_VIRT0(RK30_UART0_PHYS)
+#define RK30_UART0_SIZE SZ_8K
+#define RK30_UART1_PHYS 0x10126000
+#define RK30_UART1_BASE RK30_IO_TO_VIRT0(RK30_UART1_PHYS)
+#define RK30_UART1_SIZE SZ_8K
+#define RK30_CPU_AXI_BUS_PHYS 0x10128000
+#define RK30_CPU_AXI_BUS_SIZE SZ_32K
+
+#define RK30_L2C_PHYS 0x10138000
+#define RK30_L2C_BASE RK30_IO_TO_VIRT0(RK30_L2C_PHYS)
+#define RK30_L2C_SIZE SZ_16K
+#define RK30_SCU_PHYS 0x1013c000
+#define RK30_SCU_BASE RK30_IO_TO_VIRT0(RK30_SCU_PHYS)
+#define RK30_SCU_SIZE SZ_256
+#define RK30_GICC_PHYS 0x1013c100
+#define RK30_GICC_BASE RK30_IO_TO_VIRT0(RK30_GICC_PHYS)
+#define RK30_GICC_SIZE SZ_256
+#define RK30_GTIMER_PHYS 0x1013c200
+#define RK30_GTIMER_BASE RK30_IO_TO_VIRT0(RK30_GTIMER_PHYS)
+#define RK30_GTIMER_SIZE SZ_1K
+#define RK30_PTIMER_PHYS 0x1013c600
+#define RK30_PTIMER_BASE RK30_IO_TO_VIRT0(RK30_PTIMER_PHYS)
+#define RK30_PTIMER_SIZE (SZ_2K + SZ_512)
+#define RK30_GICD_PHYS 0x1013d000
+#define RK30_GICD_BASE RK30_IO_TO_VIRT0(RK30_GICD_PHYS)
+#define RK30_GICD_SIZE SZ_2K
+
+#define RK30_CORE_PHYS RK30_L2C_PHYS
+#define RK30_CORE_BASE RK30_IO_TO_VIRT0(RK30_CORE_PHYS)
+#define RK30_CORE_SIZE (RK30_L2C_SIZE + SZ_8K)
+
+#define RK30_USBHOST11_PHYS 0x10140000
+#define RK30_USBHOST11_SIZE SZ_256K
+#define RK30_USBOTG20_PHYS 0x10180000
+#define RK30_USBOTG20_SIZE SZ_256K
+#define RK30_USBHOST20_PHYS 0x101c0000
+#define RK30_USBHOST20_SIZE SZ_256K
+
+#define RK30_MAC_PHYS 0x10204000
+#define RK30_MAC_SIZE SZ_16K
+
+#define RK30_HSADC_PHYS 0x10210000
+#define RK30_HSADC_SIZE SZ_16K
+#define RK30_SDMMC0_PHYS 0x10214000
+#define RK30_SDMMC0_SIZE SZ_16K
+#define RK30_SDIO_PHYS 0x10218000
+#define RK30_SDIO_SIZE SZ_16K
+#define RK30_EMMC_PHYS 0x1021c000
+#define RK30_EMMC_SIZE SZ_16K
+#define RK30_PIDF_PHYS 0x10220000
+#define RK30_PIDF_SIZE SZ_16K
+
+#define RK30_PERI_AXI_BUS_PHYS 0x10300000
+#define RK30_PERI_AXI_BUS_SIZE SZ_1M
+
+#define RK30_NANDC_PHYS 0x10500000
+#define RK30_NANDC_SIZE SZ_16K
+
+#define RK30_SMC_BANK0_PHYS 0x11000000
+#define RK30_SMC_BANK0_SIZE SZ_16M
+#define RK30_SMC_BANK1_PHYS 0x12000000
+#define RK30_SMC_BANK1_SIZE SZ_16M
+
+#define RK30_CPU_DEBUG_PHYS 0x1FFE0000
+#define RK30_CPU_DEBUG_SIZE SZ_128K
+#define RK30_CRU_PHYS 0x20000000
+#define RK30_CRU_BASE RK30_IO_TO_VIRT1(RK30_CRU_PHYS)
+#define RK30_CRU_SIZE SZ_16K
+#define RK30_PMU_PHYS 0x20004000
+#define RK30_PMU_BASE RK30_IO_TO_VIRT1(RK30_PMU_PHYS)
+#define RK30_PMU_SIZE SZ_16K
+#define RK30_GRF_PHYS 0x20008000
+#define RK30_GRF_BASE RK30_IO_TO_VIRT1(RK30_GRF_PHYS)
+#define RK30_GRF_SIZE SZ_8K
+#define RK30_GPIO6_PHYS 0x2000a000
+#define RK30_GPIO6_BASE RK30_IO_TO_VIRT1(RK30_GPIO6_PHYS)
+#define RK30_GPIO6_SIZE SZ_8K
+
+#define RK30_TIMER3_PHYS 0x2000e000
+#define RK30_TIMER3_SIZE SZ_8K
+#define RK30_EFUSE_PHYS 0x20010000
+#define RK30_EFUSE_SIZE SZ_16K
+#define RK30_TZPC_PHYS 0x20014000
+#define RK30_TZPC_SIZE SZ_16K
+#define RK30_DMACS1_PHYS 0x20018000
+#define RK30_DMACS1_SIZE SZ_16K
+#define RK30_DMAC1_PHYS 0x2001c000
+#define RK30_DMAC1_SIZE SZ_16K
+#define RK30_DDR_PCTL_PHYS 0x20020000
+#define RK30_DDR_PCTL_SIZE SZ_16K
+
+#define RK30_I2C0_PHYS 0x2002c000
+#define RK30_I2C0_SIZE SZ_8K
+#define RK30_I2C1_PHYS 0x2002e000
+#define RK30_I2C1_SIZE SZ_8K
+#define RK30_PWM01_PHYS 0x20030000
+#define RK30_PWM01_SIZE SZ_16K
+#define RK30_GPIO0_PHYS 0x20034000
+#define RK30_GPIO0_BASE RK30_IO_TO_VIRT1(RK30_GPIO0_PHYS)
+#define RK30_GPIO0_SIZE SZ_16K
+#define RK30_TIMER0_PHYS 0x20038000
+#define RK30_TIMER0_SIZE SZ_8K
+#define RK30_TIMER1_PHYS 0x2003a000
+#define RK30_TIMER1_SIZE SZ_8K
+#define RK30_GPIO1_PHYS 0x2003c000
+#define RK30_GPIO1_BASE RK30_IO_TO_VIRT1(RK30_GPIO1_PHYS)
+#define RK30_GPIO1_SIZE SZ_8K
+#define RK30_GPIO2_PHYS 0x2003e000
+#define RK30_GPIO2_BASE RK30_IO_TO_VIRT1(RK30_GPIO2_PHYS)
+#define RK30_GPIO2_SIZE SZ_8K
+#define RK30_DDR_PUBL_PHYS 0x20040000
+#define RK30_DDR_PUBL_SIZE SZ_16K
+
+#define RK30_WDT_PHYS 0x2004c000
+#define RK30_WDT_SIZE SZ_16K
+#define RK30_PWM23_PHYS 0x20050000
+#define RK30_PWM23_SIZE SZ_16K
+#define RK30_I2C2_PHYS 0x20054000
+#define RK30_I2C2_SIZE SZ_16K
+#define RK30_I2C3_PHYS 0x20058000
+#define RK30_I2C3_SIZE SZ_16K
+#define RK30_I2C4_PHYS 0x2005c000
+#define RK30_I2C4_SIZE SZ_16K
+#define RK30_TSADC_PHYS 0x20060000
+#define RK30_TSADC_SIZE SZ_16K
+#define RK30_UART2_PHYS 0x20064000
+#define RK30_UART2_SIZE SZ_16K
+#define RK30_UART3_PHYS 0x20068000
+#define RK30_UART3_SIZE SZ_16K
+#define RK30_SARADC_PHYS 0x2006c000
+#define RK30_SARADC_SIZE SZ_16K
+#define RK30_SPI0_PHYS 0x20070000
+#define RK30_SPI0_SIZE SZ_16K
+#define RK30_SPI1_PHYS 0x20074000
+#define RK30_SPI1_SIZE SZ_16K
+#define RK30_DMAC2_PHYS 0x20078000
+#define RK30_DMAC2_SIZE SZ_16K
+#define RK30_SMC_PHYS 0x2007c000
+#define RK30_SMC_SIZE SZ_16K
+#define RK30_GPIO3_PHYS 0x20080000
+#define RK30_GPIO3_BASE RK30_IO_TO_VIRT1(RK30_GPIO3_PHYS)
+#define RK30_GPIO3_SIZE SZ_16K
+#define RK30_GPIO4_PHYS 0x20084000
+#define RK30_GPIO4_BASE RK30_IO_TO_VIRT1(RK30_GPIO4_PHYS)
+#define RK30_GPIO4_SIZE SZ_16K
+
+#endif
--- /dev/null
+#ifndef __MACH_IRQS_H
+#define __MACH_IRQS_H
+
+#define IRQ_LOCALTIMER 29
+
+#define RK30XX_IRQ(x) (x + 32)
+
+#define IRQ_DMAC1_0 RK30XX_IRQ(0)
+#define IRQ_DMAC1_1 RK30XX_IRQ(1)
+#define IRQ_DMAC2_0 RK30XX_IRQ(2)
+#define IRQ_DMAC2_1 RK30XX_IRQ(3)
+#define IRQ_DDR_PCTL RK30XX_IRQ(4)
+#define IRQ_GPU_GP RK30XX_IRQ(5)
+#define IRQ_GPU_MMU RK30XX_IRQ(6)
+#define IRQ_GPU_PP RK30XX_IRQ(7)
+
+#define IRQ_VEPU RK30XX_IRQ(9)
+#define IRQ_VDPU RK30XX_IRQ(10)
+#define IRQ_CIF0 RK30XX_IRQ(11)
+#define IRQ_CIF1 RK30XX_IRQ(12)
+#define IRQ_LCDC0 RK30XX_IRQ(13)
+#define IRQ_LCDC1 RK30XX_IRQ(14)
+#define IRQ_IPP RK30XX_IRQ(15)
+#define IRQ_USB_OTG RK30XX_IRQ(16)
+#define IRQ_USB_HOST RK30XX_IRQ(17)
+
+#define IRQ_MAC RK30XX_IRQ(19)
+#define IRQ_I2S2_2CH RK30XX_IRQ(20)
+#define IRQ_TSADC RK30XX_IRQ(21)
+#define IRQ_HSADC RK30XX_IRQ(22)
+#define IRQ_SDMMC RK30XX_IRQ(23)
+#define IRQ_SDIO RK30XX_IRQ(24)
+#define IRQ_EMMC RK30XX_IRQ(25)
+#define IRQ_SARADC RK30XX_IRQ(26)
+#define IRQ_NANDC RK30XX_IRQ(27)
+
+#define IRQ_SMC RK30XX_IRQ(29)
+#define IRQ_PIDF RK30XX_IRQ(30)
+#define IRQ_I2S0_8CH RK30XX_IRQ(31)
+#define IRQ_I2S1_2CH RK30XX_IRQ(32)
+#define IRQ_SPDIF RK30XX_IRQ(33)
+#define IRQ_UART0 RK30XX_IRQ(34)
+#define IRQ_UART1 RK30XX_IRQ(35)
+#define IRQ_UART2 RK30XX_IRQ(36)
+#define IRQ_UART3 RK30XX_IRQ(37)
+#define IRQ_SPI0 RK30XX_IRQ(38)
+#define IRQ_SPI1 RK30XX_IRQ(39)
+#define IRQ_I2C0 RK30XX_IRQ(40)
+#define IRQ_I2C1 RK30XX_IRQ(41)
+#define IRQ_I2C2 RK30XX_IRQ(42)
+#define IRQ_I2C3 RK30XX_IRQ(43)
+#define IRQ_TIMER0 RK30XX_IRQ(44)
+#define IRQ_TIMER1 RK30XX_IRQ(45)
+#define IRQ_TIMER2 RK30XX_IRQ(46)
+#define IRQ_PWM0 RK30XX_IRQ(47)
+#define IRQ_PWM1 RK30XX_IRQ(48)
+#define IRQ_PWM2 RK30XX_IRQ(49)
+#define IRQ_PWM3 RK30XX_IRQ(50)
+#define IRQ_WDT RK30XX_IRQ(51)
+#define IRQ_I2C4 RK30XX_IRQ(52)
+#define IRQ_PMU RK30XX_IRQ(53)
+#define IRQ_GPIO0 RK30XX_IRQ(54)
+#define IRQ_GPIO1 RK30XX_IRQ(55)
+#define IRQ_GPIO2 RK30XX_IRQ(56)
+#define IRQ_GPIO3 RK30XX_IRQ(57)
+#define IRQ_GPIO4 RK30XX_IRQ(58)
+
+#define IRQ_GPIO6 RK30XX_IRQ(60)
+#define IRQ_PERI_AHB_USB_ARBITER RK30XX_IRQ(61)
+#define IRQ_PERI_AHB_EMEM_ARBITER RK30XX_IRQ(62)
+#define IRQ_RGA RK30XX_IRQ(63)
+#define IRQ_HDMI RK30XX_IRQ(64)
+
+#define IRQ_SDMMC_DETECT RK30XX_IRQ(66)
+#define IRQ_SDIO_DETECT RK30XX_IRQ(67)
+#define IRQ_GPU_OBSRV_MAINFAULT RK30XX_IRQ(68)
+#define IRQ_PMU_STOP_EXIT_INT RK30XX_IRQ(69)
+#define IRQ_OBSERVER_MAINFAULT RK30XX_IRQ(70)
+#define IRQ_VPU_OBSRV_MAINFAULT RK30XX_IRQ(71)
+#define IRQ_PERI_OBSRV_MAINFAULT RK30XX_IRQ(72)
+#define IRQ_VIO1_OBSRV_MAINFAULT RK30XX_IRQ(73)
+#define IRQ_VIO0_OBSRV_MAINFAULT RK30XX_IRQ(74)
+#define IRQ_DMAC_OBSRV_MAINFAULT RK30XX_IRQ(75)
+
+#define NR_GIC_IRQS (IRQ_DMAC_OBSRV_MAINFAULT + 1)
+#define NR_GPIO_IRQS (5 * 32 + 16)
+#define NR_BOARD_IRQS 64
+#define NR_IRQS (NR_GIC_IRQS + NR_GPIO_IRQS + NR_BOARD_IRQS)
+
+#endif
--- /dev/null
+#ifndef __MACH_MEMORY_H
+#define __MACH_MEMORY_H
+
+/*
+ * Physical DRAM offset.
+ */
+#define PLAT_PHYS_OFFSET UL(0x60000000)
+
+#endif
--- /dev/null
+#ifndef __MACH_SYSTEM_H
+#define __MACH_SYSTEM_H
+
+#include <asm/proc-fns.h>
+
+static inline void arch_idle(void)
+{
+ cpu_do_idle();
+}
+
+extern void (*arch_reset)(char, const char *);
+
+#endif
--- /dev/null
+#ifndef __MACH_TIMEX_H
+#define __MACH_TIMEX_H
+
+#define CLOCK_TICK_RATE (HZ * 100000UL)
+
+#endif /* __ASM_ARCH_TIMEX_H */
--- /dev/null
+#ifndef __MACH_UNCOMPRESS_H
+#define __MACH_UNCOMPRESS_H
+
+#include <linux/serial_reg.h>
+#include <mach/io.h>
+
+static volatile u32 *UART = (u32 *)RK30_UART1_PHYS;
+
+static void putc(int c)
+{
+ while (!(UART[UART_LSR] & UART_LSR_THRE))
+ barrier();
+ UART[UART_TX] = c;
+}
+
+static inline void flush(void)
+{
+}
+
+static inline void arch_decomp_setup(void)
+{
+}
+
+static inline void arch_decomp_wdog(void)
+{
+}
+
+#endif
--- /dev/null
+#ifndef __MACH_VMALLOC_H
+#define __MACH_VMALLOC_H
+
+#define VMALLOC_END 0xFE800000
+
+#endif
--- /dev/null
+/* arch/arm/mach-rk30/io.c
+ *
+ * Copyright (C) 2011 ROCKCHIP, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/io.h>
+
+#include <asm/page.h>
+#include <asm/mach/map.h>
+
+#define RK30_DEVICE(name) { \
+ .virtual = (unsigned long) RK30_##name##_BASE, \
+ .pfn = __phys_to_pfn(RK30_##name##_PHYS), \
+ .length = RK30_##name##_SIZE, \
+ .type = MT_DEVICE, \
+ }
+
+static struct map_desc rk30_io_desc[] __initdata = {
+ RK30_DEVICE(CORE),
+ RK30_DEVICE(UART0),
+ RK30_DEVICE(UART1),
+ RK30_DEVICE(GRF),
+ RK30_DEVICE(CRU),
+ RK30_DEVICE(PMU),
+ RK30_DEVICE(GPIO0),
+ RK30_DEVICE(GPIO1),
+ RK30_DEVICE(GPIO2),
+ RK30_DEVICE(GPIO3),
+ RK30_DEVICE(GPIO4),
+ RK30_DEVICE(GPIO6),
+};
+
+void __init rk30_map_common_io(void)
+{
+ iotable_init(rk30_io_desc, ARRAY_SIZE(rk30_io_desc));
+}
--- /dev/null
+/*
+ * arch/arm/mach-rk30/localtimer.c
+ *
+ * Copyright (C) 2002 ARM Ltd.
+ * All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/init.h>
+#include <linux/smp.h>
+#include <linux/clockchips.h>
+#include <asm/irq.h>
+#include <asm/smp_twd.h>
+#include <asm/localtimer.h>
+
+/*
+ * Setup the local clock events for a CPU.
+ */
+int __cpuinit local_timer_setup(struct clock_event_device *evt)
+{
+ evt->irq = IRQ_LOCALTIMER;
+ twd_timer_setup(evt);
+ return 0;
+}
--- /dev/null
+#include <mach/system.h>\r
+\r
+static void rk30_arch_reset(char mode, const char *cmd)\r
+{\r
+}\r
+\r
+void (*arch_reset)(char, const char *) = rk30_arch_reset;\r
--- /dev/null
+#ifndef __PLAT_BOARD_H
+#define __PLAT_BOARD_H
+
+#define BOOT_MODE_NORMAL 0
+#define BOOT_MODE_FACTORY2 1
+#define BOOT_MODE_RECOVERY 2
+#define BOOT_MODE_CHARGE 3
+#define BOOT_MODE_POWER_TEST 4
+#define BOOT_MODE_OFFMODE_CHARGING 5
+#define BOOT_MODE_REBOOT 6
+#define BOOT_MODE_PANIC 7
+int board_boot_mode(void);
+
+/* for USB detection */
+#ifdef CONFIG_USB_GADGET
+int board_usb_detect_init(unsigned gpio);
+#else
+static int inline board_usb_detect_init(unsigned gpio) { return 0; }
+#endif
+
+/* for wakeup Android */
+void rk28_send_wakeup_key(void);
+
+#endif
ventana MACH_VENTANA VENTANA 2927
wm8505_7in_netbook MACH_WM8505_7IN_NETBOOK WM8505_7IN_NETBOOK 2928
rk29 MACH_RK29 RK29 2929
+rk30 ARCH_RK30 RK30 3066
#ec4350sdb MACH_EC4350SDB EC4350SDB 2929
mimas MACH_MIMAS MIMAS 2930
titan MACH_TITAN TITAN 2931
projects / firefly-linux-kernel-4.4.55.git / commitdiff