#ifdef CONFIG_SDMMC0_RK29
if(on)
{
+ #if defined(CONFIG_ARCH_RK30)
gpio_direction_output(GPIO3B_GPIO3B0,GPIO_HIGH);//set mmc0-clk to high
gpio_direction_output(GPIO3B_GPIO3B1,GPIO_HIGH);// set mmc0-cmd to high.
gpio_direction_output(GPIO3B_GPIO3B2,GPIO_HIGH);//set mmc0-data0 to high.
gpio_direction_output(GPIO3B_GPIO3B3,GPIO_HIGH);//set mmc0-data1 to high.
gpio_direction_output(GPIO3B_GPIO3B4,GPIO_HIGH);//set mmc0-data2 to high.
gpio_direction_output(GPIO3B_GPIO3B5,GPIO_HIGH);//set mmc0-data3 to high.
-
+ #elif defined(CONFIG_ARCH_RK31)
+ gpio_direction_output(RK30_PIN3_PA2,GPIO_HIGH);//set mmc0-clk to high
+ gpio_direction_output(RK30_PIN3_PA3,GPIO_HIGH);// set mmc0-cmd to high.
+ gpio_direction_output(RK30_PIN3_PA4,GPIO_HIGH);//set mmc0-data0 to high.
+ gpio_direction_output(RK30_PIN3_PA5,GPIO_HIGH);//set mmc0-data1 to high.
+ gpio_direction_output(RK30_PIN3_PA6,GPIO_HIGH);//set mmc0-data2 to high.
+ gpio_direction_output(RK30_PIN3_PA7,GPIO_HIGH);//set mmc0-data3 to high.
+ #endif
mdelay(30);
}
else
{
+ #if defined(CONFIG_ARCH_RK30)
rk30_mux_api_set(GPIO3B0_SDMMC0CLKOUT_NAME, GPIO3B_GPIO3B0);
gpio_request(RK30_PIN3_PB0, "mmc0-clk");
gpio_direction_output(RK30_PIN3_PB0,GPIO_LOW);//set mmc0-clk to low.
rk30_mux_api_set(GPIO3B5_SDMMC0DATA3_NAME, GPIO3B_GPIO3B5);
gpio_request(RK30_PIN3_PB5, "mmc0-data3");
gpio_direction_output(RK30_PIN3_PB5,GPIO_LOW);//set mmc0-data3 to low.
-
+ #elif defined(CONFIG_ARCH_RK31)
+ rk30_mux_api_set(GPIO3A2_SDMMC0CLKOUT_NAME, GPIO3A_GPIO3A2);
+ gpio_request(RK30_PIN3_PA2, "mmc0-clk");
+ gpio_direction_output(RK30_PIN3_PA2,GPIO_LOW);//set mmc0-clk to low.
+
+ rk30_mux_api_set(GPIO3A3_SDMMC0CMD_NAME, GPIO3A_GPIO3A3);
+ gpio_request(RK30_PIN3_PA3, "mmc0-cmd");
+ gpio_direction_output(RK30_PIN3_PA3,GPIO_LOW);//set mmc0-cmd to low.
+
+ rk30_mux_api_set(GPIO3A4_SDMMC0DATA0_NAME, GPIO3A_GPIO3A4);
+ gpio_request(RK30_PIN3_PA4, "mmc0-data0");
+ gpio_direction_output(RK30_PIN3_PA4,GPIO_LOW);//set mmc0-data0 to low.
+
+ rk30_mux_api_set(GPIO3A5_SDMMC0DATA1_NAME, GPIO3A_GPIO3A5);
+ gpio_request(RK30_PIN3_PA5, "mmc0-data1");
+ gpio_direction_output(RK30_PIN3_PA5,GPIO_LOW);//set mmc0-data1 to low.
+
+ rk30_mux_api_set(GPIO3A6_SDMMC0DATA2_NAME, GPIO3A_GPIO3A6);
+ gpio_request(RK30_PIN3_PA6, "mmc0-data2");
+ gpio_direction_output(RK30_PIN3_PA6,GPIO_LOW);//set mmc0-data2 to low.
+
+ rk30_mux_api_set(GPIO3A7_SDMMC0DATA3_NAME, GPIO3A_GPIO3A7);
+ gpio_request(RK30_PIN3_PA7, "mmc0-data3");
+ gpio_direction_output(RK30_PIN3_PA7,GPIO_LOW);//set mmc0-data3 to low.
+ #endif
mdelay(30);
}
#endif
}
else
{
+ #if defined(CONFIG_ARCH_RK30)
rk30_mux_api_set(GPIO3C5_SDMMC1CLKOUT_NAME, GPIO3C_GPIO3C5);
gpio_request(RK30_PIN3_PC5, "mmc1-clk");
gpio_direction_output(RK30_PIN3_PC5,GPIO_LOW);//set mmc1-clk to low.
rk30_mux_api_set(GPIO3C1_SDMMC1DATA0_NAME, GPIO3C_GPIO3C1);
gpio_request(RK30_PIN3_PC1, "mmc1-data0");
gpio_direction_output(RK30_PIN3_PC1,GPIO_LOW);//set mmc1-data0 to low.
+ #elif defined(CONFIG_ARCH_RK31)
+ rk30_mux_api_set(GPIO3C5_SDMMC1CLKOUT_RMIICLKOUT_RMIICLKIN_NAME, GPIO3C_GPIO3C5);
+ gpio_request(RK30_PIN3_PC5, "mmc1-clk");
+ gpio_direction_output(RK30_PIN3_PC5,GPIO_LOW);//set mmc1-clk to low.
+ rk30_mux_api_set(GPIO3C0_SDMMC1CMD_RMIITXEN_NAME, GPIO3C_GPIO3C0);
+ gpio_request(RK30_PIN3_PC0, "mmc1-cmd");
+ gpio_direction_output(RK30_PIN3_PC0,GPIO_LOW);//set mmc1-cmd to low.
+
+ rk30_mux_api_set(GPIO3C1_SDMMC1DATA0_RMIITXD1_NAME, GPIO3C_GPIO3C1);
+ gpio_request(RK30_PIN3_PC1, "mmc1-data0");
+ gpio_direction_output(RK30_PIN3_PC1,GPIO_LOW);//set mmc1-data0 to low.
+ #endif
mdelay(100);
}
#endif
case 1://SDMMC_CTYPE_4BIT:
{
+ #if defined(CONFIG_ARCH_RK30)
rk30_mux_api_set(GPIO3B3_SDMMC0DATA1_NAME, GPIO3B_SDMMC0_DATA1);
rk30_mux_api_set(GPIO3B4_SDMMC0DATA2_NAME, GPIO3B_SDMMC0_DATA2);
rk30_mux_api_set(GPIO3B5_SDMMC0DATA3_NAME, GPIO3B_SDMMC0_DATA3);
+ #elif defined(CONFIG_ARCH_RK31)
+ rk30_mux_api_set(GPIO3A5_SDMMC0DATA1_NAME, GPIO3A_SDMMC0DATA1);
+ rk30_mux_api_set(GPIO3A6_SDMMC0DATA2_NAME, GPIO3A_SDMMC0DATA2);
+ rk30_mux_api_set(GPIO3A7_SDMMC0DATA3_NAME, GPIO3A_SDMMC0DATA3);
+ #endif
}
break;
break;
case 0xFFFF: //gpio_reset
{
+ #if defined(CONFIG_ARCH_RK30)
rk30_mux_api_set(GPIO3A7_SDMMC0PWREN_NAME, GPIO3A_GPIO3A7);
gpio_request(RK30_PIN3_PA7,"sdmmc-power");
gpio_direction_output(RK30_PIN3_PA7,GPIO_HIGH); //power-off
gpio_direction_output(RK30_PIN3_PA7,GPIO_LOW); //power-on
rk29_sdmmc_gpio_open(0, 1);
+ #elif defined(CONFIG_ARCH_RK31)
+ rk30_mux_api_set(GPIO3A1_SDMMC0PWREN_NAME, GPIO3A_GPIO3A1);
+ gpio_request(RK30_PIN3_PA1,"sdmmc-power");
+ gpio_direction_output(RK30_PIN3_PA1,GPIO_HIGH); //power-off
+
+ rk29_sdmmc_gpio_open(0, 0);
+
+ gpio_direction_output(RK30_PIN3_PA1,GPIO_LOW); //power-on
+
+ rk29_sdmmc_gpio_open(0, 1);
+ #endif
}
break;
default: //case 0://SDMMC_CTYPE_1BIT:
{
- rk30_mux_api_set(GPIO3B1_SDMMC0CMD_NAME, GPIO3B_SDMMC0_CMD);
- rk30_mux_api_set(GPIO3B0_SDMMC0CLKOUT_NAME, GPIO3B_SDMMC0_CLKOUT);
- rk30_mux_api_set(GPIO3B2_SDMMC0DATA0_NAME, GPIO3B_SDMMC0_DATA0);
+ #if defined(CONFIG_ARCH_RK30)
+ rk30_mux_api_set(GPIO3B1_SDMMC0CMD_NAME, GPIO3B_SDMMC0_CMD);
+ rk30_mux_api_set(GPIO3B0_SDMMC0CLKOUT_NAME, GPIO3B_SDMMC0_CLKOUT);
+ rk30_mux_api_set(GPIO3B2_SDMMC0DATA0_NAME, GPIO3B_SDMMC0_DATA0);
rk30_mux_api_set(GPIO3B3_SDMMC0DATA1_NAME, GPIO3B_GPIO3B3);
gpio_request(RK30_PIN3_PB3, "mmc0-data1");
rk30_mux_api_set(GPIO3B5_SDMMC0DATA3_NAME, GPIO3B_GPIO3B5);
gpio_request(RK30_PIN3_PB5, "mmc0-data3");
gpio_direction_output(RK30_PIN3_PB5,GPIO_HIGH);//set mmc0-data3 to high.
+ #elif defined(CONFIG_ARCH_RK31)
+ rk30_mux_api_set(GPIO3A3_SDMMC0CMD_NAME, GPIO3A_SDMMC0CMD);
+ rk30_mux_api_set(GPIO3A2_SDMMC0CLKOUT_NAME, GPIO3A_SDMMC0CLKOUT);
+ rk30_mux_api_set(GPIO3A4_SDMMC0DATA0_NAME, GPIO3A_SDMMC0DATA0);
+
+ rk30_mux_api_set(GPIO3A5_SDMMC0DATA1_NAME, GPIO3A_GPIO3A5);
+ gpio_request(RK30_PIN3_PA5, "mmc0-data1");
+ gpio_direction_output(RK30_PIN3_PA5,GPIO_HIGH);//set mmc0-data1 to high.
+
+ rk30_mux_api_set(GPIO3A6_SDMMC0DATA2_NAME, GPIO3A_GPIO3A6);
+ gpio_request(RK30_PIN3_PA5, "mmc0-data2");
+ gpio_direction_output(RK30_PIN3_PA5,GPIO_HIGH);//set mmc0-data2 to high.
+
+ rk30_mux_api_set(GPIO3A7_SDMMC0DATA3_NAME, GPIO3A_GPIO3A7);
+ gpio_request(RK30_PIN3_PA7, "mmc0-data3");
+ gpio_direction_output(RK30_PIN3_PA7,GPIO_HIGH);//set mmc0-data3 to high.
+ #endif
}
break;
}
static void rk29_sdmmc_set_iomux_mmc1(unsigned int bus_width)
{
+#if defined(CONFIG_ARCH_RK30)
rk30_mux_api_set(GPIO3C0_SMMC1CMD_NAME, GPIO3C_SMMC1_CMD);
rk30_mux_api_set(GPIO3C5_SDMMC1CLKOUT_NAME, GPIO3C_SDMMC1_CLKOUT);
rk30_mux_api_set(GPIO3C1_SDMMC1DATA0_NAME, GPIO3C_SDMMC1_DATA0);
rk30_mux_api_set(GPIO3C2_SDMMC1DATA1_NAME, GPIO3C_SDMMC1_DATA1);
rk30_mux_api_set(GPIO3C3_SDMMC1DATA2_NAME, GPIO3C_SDMMC1_DATA2);
rk30_mux_api_set(GPIO3C4_SDMMC1DATA3_NAME, GPIO3C_SDMMC1_DATA3);
+#elif defined(CONFIG_ARCH_RK31)
+ rk30_mux_api_set(GPIO3C0_SDMMC1CMD_RMIITXEN_NAME, GPIO3C_SDMMC1CMD);
+ rk30_mux_api_set(GPIO3C5_SDMMC1CLKOUT_RMIICLKOUT_RMIICLKIN_NAME, GPIO3C_SDMMC1CLKOUT);
+ rk30_mux_api_set(GPIO3C1_SDMMC1DATA0_RMIITXD1_NAME, GPIO3C_SDMMC1DATA0);
+ rk30_mux_api_set(GPIO3C2_SDMMC1DATA1_RMIITXD0_NAME, GPIO3C_SDMMC1DATA1);
+ rk30_mux_api_set(GPIO3C3_SDMMC1DATA2_RMIIRXD0_NAME, GPIO3C_SDMMC1DATA2);
+ rk30_mux_api_set(GPIO3C4_SDMMC1DATA3_RMIIRXD1_NAME, GPIO3C_SDMMC1DATA3);
+#endif
}
static void rk29_sdmmc_set_iomux_mmc2(unsigned int bus_width)
#define RK_FB_MEM_SIZE 3*SZ_1M
#if defined(CONFIG_FB_ROCKCHIP)
-#define LCD_CS_MUX_NAME GPIO4C7_SMCDATA7_TRACEDATA7_NAME
-#define LCD_CS_PIN RK30_PIN4_PC7
+#define LCD_CS_MUX_NAME GPIO2A7_LCDC1DATA7_SMCDATA7_TRACEDATA7_NAME
+#define LCD_CS_PIN RK30_PIN2_PA7
#define LCD_CS_VALUE GPIO_HIGH
-#define LCD_EN_MUX_NAME GPIO4C7_SMCDATA7_TRACEDATA7_NAME
-#define LCD_EN_PIN RK30_PIN6_PB4
+#define LCD_EN_MUX_NAME GPIO2D7_TESTCLOCKOUT_NAME
+#define LCD_EN_PIN RK30_PIN2_PD7
#define LCD_EN_VALUE GPIO_LOW
static int rk_fb_io_init(struct rk29_fb_setting_info *fb_setting)
{
int ret = 0;
- rk30_mux_api_set(LCD_CS_MUX_NAME, GPIO4C_GPIO4C7);
+ rk30_mux_api_set(LCD_CS_MUX_NAME, GPIO2A_GPIO2A7);
ret = gpio_request(LCD_CS_PIN, NULL);
if (ret != 0)
{
static int rk29_sdmmc0_cfg_gpio(void)
{
#ifdef CONFIG_SDMMC_RK29_OLD
- rk30_mux_api_set(GPIO3B1_SDMMC0CMD_NAME, GPIO3B_SDMMC0_CMD);
- rk30_mux_api_set(GPIO3B0_SDMMC0CLKOUT_NAME, GPIO3B_SDMMC0_CLKOUT);
- rk30_mux_api_set(GPIO3B2_SDMMC0DATA0_NAME, GPIO3B_SDMMC0_DATA0);
- rk30_mux_api_set(GPIO3B3_SDMMC0DATA1_NAME, GPIO3B_SDMMC0_DATA1);
- rk30_mux_api_set(GPIO3B4_SDMMC0DATA2_NAME, GPIO3B_SDMMC0_DATA2);
- rk30_mux_api_set(GPIO3B5_SDMMC0DATA3_NAME, GPIO3B_SDMMC0_DATA3);
+ rk30_mux_api_set(GPIO3A3_SDMMC0CMD_NAME, GPIO3A_SDMMC0CMD);
+ rk30_mux_api_set(GPIO3A2_SDMMC0CLKOUT_NAME, GPIO3A_SDMMC0CLKOUT);
+ rk30_mux_api_set(GPIO3A4_SDMMC0DATA0_NAME, GPIO3A_SDMMC0DATA0);
+ rk30_mux_api_set(GPIO3A5_SDMMC0DATA1_NAME, GPIO3A_SDMMC0DATA1);
+ rk30_mux_api_set(GPIO3A6_SDMMC0DATA2_NAME, GPIO3A_SDMMC0DATA2);
+ rk30_mux_api_set(GPIO3A7_SDMMC0DATA3_NAME, GPIO3A_SDMMC0DATA3);
- rk30_mux_api_set(GPIO3B6_SDMMC0DETECTN_NAME, GPIO3B_GPIO3B6);
+ rk30_mux_api_set(GPIO3B0_SDMMC0DETECTN_NAME, GPIO3B_GPIO3B0);
- rk30_mux_api_set(GPIO3A7_SDMMC0PWREN_NAME, GPIO3A_GPIO3A7);
- gpio_request(RK30_PIN3_PA7, "sdmmc-power");
- gpio_direction_output(RK30_PIN3_PA7, GPIO_LOW);
+ rk30_mux_api_set(GPIO3A1_SDMMC0PWREN_NAME, GPIO3A_GPIO3A1);
+ gpio_request(RK30_PIN3_PA1, "sdmmc-power");
+ gpio_direction_output(RK30_PIN3_PA1, GPIO_LOW);
#else
rk29_sdmmc_set_iomux(0, 0xFFFF);
- rk30_mux_api_set(GPIO3B6_SDMMC0DETECTN_NAME, GPIO3B_SDMMC0_DETECT_N);
+ rk30_mux_api_set(GPIO3B0_SDMMC0DETECTN_NAME, GPIO3B_SDMMC0DETECTN);
#if defined(CONFIG_SDMMC0_RK29_WRITE_PROTECT)
gpio_request(SDMMC0_WRITE_PROTECT_PIN, "sdmmc-wp");
#include <linux/init.h>
+
+#if defined(CONFIG_ARCH_RK30)
//GPIO0A
#define GPIO0A_GPIO0A7 0
#define GPIO0A_I2S_8CH_SDI 1
#define GPIO6B_GPIO6B7 0
#define GPIO6B_TEST_CLOCK_OUT 1
-
-#define DEFAULT 0
-#define INITIAL 1
-
-#if defined(CONFIG_ARCH_RK31)
-
-#define GRF_GPIO0L_DIR 0x0000
-#define GRF_GPIO0H_DIR 0x0004
-#define GRF_GPIO1L_DIR 0x0008
-#define GRF_GPIO1H_DIR 0x000c
-#define GRF_GPIO2L_DIR 0x0010
-#define GRF_GPIO2H_DIR 0x0014
-#define GRF_GPIO3L_DIR 0x0018
-#define GRF_GPIO3H_DIR 0x001c
-#define GRF_GPIO0L_DO 0x0020
-#define GRF_GPIO0H_DO 0x0024
-#define GRF_GPIO1L_DO 0x0028
-#define GRF_GPIO1H_DO 0x002c
-#define GRF_GPIO2L_DO 0x0030
-#define GRF_GPIO2H_DO 0x0034
-#define GRF_GPIO3L_DO 0x0038
-#define GRF_GPIO3H_DO 0x003c
-#define GRF_GPIO0L_EN 0x0040
-#define GRF_GPIO0H_EN 0x0044
-#define GRF_GPIO1L_EN 0x0048
-#define GRF_GPIO1H_EN 0x004c
-#define GRF_GPIO2L_EN 0x0050
-#define GRF_GPIO2H_EN 0x0054
-#define GRF_GPIO3L_EN 0x0058
-#define GRF_GPIO3H_EN 0x005c
-#define GRF_GPIO0A_IOMUX RK30_GRF_BASE+0x0060
-#define GRF_GPIO0B_IOMUX RK30_GRF_BASE+0x0064
-#define GRF_GPIO0C_IOMUX RK30_GRF_BASE+0x0068
-#define GRF_GPIO0D_IOMUX RK30_GRF_BASE+0x006c
-#define GRF_GPIO1A_IOMUX RK30_GRF_BASE+0x0070
-#define GRF_GPIO1B_IOMUX RK30_GRF_BASE+0x0074
-#define GRF_GPIO1C_IOMUX RK30_GRF_BASE+0x0078
-#define GRF_GPIO1D_IOMUX RK30_GRF_BASE+0x007c
-#define GRF_GPIO2A_IOMUX RK30_GRF_BASE+0x0080
-#define GRF_GPIO2B_IOMUX RK30_GRF_BASE+0x0084
-#define GRF_GPIO2C_IOMUX RK30_GRF_BASE+0x0088
-#define GRF_GPIO2D_IOMUX RK30_GRF_BASE+0x008c
-#define GRF_GPIO3A_IOMUX RK30_GRF_BASE+0x0090
-#define GRF_GPIO3B_IOMUX RK30_GRF_BASE+0x0094
-#define GRF_GPIO3C_IOMUX RK30_GRF_BASE+0x0098
-#define GRF_GPIO3D_IOMUX RK30_GRF_BASE+0x009c
-#define GRF_SOC_CON0 0x00a0
-#define GRF_SOC_CON1 0x00a4
-#define GRF_SOC_CON2 0x00a8
-#define GRF_SOC_STATUS0 0x00ac
-#define GRF_DMAC1_CON0 0x00b0
-#define GRF_DMAC1_CON1 0x00b4
-#define GRF_DMAC1_CON2 0x00b8
-#define GRF_DMAC2_CON0 0x00bc
-#define GRF_DMAC2_CON1 0x00c0
-#define GRF_DMAC2_CON2 0x00c4
-#define GRF_DMAC2_CON3 0x00c8
-#define GRF_UOC0_CON0 0x010c
-#define GRF_UOC0_CON1 0x0110
-#define GRF_UOC0_CON2 0x0114
-#define GRF_UOC0_CON3 0x0118
-#define GRF_UOC1_CON0 0x011c
-#define GRF_UOC1_CON1 0x0120
-#define GRF_UOC1_CON2 0x0124
-#define GRF_UOC1_CON3 0x0128
-#define GRF_UOC2_CON0 0x012c
-#define GRF_UOC2_CON1 0x0130
-#define GRF_UOC3_CON0 0x0138
-#define GRF_UOC3_CON1 0x013c
-#define GRF_HSIC_STAT 0x0140
-#define GRF_DDRC_CON0 0x00ec
-#define GRF_DDRC_STAT 0x00f0
-#define GRF_OS_REG0 0x0144
-#define GRF_OS_REG1 0x0148
-#define GRF_OS_REG2 0x014c
-#define GRF_OS_REG3 0x0150
-#define GRF_OS_REG4 0x0154
-#define GRF_OS_REG5 0x0158
-#define GRF_OS_REG6 0x015c
-#define GRF_OS_REG7 0x0160
-
-#else
-
#define GRF_GPIO0L_DIR 0x0000
#define GRF_GPIO0H_DIR 0x0004
#define GRF_GPIO1L_DIR 0x0008
#define GRF_OS_REG2 0x01d0
#define GRF_OS_REG3 0x01d4
-#endif
-
//GPIO0A
#define GPIO0A7_I2S8CHSDI_NAME "gpio0a7_i2s8chsdi_name"
//GPIO6B
#define GPIO6B7_TESTCLOCKOUT_NAME "gpio6b7_testclockout_name"
+
+#elif defined(CONFIG_ARCH_RK31)
+
+//GPIO0C
+#define GPIO0C_GPIO0C0 0
+#define GPIO0C_FLASHDATA8 1
+#define GPIO0C_GPIO0C1 0
+#define GPIO0C_FLASHDATA9 1
+#define GPIO0C_GPIO0C2 0
+#define GPIO0C_FLASHDATA10 1
+#define GPIO0C_GPIO0C3 0
+#define GPIO0C_FLASHDATA11 1
+#define GPIO0C_GPIO0C4 0
+#define GPIO0C_FLASHDATA12 1
+#define GPIO0C_GPIO0C5 0
+#define GPIO0C_FLASHDATA13 1
+#define GPIO0C_GPIO0C6 0
+#define GPIO0C_FLASHDATA14 1
+#define GPIO0C_GPIO0C7 0
+#define GPIO0C_FLASHDATA15 1
+
+//GPIO0D
+#define GPIO0D_GPIO0D0 0
+#define GPIO0D_FLASHDQS 1
+#define GPIO0D_EMMCCLKOUT 2
+#define GPIO0D_GPIO0D1 0
+#define GPIO0D_FLASHCSN1 1
+#define GPIO0D_GPIO0D2 0
+#define GPIO0D_FLASHCSN2 1
+#define GPIO0D_EMMCCMD 2
+#define GPIO0D_GPIO0D3 0
+#define GPIO0D_FLASHCSN3 1
+#define GPIO0D_EMMCRSTNOUT 2
+#define GPIO0D_GPIO0D4 0
+#define GPIO0D_SPI1RXD 1
+#define GPIO0D_GPIO0D5 0
+#define GPIO0D_SPI1TXD 1
+#define GPIO0D_GPIO0D6 0
+#define GPIO0D_SPI1CLK 1
+#define GPIO0D_GPIO0D7 0
+#define GPIO0D_SPI1CSN0 1
+
+//GPIO1A
+#define GPIO1A_GPIO1A0 0
+#define GPIO1A_UART0SIN 1
+#define GPIO1A_GPIO1A1 0
+#define GPIO1A_UART0SOUT 1
+#define GPIO1A_GPIO1A2 0
+#define GPIO1A_UART0CTSN 1
+#define GPIO1A_GPIO1A3 0
+#define GPIO1A_UART0RTSN 1
+#define GPIO1A_GPIO1A4 0
+#define GPIO1A_UART1SIN 1
+#define GPIO1A_SPI0RXD 2
+#define GPIO1A_GPIO1A5 0
+#define GPIO1A_UART1SOUT 1
+#define GPIO1A_SPI0TXD 2
+#define GPIO1A_GPIO1A6 0
+#define GPIO1A_UART1CTSN 1
+#define GPIO1A_SPI0CLK 2
+#define GPIO1A_GPIO1A7 0
+#define GPIO1A_UART1RTSN 1
+#define GPIO1A_SPI0CSN0 2
+
+//GPIO1B
+#define GPIO1B_GPIO1B0 0
+#define GPIO1B_UART2SIN 1
+#define GPIO1B_JTAGTDI 2
+#define GPIO1B_GPIO1B1 0
+#define GPIO1B_UART2SOUT 1
+#define GPIO1B_JTAGTDO 2
+#define GPIO1B_GPIO1B2 0
+#define GPIO1B_UART3SIN 1
+#define GPIO1B_GPSMAG 2
+#define GPIO1B_GPIO1B3 0
+#define GPIO1B_UART3SOUT 1
+#define GPIO1B_GPSSIG 2
+#define GPIO1B_GPIO1B4 0
+#define GPIO1B_UART3CTSN 1
+#define GPIO1B_GPSRFCLK 2
+#define GPIO1B_GPIO1B5 0
+#define GPIO1B_UART3RTSN 1
+#define GPIO1B_GPIO1B6 0
+#define GPIO1B_SPDIFTX 1
+#define GPIO1B_SPI1CSN1 2
+#define GPIO1B_GPIO1B7 0
+#define GPIO1B_SPI0CSN1 1
+
+//GPIO1C
+#define GPIO1C_GPIO1C0 0
+#define GPIO1C_I2SCLK 1
+#define GPIO1C_GPIO1C1 0
+#define GPIO1C_I2SSCLK 1
+#define GPIO1C_GPIO1C2 0
+#define GPIO1C_I2SLRCLKRX 1
+#define GPIO1C_GPIO1C3 0
+#define GPIO1C_I2SLRCLKTX 1
+#define GPIO1C_GPIO1C4 0
+#define GPIO1C_I2SSDI 1
+#define GPIO1C_GPIO1C5 0
+#define GPIO1C_I2SSDO 1
+
+//GPIO1D
+#define GPIO1D_GPIO1D0 0
+#define GPIO1D_I2C0SDA 1
+#define GPIO1D_GPIO1D1 0
+#define GPIO1D_I2C0SCL 1
+#define GPIO1D_GPIO1D2 0
+#define GPIO1D_I2C1SDA 1
+#define GPIO1D_GPIO1D3 0
+#define GPIO1D_I2C1SCL 1
+#define GPIO1D_GPIO1D4 0
+#define GPIO1D_I2C2SDA 1
+#define GPIO1D_GPIO1D5 0
+#define GPIO1D_I2C2SCL 1
+#define GPIO1D_GPIO1D6 0
+#define GPIO1D_I2C4SDA 1
+#define GPIO1D_GPIO1D7 0
+#define GPIO1D_I2C4SCL 1
+
+//GPIO2A
+#define GPIO2A_GPIO2A0 0
+#define GPIO2A_LCDC1DATA0 1
+#define GPIO2A_SMCDATA0 2
+#define GPIO2A_TRACEDATA0 3
+#define GPIO2A_GPIO2A1 0
+#define GPIO2A_LCDC1DATA1 1
+#define GPIO2A_SMCDATA1 2
+#define GPIO2A_TRACEDATA1 3
+#define GPIO2A_GPIO2A2 0
+#define GPIO2A_LCDC1DATA2 1
+#define GPIO2A_SMCDATA2 2
+#define GPIO2A_TRACEDATA2 3
+#define GPIO2A_GPIO2A3 0
+#define GPIO2A_LCDC1DATA3 1
+#define GPIO2A_SMCDATA3 2
+#define GPIO2A_TRACEDATA3 3
+#define GPIO2A_GPIO2A4 0
+#define GPIO2A_LCDC1DATA4 1
+#define GPIO2A_SMCDATA4 2
+#define GPIO2A_TRACEDATA4 3
+#define GPIO2A_GPIO2A5 0
+#define GPIO2A_LCDC1DATA5 1
+#define GPIO2A_SMCDATA5 2
+#define GPIO2A_TRACEDATA5 3
+#define GPIO2A_GPIO2A6 0
+#define GPIO2A_LCDC1DATA6 1
+#define GPIO2A_SMCDATA6 2
+#define GPIO2A_TRACEDATA6 3
+#define GPIO2A_GPIO2A7 0
+#define GPIO2A_LCDC1DATA7 1
+#define GPIO2A_SMCDATA7 2
+#define GPIO2A_TRACEDATA7 3
+
+//GPIO2B
+#define GPIO2B_GPIO2B0 0
+#define GPIO2B_LCDC1DATA8 1
+#define GPIO2B_SMCDATA8 2
+#define GPIO2B_TRACEDATA8 3
+#define GPIO2B_GPIO2B1 0
+#define GPIO2B_LCDC1DATA9 1
+#define GPIO2B_SMCDATA9 2
+#define GPIO2B_TRACEDATA9 3
+#define GPIO2B_GPIO2B2 0
+#define GPIO2B_LCDC1DATA10 1
+#define GPIO2B_SMCDATA10 2
+#define GPIO2B_TRACEDATA10 3
+#define GPIO2B_GPIO2B3 0
+#define GPIO2B_LCDC1DATA11 1
+#define GPIO2B_SMCDATA11 2
+#define GPIO2B_TRACEDATA11 3
+#define GPIO2B_GPIO2B4 0
+#define GPIO2B_LCDC1DATA12 1
+#define GPIO2B_SMCDATA12 2
+#define GPIO2B_TRACEDATA12 3
+#define GPIO2B_GPIO2B5 0
+#define GPIO2B_LCDC1DATA13 1
+#define GPIO2B_SMCDATA13 2
+#define GPIO2B_TRACEDATA13 3
+#define GPIO2B_GPIO2B6 0
+#define GPIO2B_LCDC1DATA14 1
+#define GPIO2B_SMCDATA14 2
+#define GPIO2B_TRACEDATA14 3
+#define GPIO2B_GPIO2B7 0
+#define GPIO2B_LCDC1DATA15 1
+#define GPIO2B_SMCDATA15 2
+#define GPIO2B_TRACEDATA15 3
+
+//GPIO2C
+#define GPIO2C_GPIO2C0 0
+#define GPIO2C_LCDC1DATA16 1
+#define GPIO2C_SMCADDR0 2
+#define GPIO2C_GPIO2C1 0
+#define GPIO2C_LCDC1DATA17 1
+#define GPIO2C_SMCADDR1 2
+#define GPIO2C_GPIO2C2 0
+#define GPIO2C_LCDC1DATA18 1
+#define GPIO2C_SMCADDR2 2
+#define GPIO2C_GPIO2C3 0
+#define GPIO2C_LCDC1DATA19 1
+#define GPIO2C_SMCADDR3 2
+#define GPIO2C_GPIO2C4 0
+#define GPIO2C_LCDC1DATA20 1
+#define GPIO2C_SMCADDR4 2
+#define GPIO2C_GPIO2C5 0
+#define GPIO2C_LCDC1DATA21 1
+#define GPIO2C_SMCADDR5 2
+#define GPIO2C_GPIO2C6 0
+#define GPIO2C_LCDC1DATA22 1
+#define GPIO2C_SMCADDR6 2
+#define GPIO2C_GPIO2C7 0
+#define GPIO2C_LCDC1DATA23 1
+#define GPIO2C_SMCADDR7 2
+
+//GPIO2D
+#define GPIO2D_GPIO2D0 0
+#define GPIO2D_LCDC1DCLK 1
+#define GPIO2D_SMCCSN0 2
+#define GPIO2D_GPIO2D1 0
+#define GPIO2D_LCDC1DEN 1
+#define GPIO2D_SMCWEN 2
+#define GPIO2D_GPIO2D2 0
+#define GPIO2D_LCDC1HSYNC 1
+#define GPIO2D_SMCOEN 2
+#define GPIO2D_GPIO2D3 0
+#define GPIO2D_LCDC1VSYNC 1
+#define GPIO2D_SMCADVN 2
+#define GPIO2D_GPIO2D4 0
+#define GPIO2D_SMCBLSN0 1
+#define GPIO2D_GPIO2D5 0
+#define GPIO2D_SMCBLSN1 1
+#define GPIO2D_GPIO2D6 0
+#define GPIO2D_SMCCSN1 1
+#define GPIO2D_GPIO2D7 0
+#define GPIO2D_TESTCLOCKOUT 1
+
+//GPIO3A
+#define GPIO3A_GPIO3A0 0
+#define GPIO3A_SDMMC0RSTNOUT 1
+#define GPIO3A_GPIO3A1 0
+#define GPIO3A_SDMMC0PWREN 1
+#define GPIO3A_GPIO3A2 0
+#define GPIO3A_SDMMC0CLKOUT 1
+#define GPIO3A_GPIO3A3 0
+#define GPIO3A_SDMMC0CMD 1
+#define GPIO3A_GPIO3A4 0
+#define GPIO3A_SDMMC0DATA0 1
+#define GPIO3A_GPIO3A5 0
+#define GPIO3A_SDMMC0DATA1 1
+#define GPIO3A_GPIO3A6 0
+#define GPIO3A_SDMMC0DATA2 1
+#define GPIO3A_GPIO3A7 0
+#define GPIO3A_SDMMC0DATA3 1
+
+//GPIO3B
+#define GPIO3B_GPIO3B0 0
+#define GPIO3B_SDMMC0DETECTN 1
+#define GPIO3B_GPIO3B1 0
+#define GPIO3B_SDMMC0WRITEPRT 1
+#define GPIO3B_GPIO3B3 0
+#define GPIO3B_CIFCLKOUT 1
+#define GPIO3B_GPIO3B4 0
+#define GPIO3B_CIFDATA0 1
+#define GPIO3B_HSADCDATA8 2
+#define GPIO3B_GPIO3B5 0
+#define GPIO3B_CIFDATA1 1
+#define GPIO3B_HSADCDATA9 2
+#define GPIO3B_GPIO3B6 0
+#define GPIO3B_CIFDATA10 1
+#define GPIO3B_I2C3SDA 2
+#define GPIO3B_GPIO3B7 0
+#define GPIO3B_CIFDATA11 1
+#define GPIO3B_I2C3SCL 2
+
+//GPIO3C
+#define GPIO3C_GPIO3C0 0
+#define GPIO3C_SDMMC1CMD 1
+#define GPIO3C_RMIITXEN 2
+#define GPIO3C_GPIO3C1 0
+#define GPIO3C_SDMMC1DATA0 1
+#define GPIO3C_RMIITXD1 2
+#define GPIO3C_GPIO3C2 0
+#define GPIO3C_SDMMC1DATA1 1
+#define GPIO3C_RMIITXD0 2
+#define GPIO3C_GPIO3C3 0
+#define GPIO3C_SDMMC1DATA2 1
+#define GPIO3C_RMIIRXD0 2
+#define GPIO3C_GPIO3C4 0
+#define GPIO3C_SDMMC1DATA3 1
+#define GPIO3C_RMIIRXD1 2
+#define GPIO3C_GPIO3C5 0
+#define GPIO3C_SDMMC1CLKOUT 1
+#define GPIO3C_RMIICLKOUT 2
+#define GPIO3C_RMIICLKIN 3
+#define GPIO3C_GPIO3C6 0
+#define GPIO3C_SDMMC1DETECTN 1
+#define GPIO3C_RMIIRXERR 2
+#define GPIO3C_GPIO3C7 0
+#define GPIO3C_SDMMC1WRITEPRT 1
+#define GPIO3C_RMIICRS 2
+
+//GPIO3D
+#define GPIO3D_GPIO3D0 0
+#define GPIO3D_SDMMC1PWREN 1
+#define GPIO3D_MIIMD 2
+#define GPIO3D_GPIO3D1 0
+#define GPIO3D_SDMMC1BACKENPWR 1
+#define GPIO3D_MIIMDCLK 2
+#define GPIO3D_GPIO3D2 0
+#define GPIO3D_SDMMC1INTN 1
+#define GPIO3D_GPIO3D3 0
+#define GPIO3D_PWM0 1
+#define GPIO3D_GPIO3D4 0
+#define GPIO3D_PWM1 1
+#define GPIO3D_JTAGTRSTN 2
+#define GPIO3D_GPIO3D5 0
+#define GPIO3D_PWM2 1
+#define GPIO3D_JTAGTCK 2
+#define GPIO3D_OTGDRVVBUS 3
+#define GPIO3D_GPIO3D6 0
+#define GPIO3D_PWM3 1
+#define GPIO3D_JTAGTMS 2
+#define GPIO3D_HOSTDRVVBUS 3
+
+#define GRF_GPIO0L_DIR 0x0000
+#define GRF_GPIO0H_DIR 0x0004
+#define GRF_GPIO1L_DIR 0x0008
+#define GRF_GPIO1H_DIR 0x000c
+#define GRF_GPIO2L_DIR 0x0010
+#define GRF_GPIO2H_DIR 0x0014
+#define GRF_GPIO3L_DIR 0x0018
+#define GRF_GPIO3H_DIR 0x001c
+#define GRF_GPIO0L_DO 0x0020
+#define GRF_GPIO0H_DO 0x0024
+#define GRF_GPIO1L_DO 0x0028
+#define GRF_GPIO1H_DO 0x002c
+#define GRF_GPIO2L_DO 0x0030
+#define GRF_GPIO2H_DO 0x0034
+#define GRF_GPIO3L_DO 0x0038
+#define GRF_GPIO3H_DO 0x003c
+#define GRF_GPIO0L_EN 0x0040
+#define GRF_GPIO0H_EN 0x0044
+#define GRF_GPIO1L_EN 0x0048
+#define GRF_GPIO1H_EN 0x004c
+#define GRF_GPIO2L_EN 0x0050
+#define GRF_GPIO2H_EN 0x0054
+#define GRF_GPIO3L_EN 0x0058
+#define GRF_GPIO3H_EN 0x005c
+#define GRF_GPIO0A_IOMUX RK30_GRF_BASE+0x0060
+#define GRF_GPIO0B_IOMUX RK30_GRF_BASE+0x0064
+#define GRF_GPIO0C_IOMUX RK30_GRF_BASE+0x0068
+#define GRF_GPIO0D_IOMUX RK30_GRF_BASE+0x006c
+#define GRF_GPIO1A_IOMUX RK30_GRF_BASE+0x0070
+#define GRF_GPIO1B_IOMUX RK30_GRF_BASE+0x0074
+#define GRF_GPIO1C_IOMUX RK30_GRF_BASE+0x0078
+#define GRF_GPIO1D_IOMUX RK30_GRF_BASE+0x007c
+#define GRF_GPIO2A_IOMUX RK30_GRF_BASE+0x0080
+#define GRF_GPIO2B_IOMUX RK30_GRF_BASE+0x0084
+#define GRF_GPIO2C_IOMUX RK30_GRF_BASE+0x0088
+#define GRF_GPIO2D_IOMUX RK30_GRF_BASE+0x008c
+#define GRF_GPIO3A_IOMUX RK30_GRF_BASE+0x0090
+#define GRF_GPIO3B_IOMUX RK30_GRF_BASE+0x0094
+#define GRF_GPIO3C_IOMUX RK30_GRF_BASE+0x0098
+#define GRF_GPIO3D_IOMUX RK30_GRF_BASE+0x009c
+#define GRF_SOC_CON0 0x00a0
+#define GRF_SOC_CON1 0x00a4
+#define GRF_SOC_CON2 0x00a8
+#define GRF_SOC_STATUS0 0x00ac
+#define GRF_DMAC1_CON0 0x00b0
+#define GRF_DMAC1_CON1 0x00b4
+#define GRF_DMAC1_CON2 0x00b8
+#define GRF_DMAC2_CON0 0x00bc
+#define GRF_DMAC2_CON1 0x00c0
+#define GRF_DMAC2_CON2 0x00c4
+#define GRF_DMAC2_CON3 0x00c8
+#define GRF_UOC0_CON0 0x010c
+#define GRF_UOC0_CON1 0x0110
+#define GRF_UOC0_CON2 0x0114
+#define GRF_UOC0_CON3 0x0118
+#define GRF_UOC1_CON0 0x011c
+#define GRF_UOC1_CON1 0x0120
+#define GRF_UOC1_CON2 0x0124
+#define GRF_UOC1_CON3 0x0128
+#define GRF_UOC2_CON0 0x012c
+#define GRF_UOC2_CON1 0x0130
+#define GRF_UOC3_CON0 0x0138
+#define GRF_UOC3_CON1 0x013c
+#define GRF_HSIC_STAT 0x0140
+#define GRF_DDRC_CON0 0x00ec
+#define GRF_DDRC_STAT 0x00f0
+#define GRF_OS_REG0 0x0144
+#define GRF_OS_REG1 0x0148
+#define GRF_OS_REG2 0x014c
+#define GRF_OS_REG3 0x0150
+#define GRF_OS_REG4 0x0154
+#define GRF_OS_REG5 0x0158
+#define GRF_OS_REG6 0x015c
+#define GRF_OS_REG7 0x0160
+
+//GPIO0C
+#define GPIO0C0_FLASHDATA8_NAME "gpio0c0_flashdata8_name"
+#define GPIO0C1_FLASHDATA9_NAME "gpio0c1_flashdata9_name"
+#define GPIO0C2_FLASHDATA10_NAME "gpio0c2_flashdata10_name"
+#define GPIO0C3_FLASHDATA11_NAME "gpio0c3_flashdata11_name"
+#define GPIO0C4_FLASHDATA12_NAME "gpio0c4_flashdata12_name"
+#define GPIO0C5_FLASHDATA13_NAME "gpio0c5_flashdata13_name"
+#define GPIO0C6_FLASHDATA14_NAME "gpio0c6_flashdata14_name"
+#define GPIO0C7_FLASHDATA15_NAME "gpio0c7_flashdata15_name"
+
+//GPIO0D
+#define GPIO0D0_FLASHDQS_EMMCCLKOUT_NAME "gpio0d0_flashdqs_emmcclkout_name"
+#define GPIO0D1_FLASHCSN1_NAME "gpio0d1_flashcsn1_name"
+#define GPIO0D2_FLASHCSN2_EMMCCMD_NAME "gpio0d2_flashcsn2_emmccmd_name"
+#define GPIO0D3_FLASHCSN3_EMMCRSTNOUT_NAME "gpio0d3_flashcsn3_emmcrstnout_name"
+#define GPIO0D4_SPI1RXD_NAME "gpio0d4_spi1rxd_name"
+#define GPIO0D5_SPI1TXD_NAME "gpio0d5_spi1txd_name"
+#define GPIO0D6_SPI1CLK_NAME "gpio0d6_spi1clk_name"
+#define GPIO0D7_SPI1CSN0_NAME "gpio0d7_spi1csn0_name"
+
+//GPIO1A
+#define GPIO1A0_UART0SIN_NAME "gpio1a0_uart0sin_name"
+#define GPIO1A1_UART0SOUT_NAME "gpio1a1_uart0sout_name"
+#define GPIO1A2_UART0CTSN_NAME "gpio1a2_uart0ctsn_name"
+#define GPIO1A3_UART0RTSN_NAME "gpio1a3_uart0rtsn_name"
+#define GPIO1A4_UART1SIN_SPI0RXD_NAME "gpio1a4_uart1sin_spi0rxd_name"
+#define GPIO1A5_UART1SOUT_SPI0TXD_NAME "gpio1a5_uart1sout_spi0txd_name"
+#define GPIO1A6_UART1CTSN_SPI0CLK_NAME "gpio1a6_uart1ctsn_spi0clk_name"
+#define GPIO1A7_UART1RTSN_SPI0CSN0_NAME "gpio1a7_uart1rtsn_spi0csn0_name"
+
+//GPIO1B
+#define GPIO1B0_UART2SIN_JTAGTDI_NAME "gpio1b0_uart2sin_jtagtdi_name"
+#define GPIO1B1_UART2SOUT_JTAGTDO_NAME "gpio1b1_uart2sout_jtagtdo_name"
+#define GPIO1B2_UART3SIN_GPSMAG_NAME "gpio1b2_uart3sin_gpsmag_name"
+#define GPIO1B3_UART3SOUT_GPSSIG_NAME "gpio1b3_uart3sout_gpssig_name"
+#define GPIO1B4_UART3CTSN_GPSRFCLK_NAME "gpio1b4_uart3ctsn_gpsrfclk_name"
+#define GPIO1B5_UART3RTSN_NAME "gpio1b5_uart3rtsn_name"
+#define GPIO1B6_SPDIFTX_SPI1CSN1_NAME "gpio1b6_spdiftx_spi1csn1_name"
+#define GPIO1B7_SPI0CSN1_NAME "gpio1b7_spi0csn1_name"
+
+//GPIO1C
+#define GPIO1C0_I2SCLK_NAME "gpio1c0_i2sclk_name"
+#define GPIO1C1_I2SSCLK_NAME "gpio1c1_i2ssclk_name"
+#define GPIO1C2_I2SLRCLKRX_NAME "gpio1c2_i2slrclkrx_name"
+#define GPIO1C3_I2SLRCLKTX_NAME "gpio1c3_i2slrclktx_name"
+#define GPIO1C4_I2SSDI_NAME "gpio1c4_i2ssdi_name"
+#define GPIO1C5_I2SSDO_NAME "gpio1c5_i2ssdo_name"
+
+//GPIO1D
+#define GPIO1D0_I2C0SDA_NAME "gpio1d0_i2c0sda_name"
+#define GPIO1D1_I2C0SCL_NAME "gpio1d1_i2c0scl_name"
+#define GPIO1D2_I2C1SDA_NAME "gpio1d2_i2c1sda_name"
+#define GPIO1D3_I2C1SCL_NAME "gpio1d3_i2c1scl_name"
+#define GPIO1D4_I2C2SDA_NAME "gpio1d4_i2c2sda_name"
+#define GPIO1D5_I2C2SCL_NAME "gpio1d5_i2c2scl_name"
+#define GPIO1D6_I2C4SDA_NAME "gpio1d6_i2c4sda_name"
+#define GPIO1D7_I2C4SCL_NAME "gpio1d7_i2c4scl_name"
+
+//GPIO2A
+#define GPIO2A0_LCDC1DATA0_SMCDATA0_TRACEDATA0_NAME "gpio2a0_lcdc1data0_smcdata0_tracedata0_name"
+#define GPIO2A1_LCDC1DATA1_SMCDATA1_TRACEDATA1_NAME "gpio2a1_lcdc1data1_smcdata1_tracedata1_name"
+#define GPIO2A2_LCDC1DATA2_SMCDATA2_TRACEDATA2_NAME "gpio2a2_lcdc1data2_smcdata2_tracedata2_name"
+#define GPIO2A3_LCDC1DATA3_SMCDATA3_TRACEDATA3_NAME "gpio2a3_lcdc1data3_smcdata3_tracedata3_name"
+#define GPIO2A4_LCDC1DATA4_SMCDATA4_TRACEDATA4_NAME "gpio2a4_lcdc1data4_smcdata4_tracedata4_name"
+#define GPIO2A5_LCDC1DATA5_SMCDATA5_TRACEDATA5_NAME "gpio2a5_lcdc1data5_smcdata5_tracedata5_name"
+#define GPIO2A6_LCDC1DATA6_SMCDATA6_TRACEDATA6_NAME "gpio2a6_lcdc1data6_smcdata6_tracedata6_name"
+#define GPIO2A7_LCDC1DATA7_SMCDATA7_TRACEDATA7_NAME "gpio2a7_lcdc1data7_smcdata7_tracedata7_name"
+
+//GPIO2B
+#define GPIO2B0_LCDC1DATA8_SMCDATA8_TRACEDATA8_NAME "gpio2b0_lcdc1data8_smcdata8_tracedata8_name"
+#define GPIO2B1_LCDC1DATA9_SMCDATA9_TRACEDATA9_NAME "gpio2b1_lcdc1data9_smcdata9_tracedata9_name"
+#define GPIO2B2_LCDC1DATA10_SMCDATA10_TRACEDATA10_NAME "gpio2b2_lcdc1data10_smcdata10_tracedata10_name"
+#define GPIO2B3_LCDC1DATA11_SMCDATA11_TRACEDATA11_NAME "gpio2b3_lcdc1data11_smcdata11_tracedata11_name"
+#define GPIO2B4_LCDC1DATA12_SMCDATA12_TRACEDATA12_NAME "gpio2b4_lcdc1data12_smcdata12_tracedata12_name"
+#define GPIO2B5_LCDC1DATA13_SMCDATA13_TRACEDATA13_NAME "gpio2b5_lcdc1data13_smcdata13_tracedata13_name"
+#define GPIO2B6_LCDC1DATA14_SMCDATA14_TRACEDATA14_NAME "gpio2b6_lcdc1data14_smcdata14_tracedata14_name"
+#define GPIO2B7_LCDC1DATA15_SMCDATA15_TRACEDATA15_NAME "gpio2b7_lcdc1data15_smcdata15_tracedata15_name"
+
+//GPIO2C
+#define GPIO2C0_LCDC1DATA16_SMCADDR0_TRACECLK_NAME "gpio2c0_lcdc1data16_smcaddr0_traceclk_name"
+#define GPIO2C1_LCDC1DATA17_SMCADDR1_TRACECTL_NAME "gpio2c1_lcdc1data17_smcaddr1_tracectl_name"
+#define GPIO2C2_LCDC1DATA18_SMCADDR2_NAME "gpio2c2_lcdc1data18_smcaddr2_name"
+#define GPIO2C3_LCDC1DATA19_SMCADDR3_NAME "gpio2c3_lcdc1data19_smcaddr3_name"
+#define GPIO2C4_LCDC1DATA20_SMCADDR4_NAME "gpio2c4_lcdc1data20_smcaddr4_name"
+#define GPIO2C5_LCDC1DATA21_SMCADDR5_NAME "gpio2c5_lcdc1data21_smcaddr5_name"
+#define GPIO2C6_LCDC1DATA22_SMCADDR6_NAME "gpio2c6_lcdc1data22_smcaddr6_name"
+#define GPIO2C7_LCDC1DATA23_SMCADDR7_NAME "gpio2c7_lcdc1data23_smcaddr7_name"
+
+//GPIO2D
+#define GPIO2D0_LCDC1DCLK_SMCCSN0_NAME "gpio2d0_lcdc1dclk_smccsn0_name"
+#define GPIO2D1_LCDC1DEN_SMCWEN_NAME "gpio2d1_lcdc1den_smcwen_name"
+#define GPIO2D2_LCDC1HSYNC_SMCOEN_NAME "gpio2d2_lcdc1hsync_smcoen_name"
+#define GPIO2D3_LCDC1VSYNC_SMCADVN_NAME "gpio2d3_lcdc1vsync_smcadvn_name"
+#define GPIO2D4_SMCBLSN0_NAME "gpio2d4_smcblsn0_name"
+#define GPIO2D5_SMCBLSN1_NAME "gpio2d5_smcblsn1_name"
+#define GPIO2D6_SMCCSN1_NAME "gpio2d6_smccsn1_name"
+#define GPIO2D7_TESTCLOCKOUT_NAME "gpio2d7_testclockout_name"
+
+//GPIO3A
+#define GPIO3A0_SDMMC0RSTNOUT_NAME "gpio3a0_sdmmc0rstnout_name"
+#define GPIO3A1_SDMMC0PWREN_NAME "gpio3a1_sdmmc0pwren_name"
+#define GPIO3A2_SDMMC0CLKOUT_NAME "gpio3a2_sdmmc0clkout_name"
+#define GPIO3A3_SDMMC0CMD_NAME "gpio3a3_sdmmc0cmd_name"
+#define GPIO3A4_SDMMC0DATA0_NAME "gpio3a4_sdmmc0data0_name"
+#define GPIO3A5_SDMMC0DATA1_NAME "gpio3a5_sdmmc0data1_name"
+#define GPIO3A6_SDMMC0DATA2_NAME "gpio3a6_sdmmc0data2_name"
+#define GPIO3A7_SDMMC0DATA3_NAME "gpio3a7_sdmmc0data3_name"
+
+//GPIO3B
+#define GPIO3B0_SDMMC0DETECTN_NAME "gpio3b0_sdmmc0detectn_name"
+#define GPIO3B1_SDMMC0WRITEPRT_NAME "gpio3b1_sdmmc0writeprt_name"
+#define GPIO3B3_CIFCLKOUT_NAME "gpio3b3_cifclkout_name"
+#define GPIO3B4_CIFDATA0_HSADCDATA8_NAME "gpio3b4_cifdata0_hsadcdata8_name"
+#define GPIO3B5_CIFDATA1_HSADCDATA9_NAME "gpio3b5_cifdata1_hsadcdata9_name"
+#define GPIO3B6_CIFDATA10_I2C3SDA_NAME "gpio3b6_cifdata10_i2c3sda_name"
+#define GPIO3B7_CIFDATA11_I2C3SCL_NAME "gpio3b7_cifdata11_i2c3scl_name"
+
+//GPIO3C
+#define GPIO3C0_SDMMC1CMD_RMIITXEN_NAME "gpio3c0_sdmmc1cmd_rmiitxen_name"
+#define GPIO3C1_SDMMC1DATA0_RMIITXD1_NAME "gpio3c1_sdmmc1data0_rmiitxd1_name"
+#define GPIO3C2_SDMMC1DATA1_RMIITXD0_NAME "gpio3c2_sdmmc1data1_rmiitxd0_name"
+#define GPIO3C3_SDMMC1DATA2_RMIIRXD0_NAME "gpio3c3_sdmmc1data2_rmiirxd0_name"
+#define GPIO3C4_SDMMC1DATA3_RMIIRXD1_NAME "gpio3c4_sdmmc1data3_rmiirxd1_name"
+#define GPIO3C5_SDMMC1CLKOUT_RMIICLKOUT_RMIICLKIN_NAME "gpio3c5_sdmmc1clkout_rmiiclkout_rmiiclkin_name"
+#define GPIO3C6_SDMMC1DETECTN_RMIIRXERR_NAME "gpio3c6_sdmmc1detectn_rmiirxerr_name"
+#define GPIO3C7_SDMMC1WRITEPRT_RMIICRS_NAME "gpio3c7_sdmmc1writeprt_rmiicrs_name"
+
+//GPIO3D
+#define GPIO3D0_SDMMC1PWREN_MIIMD_NAME "gpio3d0_sdmmc1pwren_miimd_name"
+#define GPIO3D1_SDMMC1BACKENDPWR_MIIMDCLK_NAME "gpio3d1_sdmmc1backendpwr_miimdclk_name"
+#define GPIO3D2_SDMMC1INTN_NAME "gpio3d2_sdmmc1intn_name"
+#define GPIO3D3_PWM0_NAME "gpio3d3_pwm0_name"
+#define GPIO3D4_PWM1_JTAGTRSTN_NAME "gpio3d4_pwm1_jtagtrstn_name"
+#define GPIO3D5_PWM2_JTAGTCK_OTGDRVVBUS_NAME "gpio3d5_pwm2_jtagtck_otgdrvvbus_name"
+#define GPIO3D6_PWM3_JTAGTMS_HOSTDRVVBUS_NAME "gpio3d6_pwm3_jtagtms_hostdrvvbus_name"
+
+#endif
+
+#define DEFAULT 0
+#define INITIAL 1
+
#define MUX_CFG(desc,reg,off,interl,mux_mode,bflags) \
{ \
.name = desc, \
/*
* description mux mode mux mux
* reg offset inter mode
- */
+ */
+#if defined(CONFIG_ARCH_RK30)
//GPIO0A
MUX_CFG(GPIO0A7_I2S8CHSDI_NAME, GPIO0A, 14, 1, 0, DEFAULT)
MUX_CFG(GPIO0A6_HOSTDRVVBUS_NAME, GPIO0A, 12, 1, 0, DEFAULT)
MUX_CFG(GPIO3D1_SDMMC1BACKENDPWR_NAME, GPIO3D, 2, 1, 0, DEFAULT)
MUX_CFG(GPIO3D0_SDMMC1PWREN_NAME, GPIO3D, 0, 1, 0, DEFAULT)
-#if defined(CONFIG_ARCH_RK30)
//GPIO4A
MUX_CFG(GPIO4A7_FLASHDATA15_NAME, GPIO4A, 14, 1, 0, DEFAULT)
MUX_CFG(GPIO4A6_FLASHDATA14_NAME, GPIO4A, 12, 1, 0, DEFAULT)
//GPIO6B
MUX_CFG(GPIO6B7_TESTCLOCKOUT_NAME, GPIO6B, 14, 1, 0, DEFAULT)
+#elif defined(CONFIG_ARCH_RK31)
+
+//GPIO0C
+MUX_CFG(GPIO0C7_FLASHDATA15_NAME, GPIO0C, 14, 1, 0, DEFAULT)
+MUX_CFG(GPIO0C6_FLASHDATA14_NAME, GPIO0C, 12, 1, 0, DEFAULT)
+MUX_CFG(GPIO0C5_FLASHDATA13_NAME, GPIO0C, 10, 1, 0, DEFAULT)
+MUX_CFG(GPIO0C4_FLASHDATA12_NAME, GPIO0C, 8, 1, 0, DEFAULT)
+MUX_CFG(GPIO0C3_FLASHDATA11_NAME, GPIO0C, 6, 1, 0, DEFAULT)
+MUX_CFG(GPIO0C2_FLASHDATA10_NAME, GPIO0C, 4, 1, 0, DEFAULT)
+MUX_CFG(GPIO0C1_FLASHDATA9_NAME, GPIO0C, 2, 1, 0, DEFAULT)
+MUX_CFG(GPIO0C0_FLASHDATA8_NAME, GPIO0C, 0, 1, 0, DEFAULT)
+
+//GPIO0D
+MUX_CFG(GPIO0D7_SPI1CSN0_NAME, GPIO0D, 14, 1, 0, DEFAULT)
+MUX_CFG(GPIO0D6_SPI1CLK_NAME, GPIO0D, 12, 1, 0, DEFAULT)
+MUX_CFG(GPIO0D5_SPI1TXD_NAME, GPIO0D, 10, 1, 0, DEFAULT)
+MUX_CFG(GPIO0D4_SPI1RXD_NAME, GPIO0D, 8, 1, 0, DEFAULT)
+MUX_CFG(GPIO0D3_FLASHCSN3_EMMCRSTNOUT_NAME, GPIO0D, 6, 2, 0, DEFAULT)
+MUX_CFG(GPIO0D2_FLASHCSN2_EMMCCMD_NAME, GPIO0D, 4, 2, 0, DEFAULT)
+MUX_CFG(GPIO0D1_FLASHCSN1_NAME, GPIO0D, 2, 2, 0, DEFAULT)
+MUX_CFG(GPIO0D0_FLASHDQS_EMMCCLKOUT_NAME, GPIO0D, 0, 2, 0, DEFAULT)
+
+//GPIO1A
+MUX_CFG(GPIO1A7_UART1RTSN_SPI0CSN0_NAME, GPIO1A, 14, 2, 0, DEFAULT)
+MUX_CFG(GPIO1A6_UART1CTSN_SPI0CLK_NAME, GPIO1A, 12, 2, 0, DEFAULT)
+MUX_CFG(GPIO1A5_UART1SOUT_SPI0TXD_NAME, GPIO1A, 10, 2, 0, DEFAULT)
+MUX_CFG(GPIO1A4_UART1SIN_SPI0RXD_NAME, GPIO1A, 8, 2, 0, DEFAULT)
+MUX_CFG(GPIO1A3_UART0RTSN_NAME, GPIO1A, 6, 1, 0, DEFAULT)
+MUX_CFG(GPIO1A2_UART0CTSN_NAME, GPIO1A, 4, 1, 0, DEFAULT)
+MUX_CFG(GPIO1A1_UART0SOUT_NAME, GPIO1A, 2, 1, 0, DEFAULT)
+MUX_CFG(GPIO1A0_UART0SIN_NAME, GPIO1A, 0, 1, 0, DEFAULT)
+
+//GPIO1B
+MUX_CFG(GPIO1B7_SPI0CSN1_NAME, GPIO1B, 14, 1, 0, DEFAULT)
+MUX_CFG(GPIO1B6_SPDIFTX_SPI1CSN1_NAME, GPIO1B, 12, 2, 0, DEFAULT)
+MUX_CFG(GPIO1B5_UART3RTSN_NAME, GPIO1B, 10, 2, 0, DEFAULT)
+MUX_CFG(GPIO1B4_UART3CTSN_GPSRFCLK_NAME, GPIO1B, 8, 2, 0, DEFAULT)
+MUX_CFG(GPIO1B3_UART3SOUT_GPSSIG_NAME, GPIO1B, 6, 2, 0, DEFAULT)
+MUX_CFG(GPIO1B2_UART3SIN_GPSMAG_NAME, GPIO1B, 4, 2, 0, DEFAULT)
+MUX_CFG(GPIO1B1_UART2SOUT_JTAGTDO_NAME, GPIO1B, 2, 2, 0, DEFAULT)
+MUX_CFG(GPIO1B0_UART2SIN_JTAGTDI_NAME, GPIO1B, 0, 2, 0, DEFAULT)
+
+//GPIO1C
+MUX_CFG(GPIO1C5_I2SSDO_NAME, GPIO1C, 10, 1, 0, DEFAULT)
+MUX_CFG(GPIO1C4_I2SSDI_NAME, GPIO1C, 8, 1, 0, DEFAULT)
+MUX_CFG(GPIO1C3_I2SLRCLKTX_NAME, GPIO1C, 6, 1, 0, DEFAULT)
+MUX_CFG(GPIO1C2_I2SLRCLKRX_NAME, GPIO1C, 4, 1, 0, DEFAULT)
+MUX_CFG(GPIO1C1_I2SSCLK_NAME, GPIO1C, 2, 1, 0, DEFAULT)
+MUX_CFG(GPIO1C0_I2SCLK_NAME, GPIO1C, 0, 1, 0, DEFAULT)
+
+//GPIO1D
+MUX_CFG(GPIO1D7_I2C4SCL_NAME, GPIO1D, 14, 1, 0, DEFAULT)
+MUX_CFG(GPIO1D6_I2C4SDA_NAME, GPIO1D, 12, 1, 0, DEFAULT)
+MUX_CFG(GPIO1D5_I2C2SCL_NAME, GPIO1D, 10, 1, 0, DEFAULT)
+MUX_CFG(GPIO1D4_I2C2SDA_NAME, GPIO1D, 8, 1, 0, DEFAULT)
+MUX_CFG(GPIO1D3_I2C1SCL_NAME, GPIO1D, 6, 1, 0, DEFAULT)
+MUX_CFG(GPIO1D2_I2C1SDA_NAME, GPIO1D, 4, 1, 0, DEFAULT)
+MUX_CFG(GPIO1D1_I2C0SCL_NAME, GPIO1D, 2, 1, 0, DEFAULT)
+MUX_CFG(GPIO1D0_I2C0SDA_NAME, GPIO1D, 0, 1, 0, DEFAULT)
+
+//GPIO2A
+MUX_CFG(GPIO2A7_LCDC1DATA7_SMCDATA7_TRACEDATA7_NAME, GPIO2A, 14, 2, 0, DEFAULT)
+MUX_CFG(GPIO2A6_LCDC1DATA6_SMCDATA6_TRACEDATA6_NAME, GPIO2A, 12, 2, 0, DEFAULT)
+MUX_CFG(GPIO2A5_LCDC1DATA5_SMCDATA5_TRACEDATA5_NAME, GPIO2A, 10, 2, 0, DEFAULT)
+MUX_CFG(GPIO2A4_LCDC1DATA4_SMCDATA4_TRACEDATA4_NAME, GPIO2A, 8, 2, 0, DEFAULT)
+MUX_CFG(GPIO2A3_LCDC1DATA3_SMCDATA3_TRACEDATA3_NAME, GPIO2A, 6, 2, 0, DEFAULT)
+MUX_CFG(GPIO2A2_LCDC1DATA2_SMCDATA2_TRACEDATA2_NAME, GPIO2A, 4, 2, 0, DEFAULT)
+MUX_CFG(GPIO2A1_LCDC1DATA1_SMCDATA1_TRACEDATA1_NAME, GPIO2A, 2, 2, 0, DEFAULT)
+MUX_CFG(GPIO2A0_LCDC1DATA0_SMCDATA0_TRACEDATA0_NAME, GPIO2A, 0, 2, 0, DEFAULT)
+
+//GPIO2B
+MUX_CFG(GPIO2B7_LCDC1DATA15_SMCDATA15_TRACEDATA15_NAME, GPIO2B, 14, 2, 0, DEFAULT)
+MUX_CFG(GPIO2B6_LCDC1DATA14_SMCDATA14_TRACEDATA14_NAME, GPIO2B, 12, 2, 0, DEFAULT)
+MUX_CFG(GPIO2B5_LCDC1DATA13_SMCDATA13_TRACEDATA13_NAME, GPIO2B, 10, 2, 0, DEFAULT)
+MUX_CFG(GPIO2B4_LCDC1DATA12_SMCDATA12_TRACEDATA12_NAME, GPIO2B, 8, 2, 0, DEFAULT)
+MUX_CFG(GPIO2B3_LCDC1DATA11_SMCDATA11_TRACEDATA11_NAME, GPIO2B, 6, 2, 0, DEFAULT)
+MUX_CFG(GPIO2B2_LCDC1DATA10_SMCDATA10_TRACEDATA10_NAME, GPIO2B, 4, 2, 0, DEFAULT)
+MUX_CFG(GPIO2B1_LCDC1DATA9_SMCDATA9_TRACEDATA9_NAME, GPIO2B, 2, 2, 0, DEFAULT)
+MUX_CFG(GPIO2B0_LCDC1DATA8_SMCDATA8_TRACEDATA8_NAME, GPIO2B, 0, 2, 0, DEFAULT)
+
+//GPIO2C
+MUX_CFG(GPIO2C7_LCDC1DATA23_SMCADDR7_NAME, GPIO2C, 14, 2, 0, DEFAULT)
+MUX_CFG(GPIO2C6_LCDC1DATA22_SMCADDR6_NAME, GPIO2C, 12, 2, 0, DEFAULT)
+MUX_CFG(GPIO2C5_LCDC1DATA21_SMCADDR5_NAME, GPIO2C, 10, 2, 0, DEFAULT)
+MUX_CFG(GPIO2C4_LCDC1DATA20_SMCADDR4_NAME, GPIO2C, 8, 2, 0, DEFAULT)
+MUX_CFG(GPIO2C3_LCDC1DATA19_SMCADDR3_NAME, GPIO2C, 6, 2, 0, DEFAULT)
+MUX_CFG(GPIO2C2_LCDC1DATA18_SMCADDR2_NAME, GPIO2C, 4, 2, 0, DEFAULT)
+MUX_CFG(GPIO2C1_LCDC1DATA17_SMCADDR1_TRACECTL_NAME, GPIO2C, 2, 2, 0, DEFAULT)
+MUX_CFG(GPIO2C0_LCDC1DATA16_SMCADDR0_TRACECLK_NAME, GPIO2C, 0, 2, 0, DEFAULT)
+
+//GPIO2D
+MUX_CFG(GPIO2D7_TESTCLOCKOUT_NAME, GPIO2D, 14, 1, 0, DEFAULT)
+MUX_CFG(GPIO2D6_SMCCSN1_NAME, GPIO2D, 12, 1, 0, DEFAULT)
+MUX_CFG(GPIO2D5_SMCBLSN1_NAME, GPIO2D, 10, 1, 0, DEFAULT)
+MUX_CFG(GPIO2D4_SMCBLSN0_NAME, GPIO2D, 8, 1, 0, DEFAULT)
+MUX_CFG(GPIO2D3_LCDC1VSYNC_SMCADVN_NAME, GPIO2D, 6, 2, 0, DEFAULT)
+MUX_CFG(GPIO2D2_LCDC1HSYNC_SMCOEN_NAME, GPIO2D, 4, 2, 0, DEFAULT)
+MUX_CFG(GPIO2D1_LCDC1DEN_SMCWEN_NAME, GPIO2D, 2, 2, 0, DEFAULT)
+MUX_CFG(GPIO2D0_LCDC1DCLK_SMCCSN0_NAME, GPIO2D, 0, 2, 0, DEFAULT)
+
+//GPIO3A
+MUX_CFG(GPIO3A7_SDMMC0DATA3_NAME, GPIO3A, 14, 1, 0, DEFAULT)
+MUX_CFG(GPIO3A6_SDMMC0DATA2_NAME, GPIO3A, 12, 1, 0, DEFAULT)
+MUX_CFG(GPIO3A5_SDMMC0DATA1_NAME, GPIO3A, 10, 1, 0, DEFAULT)
+MUX_CFG(GPIO3A4_SDMMC0DATA0_NAME, GPIO3A, 8, 1, 0, DEFAULT)
+MUX_CFG(GPIO3A3_SDMMC0CMD_NAME, GPIO3A, 6, 1, 0, DEFAULT)
+MUX_CFG(GPIO3A2_SDMMC0CLKOUT_NAME, GPIO3A, 4, 1, 0, DEFAULT)
+MUX_CFG(GPIO3A1_SDMMC0PWREN_NAME, GPIO3A, 2, 1, 0, DEFAULT)
+MUX_CFG(GPIO3A0_SDMMC0RSTNOUT_NAME, GPIO3A, 0, 1, 0, DEFAULT)
+
+//GPIO3B
+MUX_CFG(GPIO3B7_CIFDATA11_I2C3SCL_NAME, GPIO3B, 14, 2, 0, DEFAULT)
+MUX_CFG(GPIO3B6_CIFDATA10_I2C3SDA_NAME, GPIO3B, 12, 2, 0, DEFAULT)
+MUX_CFG(GPIO3B5_CIFDATA1_HSADCDATA9_NAME, GPIO3B, 10, 2, 0, DEFAULT)
+MUX_CFG(GPIO3B4_CIFDATA0_HSADCDATA8_NAME, GPIO3B, 8, 2, 0, DEFAULT)
+MUX_CFG(GPIO3B3_CIFCLKOUT_NAME, GPIO3B, 6, 1, 0, DEFAULT)
+MUX_CFG(GPIO3B1_SDMMC0WRITEPRT_NAME, GPIO3B, 2, 1, 0, DEFAULT)
+MUX_CFG(GPIO3B0_SDMMC0DETECTN_NAME, GPIO3B, 0, 1, 0, DEFAULT)
+
+//GPIO3C
+MUX_CFG(GPIO3C7_SDMMC1WRITEPRT_RMIICRS_NAME, GPIO3C, 14, 2, 0, DEFAULT)
+MUX_CFG(GPIO3C6_SDMMC1DETECTN_RMIIRXERR_NAME, GPIO3C, 12, 2, 0, DEFAULT)
+MUX_CFG(GPIO3C5_SDMMC1CLKOUT_RMIICLKOUT_RMIICLKIN_NAME, GPIO3C, 10, 2, 0, DEFAULT)
+MUX_CFG(GPIO3C4_SDMMC1DATA3_RMIIRXD1_NAME, GPIO3C, 8, 2, 0, DEFAULT)
+MUX_CFG(GPIO3C3_SDMMC1DATA2_RMIIRXD0_NAME, GPIO3C, 6, 2, 0, DEFAULT)
+MUX_CFG(GPIO3C2_SDMMC1DATA1_RMIITXD0_NAME, GPIO3C, 4, 2, 0, DEFAULT)
+MUX_CFG(GPIO3C1_SDMMC1DATA0_RMIITXD1_NAME, GPIO3C, 2, 2, 0, DEFAULT)
+MUX_CFG(GPIO3C0_SDMMC1CMD_RMIITXEN_NAME, GPIO3C, 0, 2, 0, DEFAULT)
+
+//GPIO3D
+MUX_CFG(GPIO3D6_PWM3_JTAGTMS_HOSTDRVVBUS_NAME, GPIO3D, 12, 2, 0, DEFAULT)
+MUX_CFG(GPIO3D5_PWM2_JTAGTCK_OTGDRVVBUS_NAME, GPIO3D, 10, 2, 0, DEFAULT)
+MUX_CFG(GPIO3D4_PWM1_JTAGTRSTN_NAME, GPIO3D, 8, 2, 0, DEFAULT)
+MUX_CFG(GPIO3D3_PWM0_NAME, GPIO3D, 6, 1, 0, DEFAULT)
+MUX_CFG(GPIO3D2_SDMMC1INTN_NAME, GPIO3D, 4, 1, 0, DEFAULT)
+MUX_CFG(GPIO3D1_SDMMC1BACKENDPWR_MIIMDCLK_NAME, GPIO3D, 2, 2, 0, DEFAULT)
+MUX_CFG(GPIO3D0_SDMMC1PWREN_MIIMD_NAME, GPIO3D, 0, 2, 0, DEFAULT)
+
#endif
};
rk30_mux_set(&rk30_muxs[i]);
}
+#if defined(CONFIG_ARCH_RK30)
+
#if defined(CONFIG_UART0_RK29) || (CONFIG_RK_DEBUG_UART == 0)
rk30_mux_api_set(GPIO1A1_UART0SOUT_NAME, GPIO1A_UART0_SOUT);
rk30_mux_api_set(GPIO1A0_UART0SIN_NAME, GPIO1A_UART0_SIN);
rk30_mux_api_set(GPIO1D1_CIF1HREF_MIIMDCLK_NAME, GPIO1D_MII_MDCLK);
rk30_mux_api_set(GPIO1D0_CIF1VSYNC_MIIMD_NAME, GPIO1D_MII_MD);
+#endif
+
+#elif defined(CONFIG_ARCH_RK31)
+
#endif
return 0;
\r
static int rk_sensor_iomux(int pin)\r
{ \r
+#if defined(CONFIG_ARCH_RK30)\r
switch (pin)\r
{\r
case RK30_PIN0_PA0: \r
break;\r
}\r
}\r
+#endif\r
return 0;\r
}\r
#define PMEM_CAM_BASE 0 //just for compile ,no meaning\r
#define SD_DETECT_NAME GPIO2A2_SDMMC0DETECTN_NAME
#define SD_DETECT_GPIO_MODE GPIO2L_GPIO2A2
#define SD_DETECT_DET_MODE GPIO2L_SDMMC0_DETECT_N
-#elif defined(CONFIG_ARCH_RK30) || defined(CONFIG_ARCH_RK31)
+#elif defined(CONFIG_ARCH_RK30)
#define SD_DETECT_PIN RK30_PIN3_PB6
#define SD_DETECT_NAME GPIO3B6_SDMMC0DETECTN_NAME
#define SD_DETECT_GPIO_MODE GPIO3B_GPIO3B6
#define SD_DETECT_NAME GPIO1C1_MMC0_DETN_NAME
#define SD_DETECT_GPIO_MODE GPIO1C_GPIO1C1
#define SD_DETECT_DET_MODE GPIO1C_MMC0_DETN
+#elif defined(CONFIG_ARCH_RK31)
+#define SD_DETECT_PIN RK30_PIN3_PB0
+#define SD_DETECT_NAME GPIO3B0_SDMMC0DETECTN_NAME
+#define SD_DETECT_GPIO_MODE GPIO3B_GPIO3B0
+#define SD_DETECT_DET_MODE GPIO3B_SDMMC0DETECTN
#endif
#define RK29_SDMMC_xbw_Debug 0
projects / firefly-linux-kernel-4.4.55.git / commitdiff