ARM: at91: make smc register base soc independent
authorJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Thu, 13 Oct 2011 17:37:09 +0000 (01:37 +0800)
committerJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Mon, 28 Nov 2011 14:50:38 +0000 (22:50 +0800)
now sam9_smc_configure will take as first parameter is the SMC id

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
33 files changed:
arch/arm/mach-at91/at91cap9.c
arch/arm/mach-at91/at91rm9200.c
arch/arm/mach-at91/at91sam9260.c
arch/arm/mach-at91/at91sam9261.c
arch/arm/mach-at91/at91sam9263.c
arch/arm/mach-at91/at91sam9g45.c
arch/arm/mach-at91/at91sam9rl.c
arch/arm/mach-at91/board-cam60.c
arch/arm/mach-at91/board-cap9adk.c
arch/arm/mach-at91/board-cpu9krea.c
arch/arm/mach-at91/board-dt.c
arch/arm/mach-at91/board-neocore926.c
arch/arm/mach-at91/board-pcontrol-g20.c
arch/arm/mach-at91/board-qil-a9260.c
arch/arm/mach-at91/board-sam9-l9260.c
arch/arm/mach-at91/board-sam9260ek.c
arch/arm/mach-at91/board-sam9261ek.c
arch/arm/mach-at91/board-sam9263ek.c
arch/arm/mach-at91/board-sam9g20ek.c
arch/arm/mach-at91/board-sam9m10g45ek.c
arch/arm/mach-at91/board-sam9rlek.c
arch/arm/mach-at91/board-snapper9260.c
arch/arm/mach-at91/board-stamp9g20.c
arch/arm/mach-at91/board-usb-a926x.c
arch/arm/mach-at91/include/mach/at91cap9.h
arch/arm/mach-at91/include/mach/at91sam9260.h
arch/arm/mach-at91/include/mach/at91sam9261.h
arch/arm/mach-at91/include/mach/at91sam9263.h
arch/arm/mach-at91/include/mach/at91sam9_smc.h
arch/arm/mach-at91/include/mach/at91sam9g45.h
arch/arm/mach-at91/include/mach/at91sam9rl.h
arch/arm/mach-at91/sam9_smc.c
arch/arm/mach-at91/sam9_smc.h

index abfe36858a011591d9e68f5013a4d45707e7d451..1ea931274bac1d9397a734dd13a8fc01504951b1 100644 (file)
@@ -28,6 +28,7 @@
 #include "soc.h"
 #include "generic.h"
 #include "clock.h"
+#include "sam9_smc.h"
 
 /* --------------------------------------------------------------------
  *  Clocks
@@ -336,6 +337,7 @@ static void __init at91cap9_map_io(void)
 static void __init at91cap9_ioremap_registers(void)
 {
        at91sam926x_ioremap_pit(AT91CAP9_BASE_PIT);
+       at91sam9_ioremap_smc(0, AT91CAP9_BASE_SMC);
 }
 
 static void __init at91cap9_initialize(void)
index c67d50c9ea2012aa357c864bbfed39dd45033302..c06c14fecba4b995c0269571da1181329c77afbd 100644 (file)
@@ -23,6 +23,7 @@
 #include "soc.h"
 #include "generic.h"
 #include "clock.h"
+#include "sam9_smc.h"
 
 static struct map_desc at91rm9200_io_desc[] __initdata = {
        {
index 0030d5f16ed895da6b4ea87bd78f283a116326f1..fc1f734b80ceb9683839934b3713ab5a79377b59 100644 (file)
@@ -26,6 +26,7 @@
 #include "soc.h"
 #include "generic.h"
 #include "clock.h"
+#include "sam9_smc.h"
 
 /* --------------------------------------------------------------------
  *  Clocks
@@ -328,6 +329,7 @@ static void __init at91sam9260_map_io(void)
 static void __init at91sam9260_ioremap_registers(void)
 {
        at91sam926x_ioremap_pit(AT91SAM9260_BASE_PIT);
+       at91sam9_ioremap_smc(0, AT91SAM9260_BASE_SMC);
 }
 
 static void __init at91sam9260_initialize(void)
index 348d5ae4dee263cce2064815b13586492bfb8dbd..804181aedd9e13164fe011ddfd51131d9f69b8fa 100644 (file)
@@ -25,6 +25,7 @@
 #include "soc.h"
 #include "generic.h"
 #include "clock.h"
+#include "sam9_smc.h"
 
 /* --------------------------------------------------------------------
  *  Clocks
@@ -288,6 +289,7 @@ static void __init at91sam9261_map_io(void)
 static void __init at91sam9261_ioremap_registers(void)
 {
        at91sam926x_ioremap_pit(AT91SAM9261_BASE_PIT);
+       at91sam9_ioremap_smc(0, AT91SAM9261_BASE_SMC);
 }
 
 static void __init at91sam9261_initialize(void)
index 09ccf734c7d7b43170e3c419504fd1d9e754240c..b8f49962e87fe1676f1708511b813b7b8bac3cd3 100644 (file)
@@ -24,6 +24,7 @@
 #include "soc.h"
 #include "generic.h"
 #include "clock.h"
+#include "sam9_smc.h"
 
 /* --------------------------------------------------------------------
  *  Clocks
@@ -306,6 +307,8 @@ static void __init at91sam9263_map_io(void)
 static void __init at91sam9263_ioremap_registers(void)
 {
        at91sam926x_ioremap_pit(AT91SAM9263_BASE_PIT);
+       at91sam9_ioremap_smc(0, AT91SAM9263_BASE_SMC0);
+       at91sam9_ioremap_smc(1, AT91SAM9263_BASE_SMC1);
 }
 
 static void __init at91sam9263_initialize(void)
index aa8b4414f3ed9c8e3f48ebfbbd5114cc3b79c50a..ce3233f22ed1bc2d90fb7fd3b7c18e3bdc178cd4 100644 (file)
@@ -26,6 +26,7 @@
 #include "soc.h"
 #include "generic.h"
 #include "clock.h"
+#include "sam9_smc.h"
 
 /* --------------------------------------------------------------------
  *  Clocks
@@ -341,6 +342,7 @@ static void __init at91sam9g45_map_io(void)
 static void __init at91sam9g45_ioremap_registers(void)
 {
        at91sam926x_ioremap_pit(AT91SAM9G45_BASE_PIT);
+       at91sam9_ioremap_smc(0, AT91SAM9G45_BASE_SMC);
 }
 
 static void __init at91sam9g45_initialize(void)
index 291fc9983cc390ab32717f713281e1361d098de0..1bcccd705296114ef10e86565edff43ee47aa149 100644 (file)
@@ -25,6 +25,7 @@
 #include "soc.h"
 #include "generic.h"
 #include "clock.h"
+#include "sam9_smc.h"
 
 /* --------------------------------------------------------------------
  *  Clocks
@@ -293,6 +294,7 @@ static void __init at91sam9rl_map_io(void)
 static void __init at91sam9rl_ioremap_registers(void)
 {
        at91sam926x_ioremap_pit(AT91SAM9RL_BASE_PIT);
+       at91sam9_ioremap_smc(0, AT91SAM9RL_BASE_SMC);
 }
 
 static void __init at91sam9rl_initialize(void)
index f90cfb32bad2b89815c0ed292b15721dcaa393be..02ded92de5b78deb8819cdf1f9dbaedad80be9e8 100644 (file)
@@ -163,7 +163,7 @@ static struct sam9_smc_config __initdata cam60_nand_smc_config = {
 static void __init cam60_add_device_nand(void)
 {
        /* configure chip-select 3 (NAND) */
-       sam9_smc_configure(3, &cam60_nand_smc_config);
+       sam9_smc_configure(0, 3, &cam60_nand_smc_config);
 
        at91_add_device_nand(&cam60_nand_data);
 }
index 5dffd3be62d25878b52cdbb46150a7d71ad965ac..da2616f20e10880df8be546577a7727a52884dfc 100644 (file)
@@ -212,7 +212,7 @@ static void __init cap9adk_add_device_nand(void)
                cap9adk_nand_smc_config.mode |= AT91_SMC_DBW_8;
 
        /* configure chip-select 3 (NAND) */
-       sam9_smc_configure(3, &cap9adk_nand_smc_config);
+       sam9_smc_configure(0, 3, &cap9adk_nand_smc_config);
 
        at91_add_device_nand(&cap9adk_nand_data);
 }
@@ -282,7 +282,7 @@ static __init void cap9adk_add_device_nor(void)
        at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_VDDIOMSEL_3_3V);
 
        /* configure chip-select 0 (NOR) */
-       sam9_smc_configure(0, &cap9adk_nor_smc_config);
+       sam9_smc_configure(0, 0, &cap9adk_nor_smc_config);
 
        platform_device_register(&cap9adk_nor_flash);
 }
index fc885a4ce243fbedce8461435cf966c859f68886..7dd752e32e2a2bbd4dbe95201bee1514782122b6 100644 (file)
@@ -156,7 +156,7 @@ static struct sam9_smc_config __initdata cpu9krea_nand_smc_config = {
 
 static void __init cpu9krea_add_device_nand(void)
 {
-       sam9_smc_configure(3, &cpu9krea_nand_smc_config);
+       sam9_smc_configure(0, 3, &cpu9krea_nand_smc_config);
        at91_add_device_nand(&cpu9krea_nand_data);
 }
 
@@ -238,7 +238,7 @@ static __init void cpu9krea_add_device_nor(void)
        at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_VDDIOMSEL_3_3V);
 
        /* configure chip-select 0 (NOR) */
-       sam9_smc_configure(0, &cpu9krea_nor_smc_config);
+       sam9_smc_configure(0, 0, &cpu9krea_nor_smc_config);
 
        platform_device_register(&cpu9krea_nor_flash);
 }
index 0b7d327782100efdf1805f901c64c8f12467966c..41d84d9a2316268e1dec9b7b288d42753339db2d 100644 (file)
@@ -82,7 +82,7 @@ static void __init ek_add_device_nand(void)
                ek_nand_smc_config.mode |= AT91_SMC_DBW_8;
 
        /* configure chip-select 3 (NAND) */
-       sam9_smc_configure(3, &ek_nand_smc_config);
+       sam9_smc_configure(0, 3, &ek_nand_smc_config);
 
        at91_add_device_nand(&ek_nand_data);
 }
index ef816c17dc61ebd0a0b9fb0c04ab134912f5b4c7..a9b9adc78c1d6284eacdb43e6b3bd02f79a95654 100644 (file)
@@ -213,7 +213,7 @@ static struct sam9_smc_config __initdata neocore926_nand_smc_config = {
 static void __init neocore926_add_device_nand(void)
 {
        /* configure chip-select 3 (NAND) */
-       sam9_smc_configure(3, &neocore926_nand_smc_config);
+       sam9_smc_configure(0, 3, &neocore926_nand_smc_config);
 
        at91_add_device_nand(&neocore926_nand_data);
 }
index 49e3f699b48e1edff3d73921c178f4426b056896..0e3c632d30ebcb15530286621efbb68e2585bec6 100644 (file)
@@ -96,9 +96,9 @@ static struct sam9_smc_config __initdata pcontrol_smc_config[2] = { {
 static void __init add_device_pcontrol(void)
 {
        /* configure chip-select 4 (IO compatible to 8051  X4 ) */
-       sam9_smc_configure(4, &pcontrol_smc_config[0]);
+       sam9_smc_configure(0, 4, &pcontrol_smc_config[0]);
        /* configure chip-select 7 (FerroRAM 256KiBx16bit MR2A16A  D4 ) */
-       sam9_smc_configure(7, &pcontrol_smc_config[1]);
+       sam9_smc_configure(0, 7, &pcontrol_smc_config[1]);
 }
 
 
index 07421bdb88eaf7f1b985a39c23bac74a7d61dd08..89d44c037291f4a2925c7d1ad6da7a092ffeb601 100644 (file)
@@ -161,7 +161,7 @@ static struct sam9_smc_config __initdata ek_nand_smc_config = {
 static void __init ek_add_device_nand(void)
 {
        /* configure chip-select 3 (NAND) */
-       sam9_smc_configure(3, &ek_nand_smc_config);
+       sam9_smc_configure(0, 3, &ek_nand_smc_config);
 
        at91_add_device_nand(&ek_nand_data);
 }
index 072d53af98d9ebdd594dc9d17efd68c479341976..e0283c57f4674521fa418c7853987b7a45a9d91b 100644 (file)
@@ -162,7 +162,7 @@ static struct sam9_smc_config __initdata ek_nand_smc_config = {
 static void __init ek_add_device_nand(void)
 {
        /* configure chip-select 3 (NAND) */
-       sam9_smc_configure(3, &ek_nand_smc_config);
+       sam9_smc_configure(0, 3, &ek_nand_smc_config);
 
        at91_add_device_nand(&ek_nand_data);
 }
index 4f10181a07822b4a4a93b0634aa668f428951a19..00db0f8e34b6127ae7e697686fe1dde7d8237caa 100644 (file)
@@ -211,7 +211,7 @@ static void __init ek_add_device_nand(void)
                ek_nand_smc_config.mode |= AT91_SMC_DBW_8;
 
        /* configure chip-select 3 (NAND) */
-       sam9_smc_configure(3, &ek_nand_smc_config);
+       sam9_smc_configure(0, 3, &ek_nand_smc_config);
 
        at91_add_device_nand(&ek_nand_data);
 }
index b005b738e8ff7bc6dc4af3c8e173421bd9b234c7..a879b3398f38875ef097acdbb431504d6365ba7f 100644 (file)
@@ -131,7 +131,7 @@ static struct sam9_smc_config __initdata dm9000_smc_config = {
 static void __init ek_add_device_dm9000(void)
 {
        /* Configure chip-select 2 (DM9000) */
-       sam9_smc_configure(2, &dm9000_smc_config);
+       sam9_smc_configure(0, 2, &dm9000_smc_config);
 
        /* Configure Reset signal as output */
        at91_set_gpio_output(AT91_PIN_PC10, 0);
@@ -217,7 +217,7 @@ static void __init ek_add_device_nand(void)
                ek_nand_smc_config.mode |= AT91_SMC_DBW_8;
 
        /* configure chip-select 3 (NAND) */
-       sam9_smc_configure(3, &ek_nand_smc_config);
+       sam9_smc_configure(0, 3, &ek_nand_smc_config);
 
        at91_add_device_nand(&ek_nand_data);
 }
index bccdcf23caa106e392dba97fa4df69f9775a5337..7b25ca10d9d559b47afdc5952566593c461d6d66 100644 (file)
@@ -218,7 +218,7 @@ static void __init ek_add_device_nand(void)
                ek_nand_smc_config.mode |= AT91_SMC_DBW_8;
 
        /* configure chip-select 3 (NAND) */
-       sam9_smc_configure(3, &ek_nand_smc_config);
+       sam9_smc_configure(0, 3, &ek_nand_smc_config);
 
        at91_add_device_nand(&ek_nand_data);
 }
index 64fc75c9d0ac118730cac024eeb94c4d3da17611..0579f069d97ba4a6d7807b61ff19631bc0e77716 100644 (file)
@@ -195,7 +195,7 @@ static void __init ek_add_device_nand(void)
                ek_nand_smc_config.mode |= AT91_SMC_DBW_8;
 
        /* configure chip-select 3 (NAND) */
-       sam9_smc_configure(3, &ek_nand_smc_config);
+       sam9_smc_configure(0, 3, &ek_nand_smc_config);
 
        at91_add_device_nand(&ek_nand_data);
 }
index 92de9127923a6dd0ecf6b61780129a1e3e9d6cf2..3e0d5a91f7826e6ea7dc3a2845984c1a6983e61d 100644 (file)
@@ -175,7 +175,7 @@ static void __init ek_add_device_nand(void)
                ek_nand_smc_config.mode |= AT91_SMC_DBW_8;
 
        /* configure chip-select 3 (NAND) */
-       sam9_smc_configure(3, &ek_nand_smc_config);
+       sam9_smc_configure(0, 3, &ek_nand_smc_config);
 
        at91_add_device_nand(&ek_nand_data);
 }
index b2b748239f365ab77627a6d96a7c442be91fd161..c561edac25b94e7a1682b19d3721fa350573c61b 100644 (file)
@@ -119,7 +119,7 @@ static struct sam9_smc_config __initdata ek_nand_smc_config = {
 static void __init ek_add_device_nand(void)
 {
        /* configure chip-select 3 (NAND) */
-       sam9_smc_configure(3, &ek_nand_smc_config);
+       sam9_smc_configure(0, 3, &ek_nand_smc_config);
 
        at91_add_device_nand(&ek_nand_data);
 }
index 0df01c6e2d0c1b458bc89ac41e46740302eda69b..645d8336468e7514ab589deb286ee5218d0bccbf 100644 (file)
@@ -149,7 +149,7 @@ static struct i2c_board_info __initdata snapper9260_i2c_devices[] = {
 static void __init snapper9260_add_device_nand(void)
 {
        at91_set_A_periph(AT91_PIN_PC14, 0);
-       sam9_smc_configure(3, &snapper9260_nand_smc_config);
+       sam9_smc_configure(0, 3, &snapper9260_nand_smc_config);
        at91_add_device_nand(&snapper9260_nand_data);
 }
 
index 936e5fd7f40696d6db2680fde276344a7e3950cb..f94ac865da53156a5f0702895079a2dc80edc5d2 100644 (file)
@@ -108,7 +108,7 @@ static struct sam9_smc_config __initdata nand_smc_config = {
 static void __init add_device_nand(void)
 {
        /* configure chip-select 3 (NAND) */
-       sam9_smc_configure(3, &nand_smc_config);
+       sam9_smc_configure(0, 3, &nand_smc_config);
 
        at91_add_device_nand(&nand_data);
 }
index 0a20bab21f998ef5597be890f9ed47977d27d19f..6f893cf4d336a666dc7c897f1b4d298e76180948 100644 (file)
@@ -245,9 +245,9 @@ static void __init ek_add_device_nand(void)
 
        /* configure chip-select 3 (NAND) */
        if (machine_is_usb_a9g20())
-               sam9_smc_configure(3, &usb_a9g20_nand_smc_config);
+               sam9_smc_configure(0, 3, &usb_a9g20_nand_smc_config);
        else
-               sam9_smc_configure(3, &usb_a9260_nand_smc_config);
+               sam9_smc_configure(0, 3, &usb_a9260_nand_smc_config);
 
        at91_add_device_nand(&ek_nand_data);
 }
index ad8d298cf8ba86e3744c29ba22b4453d3e942a2e..d7d0b685668fa93ec2c8c92e34d77b9f66e5abd7 100644 (file)
@@ -81,7 +81,6 @@
  */
 #define AT91_BCRAMC    (0xffffe400 - AT91_BASE_SYS)
 #define AT91_DDRSDRC0  (0xffffe600 - AT91_BASE_SYS)
-#define AT91_SMC       (0xffffe800 - AT91_BASE_SYS)
 #define AT91_MATRIX    (0xffffea00 - AT91_BASE_SYS)
 #define AT91_CCFG      (0xffffeb10 - AT91_BASE_SYS)
 #define AT91_DBGU      (0xffffee00 - AT91_BASE_SYS)
@@ -96,6 +95,7 @@
 
 #define AT91CAP9_BASE_ECC      0xffffe200
 #define AT91CAP9_BASE_DMA      0xffffec00
+#define AT91CAP9_BASE_SMC      0xffffe800
 #define AT91CAP9_BASE_PIOA     0xfffff200
 #define AT91CAP9_BASE_PIOB     0xfffff400
 #define AT91CAP9_BASE_PIOC     0xfffff600
index b8c85dc4abcea26fe7b9131318ef8ba14b2e8149..e55ab6abcdbfed81d6e45b075233703f07047fa0 100644 (file)
@@ -81,7 +81,6 @@
  * System Peripherals (offset from AT91_BASE_SYS)
  */
 #define AT91_SDRAMC0   (0xffffea00 - AT91_BASE_SYS)
-#define AT91_SMC       (0xffffec00 - AT91_BASE_SYS)
 #define AT91_MATRIX    (0xffffee00 - AT91_BASE_SYS)
 #define AT91_CCFG      (0xffffef10 - AT91_BASE_SYS)
 #define AT91_AIC       (0xfffff000 - AT91_BASE_SYS)
@@ -93,6 +92,7 @@
 #define AT91_GPBR      (0xfffffd50 - AT91_BASE_SYS)
 
 #define AT91SAM9260_BASE_ECC   0xffffe800
+#define AT91SAM9260_BASE_SMC   0xffffec00
 #define AT91SAM9260_BASE_PIOA  0xfffff400
 #define AT91SAM9260_BASE_PIOB  0xfffff600
 #define AT91SAM9260_BASE_PIOC  0xfffff800
index 0dccaff5212e9b4c726a25ffb12204536b258db8..1ea2d6b06c8167dd9d25644068498a4c651c3b45 100644 (file)
@@ -66,7 +66,6 @@
  * System Peripherals (offset from AT91_BASE_SYS)
  */
 #define AT91_SDRAMC0   (0xffffea00 - AT91_BASE_SYS)
-#define AT91_SMC       (0xffffec00 - AT91_BASE_SYS)
 #define AT91_MATRIX    (0xffffee00 - AT91_BASE_SYS)
 #define AT91_AIC       (0xfffff000 - AT91_BASE_SYS)
 #define AT91_DBGU      (0xfffff200 - AT91_BASE_SYS)
@@ -76,6 +75,7 @@
 #define AT91_WDT       (0xfffffd40 - AT91_BASE_SYS)
 #define AT91_GPBR      (0xfffffd50 - AT91_BASE_SYS)
 
+#define AT91SAM9261_BASE_SMC   0xffffec00
 #define AT91SAM9261_BASE_PIOA  0xfffff400
 #define AT91SAM9261_BASE_PIOB  0xfffff600
 #define AT91SAM9261_BASE_PIOC  0xfffff800
index 735408e6d2e64f1bfaf967262b4b67b33fdd6aa1..b827ff7974b290d631f38c67e286bf746f0ef5a6 100644 (file)
@@ -75,9 +75,7 @@
  * System Peripherals (offset from AT91_BASE_SYS)
  */
 #define AT91_SDRAMC0   (0xffffe200 - AT91_BASE_SYS)
-#define AT91_SMC0      (0xffffe400 - AT91_BASE_SYS)
 #define AT91_SDRAMC1   (0xffffe800 - AT91_BASE_SYS)
-#define AT91_SMC1      (0xffffea00 - AT91_BASE_SYS)
 #define AT91_MATRIX    (0xffffec00 - AT91_BASE_SYS)
 #define AT91_CCFG      (0xffffed10 - AT91_BASE_SYS)
 #define AT91_DBGU      (0xffffee00 - AT91_BASE_SYS)
@@ -89,7 +87,9 @@
 #define AT91_GPBR      (0xfffffd60 - AT91_BASE_SYS)
 
 #define AT91SAM9263_BASE_ECC0  0xffffe000
+#define AT91SAM9263_BASE_SMC0  0xffffe400
 #define AT91SAM9263_BASE_ECC1  0xffffe600
+#define AT91SAM9263_BASE_SMC1  0xffffea00
 #define AT91SAM9263_BASE_PIOA  0xfffff200
 #define AT91SAM9263_BASE_PIOB  0xfffff400
 #define AT91SAM9263_BASE_PIOC  0xfffff600
index 57de6207e57e566842ea53cb2113b27796ce3c47..eb18a70fa6472d32881af288909d144d988f39ce 100644 (file)
@@ -16,7 +16,9 @@
 #ifndef AT91SAM9_SMC_H
 #define AT91SAM9_SMC_H
 
-#define AT91_SMC_SETUP(n)      (AT91_SMC + 0x00 + ((n)*0x10))  /* Setup Register for CS n */
+#include <mach/cpu.h>
+
+#define AT91_SMC_SETUP         0x00                            /* Setup Register for CS n */
 #define                AT91_SMC_NWESETUP       (0x3f << 0)                     /* NWE Setup Length */
 #define                        AT91_SMC_NWESETUP_(x)   ((x) << 0)
 #define                AT91_SMC_NCS_WRSETUP    (0x3f << 8)                     /* NCS Setup Length in Write Access */
@@ -26,7 +28,7 @@
 #define                AT91_SMC_NCS_RDSETUP    (0x3f << 24)                    /* NCS Setup Length in Read Access */
 #define                        AT91_SMC_NCS_RDSETUP_(x)        ((x) << 24)
 
-#define AT91_SMC_PULSE(n)      (AT91_SMC + 0x04 + ((n)*0x10))  /* Pulse Register for CS n */
+#define AT91_SMC_PULSE         0x04                            /* Pulse Register for CS n */
 #define                AT91_SMC_NWEPULSE       (0x7f <<  0)                    /* NWE Pulse Length */
 #define                        AT91_SMC_NWEPULSE_(x)   ((x) << 0)
 #define                AT91_SMC_NCS_WRPULSE    (0x7f <<  8)                    /* NCS Pulse Length in Write Access */
 #define                AT91_SMC_NCS_RDPULSE    (0x7f << 24)                    /* NCS Pulse Length in Read Access */
 #define                        AT91_SMC_NCS_RDPULSE_(x)((x) << 24)
 
-#define AT91_SMC_CYCLE(n)      (AT91_SMC + 0x08 + ((n)*0x10))  /* Cycle Register for CS n */
+#define AT91_SMC_CYCLE         0x08                            /* Cycle Register for CS n */
 #define                AT91_SMC_NWECYCLE       (0x1ff << 0 )                   /* Total Write Cycle Length */
 #define                        AT91_SMC_NWECYCLE_(x)   ((x) << 0)
 #define                AT91_SMC_NRDCYCLE       (0x1ff << 16)                   /* Total Read Cycle Length */
 #define                        AT91_SMC_NRDCYCLE_(x)   ((x) << 16)
 
-#define AT91_SMC_MODE(n)       (AT91_SMC + 0x0c + ((n)*0x10))  /* Mode Register for CS n */
+#define AT91_SMC_MODE          0x0c                            /* Mode Register for CS n */
 #define                AT91_SMC_READMODE       (1 <<  0)                       /* Read Mode */
 #define                AT91_SMC_WRITEMODE      (1 <<  1)                       /* Write Mode */
 #define                AT91_SMC_EXNWMODE       (3 <<  4)                       /* NWAIT Mode */
 #define                        AT91_SMC_PS_16                  (2 << 28)
 #define                        AT91_SMC_PS_32                  (3 << 28)
 
-#if defined(AT91_SMC1)         /* The AT91SAM9263 has 2 Static Memory contollers */
-#define AT91_SMC1_SETUP(n)     (AT91_SMC1 + 0x00 + ((n)*0x10)) /* Setup Register for CS n */
-#define AT91_SMC1_PULSE(n)     (AT91_SMC1 + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */
-#define AT91_SMC1_CYCLE(n)     (AT91_SMC1 + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */
-#define AT91_SMC1_MODE(n)      (AT91_SMC1 + 0x0c + ((n)*0x10)) /* Mode Register for CS n */
-#endif
-
 #endif
index ba609f3872fd66a7673852ccc2fce06c4a0f3159..ac051d427e6be6cab5e055c43c11f4f5689d2ac1 100644 (file)
@@ -88,7 +88,6 @@
  */
 #define AT91_DDRSDRC1  (0xffffe400 - AT91_BASE_SYS)
 #define AT91_DDRSDRC0  (0xffffe600 - AT91_BASE_SYS)
-#define AT91_SMC       (0xffffe800 - AT91_BASE_SYS)
 #define AT91_MATRIX    (0xffffea00 - AT91_BASE_SYS)
 #define AT91_DBGU      (0xffffee00 - AT91_BASE_SYS)
 #define AT91_AIC       (0xfffff000 - AT91_BASE_SYS)
 
 #define AT91SAM9G45_BASE_ECC   0xffffe200
 #define AT91SAM9G45_BASE_DMA   0xffffec00
+#define AT91SAM9G45_BASE_SMC   0xffffe800
 #define AT91SAM9G45_BASE_PIOA  0xfffff200
 #define AT91SAM9G45_BASE_PIOB  0xfffff400
 #define AT91SAM9G45_BASE_PIOC  0xfffff600
index bab09a745d2b2833874bb4e4014880f233fe48b9..846139ddf06a6f6d653373381fabb01a84d7de09 100644 (file)
@@ -70,7 +70,6 @@
  * System Peripherals (offset from AT91_BASE_SYS)
  */
 #define AT91_SDRAMC0   (0xffffea00 - AT91_BASE_SYS)
-#define AT91_SMC       (0xffffec00 - AT91_BASE_SYS)
 #define AT91_MATRIX    (0xffffee00 - AT91_BASE_SYS)
 #define AT91_CCFG      (0xffffef10 - AT91_BASE_SYS)
 #define AT91_AIC       (0xfffff000 - AT91_BASE_SYS)
@@ -85,6 +84,7 @@
 
 #define AT91SAM9RL_BASE_DMA    0xffffe600
 #define AT91SAM9RL_BASE_ECC    0xffffe800
+#define AT91SAM9RL_BASE_SMC    0xffffec00
 #define AT91SAM9RL_BASE_PIOA   0xfffff400
 #define AT91SAM9RL_BASE_PIOB   0xfffff600
 #define AT91SAM9RL_BASE_PIOC   0xfffff800
index 5eab6aa621d070dd251411c6523ade62a3402962..8294783b679d8aa58579a9d0a149a1a79bb1af6a 100644 (file)
 
 #include <linux/module.h>
 #include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
 
 #include <mach/at91sam9_smc.h>
 
 #include "sam9_smc.h"
 
-void __init sam9_smc_configure(int cs, struct sam9_smc_config* config)
+
+#define AT91_SMC_CS(id, n)     (smc_base_addr[id] + ((n) * 0x10))
+
+static void __iomem *smc_base_addr[2];
+
+static void __init sam9_smc_cs_configure(void __iomem *base, struct sam9_smc_config* config)
 {
+
        /* Setup register */
-       at91_sys_write(AT91_SMC_SETUP(cs),
-                 AT91_SMC_NWESETUP_(config->nwe_setup)
-               | AT91_SMC_NCS_WRSETUP_(config->ncs_write_setup)
-               | AT91_SMC_NRDSETUP_(config->nrd_setup)
-               | AT91_SMC_NCS_RDSETUP_(config->ncs_read_setup)
-       );
+       __raw_writel(AT91_SMC_NWESETUP_(config->nwe_setup)
+                  | AT91_SMC_NCS_WRSETUP_(config->ncs_write_setup)
+                  | AT91_SMC_NRDSETUP_(config->nrd_setup)
+                  | AT91_SMC_NCS_RDSETUP_(config->ncs_read_setup),
+                  base + AT91_SMC_SETUP);
 
        /* Pulse register */
-       at91_sys_write(AT91_SMC_PULSE(cs),
-                 AT91_SMC_NWEPULSE_(config->nwe_pulse)
-               | AT91_SMC_NCS_WRPULSE_(config->ncs_write_pulse)
-                | AT91_SMC_NRDPULSE_(config->nrd_pulse)
-               | AT91_SMC_NCS_RDPULSE_(config->ncs_read_pulse)
-       );
+       __raw_writel(AT91_SMC_NWEPULSE_(config->nwe_pulse)
+                  | AT91_SMC_NCS_WRPULSE_(config->ncs_write_pulse)
+                  | AT91_SMC_NRDPULSE_(config->nrd_pulse)
+                  | AT91_SMC_NCS_RDPULSE_(config->ncs_read_pulse),
+                  base + AT91_SMC_PULSE);
 
        /* Cycle register */
-       at91_sys_write(AT91_SMC_CYCLE(cs),
-                 AT91_SMC_NWECYCLE_(config->write_cycle)
-               | AT91_SMC_NRDCYCLE_(config->read_cycle)
-       );
+       __raw_writel(AT91_SMC_NWECYCLE_(config->write_cycle)
+                  | AT91_SMC_NRDCYCLE_(config->read_cycle),
+                  base + AT91_SMC_CYCLE);
 
        /* Mode register */
-       at91_sys_write(AT91_SMC_MODE(cs),
-                 config->mode
-               | AT91_SMC_TDF_(config->tdf_cycles)
-       );
+       __raw_writel(config->mode
+                  | AT91_SMC_TDF_(config->tdf_cycles),
+                  base + AT91_SMC_MODE);
+}
+
+void __init sam9_smc_configure(int id, int cs, struct sam9_smc_config* config)
+{
+       sam9_smc_cs_configure(AT91_SMC_CS(id, cs), config);
+}
+
+void __init at91sam9_ioremap_smc(int id, u32 addr)
+{
+       if (id > 1) {
+               pr_warn("%s: id > 2\n", __func__);
+               return;
+       }
+       smc_base_addr[id] = ioremap(addr, 512);
+       if (!smc_base_addr[id])
+               pr_warn("Impossible to ioremap smc.%d 0x%x\n", id, addr);
 }
index bf72cfb3455baf2ebb224eff017e4ecdab2fbea2..039c5ce17aec5cb2c8b01625041b7924f5bc7e3c 100644 (file)
@@ -30,4 +30,5 @@ struct sam9_smc_config {
        u8 tdf_cycles:4;
 };
 
-extern void __init sam9_smc_configure(int cs, struct sam9_smc_config* config);
+extern void __init sam9_smc_configure(int id, int cs, struct sam9_smc_config* config);
+extern void __init at91sam9_ioremap_smc(int id, u32 addr);