[ARM] mm: add memory type for inner-writeback

For streaming-style operations (e.g., software rendering of graphics
surfaces shared with non-coherent DMA devices), the cost of performing
L2 cache maintenance can exceed the benefit of having the larger cache
(this is particularly true for OUTER_CACHE configurations like the ARM
PL2x0).

This change uses the currently-unused mapping 5 (TEX[0]=1, C=0, B=1)
in the tex remapping tables as an inner-writeback-write-allocate, outer
non-cacheable memory type, so that this mapping will be available to
clients which will benefit from the reduced L2 maintenance.

Change-Id: Iaec3314a304eab2215100d991b1e880b676ac906
Signed-off-by: Gary King <gking@nvidia.com>

diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h
index e90b167ea8484002fffb0121e7a2d61726851fe6..73ee18b1a054b266d4b3959512d012986d16311a 100644 (file)
--- a/arch/arm/include/asm/pgtable.h
+++ b/arch/arm/include/asm/pgtable.h
@@ -184,6 +184,7 @@ extern void __pgd_error(const char *file, int line, unsigned long val);
 #define L_PTE_MT_DEV_NONSHARED (0x0c << 2)     /* 1100 */
 #define L_PTE_MT_DEV_WC                (0x09 << 2)     /* 1001 */
 #define L_PTE_MT_DEV_CACHED    (0x0b << 2)     /* 1011 */
+#define L_PTE_MT_INNER_WB      (0x05 << 2)     /* 0101 (armv6, armv7) */
 #define L_PTE_MT_MASK          (0x0f << 2)
 
 #ifndef __ASSEMBLY__
@@ -325,6 +326,8 @@ extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
 #define pgprot_dmacoherent(prot) \
        __pgprot_modify(prot, L_PTE_MT_MASK|L_PTE_EXEC, L_PTE_MT_UNCACHED)
 #endif
+#define pgprot_inner_writeback(prot) \
+       __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_INNER_WB)
 
 #define pmd_none(pmd)          (!pmd_val(pmd))
 #define pmd_present(pmd)       (pmd_val(pmd))

diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S
index 7d63beaf97456541c0718c84b475b844194156e6..6da85e3f0632280717584b9d5e9059a3f58f0b13 100644 (file)
--- a/arch/arm/mm/proc-macros.S
+++ b/arch/arm/mm/proc-macros.S
@@ -107,7 +107,7 @@
        .long   PTE_CACHEABLE                                   @ L_PTE_MT_WRITETHROUGH
        .long   PTE_CACHEABLE | PTE_BUFFERABLE                  @ L_PTE_MT_WRITEBACK
        .long   PTE_BUFFERABLE                                  @ L_PTE_MT_DEV_SHARED
-       .long   0x00                                            @ unused
+       .long   PTE_EXT_TEX(4) | PTE_BUFFERABLE                 @ L_PTE_MT_INNER_WB
        .long   0x00                                            @ L_PTE_MT_MINICACHE (not present)
        .long   PTE_EXT_TEX(1) | PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEALLOC
        .long   0x00                                            @ unused

diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 750175e95ab0ea4180e0e1c5071a30fdd41e1703..e0028e5bef13d11920a912629b95f53281c0b097 100644 (file)
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -294,11 +294,11 @@ __v7_setup:
         *   NS1 = PRRR[19] = 1         - normal shareable property
         *   NOS = PRRR[24+n] = 1       - not outer shareable
         */
-       ldr     r5, =0xff0a81a8                 @ PRRR
+       ldr     r5, =0xff0a89a8                 @ PRRR
 #ifdef CONFIG_SMP
-       ldr     r6, =0xc0e0c0e0                 @ NMRR
+       ldr     r6, =0xc0e0c4e0                 @ NMRR
 #else
-       ldr     r6, =0x40e040e0
+       ldr     r6, =0x40e044e0
 #endif
        mcr     p15, 0, r5, c10, c2, 0          @ write PRRR
        mcr     p15, 0, r6, c10, c2, 1          @ write NMRR

diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S
index 361a51e4903063ffc82f6831f3bee47e3a957860..b5dc61a22bf2a387e8f1503c2291343d72818a96 100644 (file)
--- a/arch/arm/mm/proc-xsc3.S
+++ b/arch/arm/mm/proc-xsc3.S
@@ -373,7 +373,7 @@ cpu_xsc3_mt_table:
        .long   PTE_EXT_TEX(5) | PTE_CACHEABLE                  @ L_PTE_MT_WRITETHROUGH
        .long   PTE_CACHEABLE | PTE_BUFFERABLE                  @ L_PTE_MT_WRITEBACK
        .long   PTE_EXT_TEX(1) | PTE_BUFFERABLE                 @ L_PTE_MT_DEV_SHARED
-       .long   0x00                                            @ unused
+       .long   PTE_EXT_TEX(4) | PTE_BUFFERABLE                 @ L_PTE_MT_INNER_WB (not present?)
        .long   0x00                                            @ L_PTE_MT_MINICACHE (not present)
        .long   PTE_EXT_TEX(5) | PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEALLOC (not present?)
        .long   0x00                                            @ unused

diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S
index 14075979bcbac1a4bfe7ae346e97058de819d448..69518395e710cd1f0d3baba44a3913e7fd95262e 100644 (file)
--- a/arch/arm/mm/proc-xscale.S
+++ b/arch/arm/mm/proc-xscale.S
@@ -469,7 +469,7 @@ cpu_xscale_mt_table:
        .long   PTE_CACHEABLE                                   @ L_PTE_MT_WRITETHROUGH
        .long   PTE_CACHEABLE | PTE_BUFFERABLE                  @ L_PTE_MT_WRITEBACK
        .long   PTE_EXT_TEX(1) | PTE_BUFFERABLE                 @ L_PTE_MT_DEV_SHARED
-       .long   0x00                                            @ unused
+       .long   PTE_EXT_TEX(1) | PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_INNER_WB
        .long   PTE_EXT_TEX(1) | PTE_CACHEABLE                  @ L_PTE_MT_MINICACHE
        .long   PTE_EXT_TEX(1) | PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEALLOC
        .long   0x00                                            @ unused