rk3168: dvfs-rk3066b.c set some variables to static

diff --git a/arch/arm/mach-rk30/dvfs-rk3066b.c b/arch/arm/mach-rk30/dvfs-rk3066b.c
index f7eb4c825c242139d03152caa954be1f0862bfb6..b188f2330437d5c4a5ce21ffaff0a9b392a95e12 100755 (executable)
--- a/arch/arm/mach-rk30/dvfs-rk3066b.c
+++ b/arch/arm/mach-rk30/dvfs-rk3066b.c
@@ -36,8 +36,8 @@
 #define CLK_LOOPS_JIFFY_REF 11996091ULL\r
 #define CLK_LOOPS_RATE_REF (1200) //Mhz\r
 #define CLK_LOOPS_RECALC(new_rate)  div_u64(CLK_LOOPS_JIFFY_REF*(new_rate),CLK_LOOPS_RATE_REF*MHZ)\r
-struct clk *clk_cpu = NULL, *clk_cpu_div = NULL, *arm_pll_clk = NULL, *general_pll_clk = NULL;\r
-unsigned long lpj_24m;\r
+static struct clk *clk_cpu = NULL, *clk_cpu_div = NULL, *arm_pll_clk = NULL, *general_pll_clk = NULL;\r
+static unsigned long lpj_24m;\r
 \r
 struct gate_delay_table {\r
        unsigned long arm_perf;\r
@@ -221,7 +221,7 @@ int uoc_val = 0;
 #define SIZE_VP_TABLE          ARRAY_SIZE(dvfs_vp_table)\r
 #define SIZE_ARM_FREQ_TABLE    10\r
 static struct cycle_by_rate rate_cycle[SIZE_ARM_FREQ_TABLE];\r
-int size_dvfs_arm_table = 0;\r
+static int size_dvfs_arm_table = 0;\r
 \r
 static struct clk_node *dvfs_clk_cpu;\r
 static struct vd_node vd_core;\r
@@ -333,7 +333,7 @@ struct dvfs_uoc_val_table {
        unsigned long   volt_arm;\r
        struct dvfs_volt_uoc    vu_list[SIZE_SUPPORT_LOG_VOLT];\r
 };\r
-struct dvfs_uoc_val_table dvfs_uoc_val_list[SIZE_ARM_FREQ_TABLE];\r
+static struct dvfs_uoc_val_table dvfs_uoc_val_list[SIZE_ARM_FREQ_TABLE];\r
 \r
 static int dvfs_get_uoc_val_init(unsigned long *p_volt_arm_new, unsigned long *p_volt_log_new, \r
                unsigned long rate_khz);\r