+++ /dev/null
-#include <linux/delay.h>\r
-#include <linux/i2c.h>\r
-#include <linux/hdmi.h>\r
-#include <linux/slab.h>\r
-\r
-#include "anx7150.h"\r
-#include "anx7150_hw.h"\r
-//#ifdef ITU656\r
-struct ANX7150_video_timingtype ANX7150_video_timingtype_table =\r
-{\r
- //640x480p-60hz\r
- {0x20/*H_RES_LOW*/, 0x03/*H_RES_HIGH*/,0x80 /*ACT_PIX_LOW*/,0x02 /*ACT_PIX_HIGH*/,\r
- 0x60/*HSYNC_WIDTH_LOW*/,0x00 /*HSYNC_WIDTH_HIGH*/,0x30 /*H_BP_LOW*/,0x00 /*H_BP_HIGH*/,\r
- 0xe0/*ACT_LINE_LOW*/, 0x01/*ACT_LINE_HIGH*/,0x02 /*VSYNC_WIDTH*/, 0x21/*V_BP_LINE*/,\r
- 0x0a/*V_FP_LINE*/,0x10 /*H_FP_LOW*/, 0x00/*H_FP_HIGH*/,\r
- ANX7150_Progressive, ANX7150_Neg_Hsync_pol, ANX7150_Neg_Vsync_pol},\r
- //720x480p-60hz\r
- {0x5a/*H_RES_LOW*/,0x03 /*H_RES_HIGH*/,0xd0/*ACT_PIX_LOW*/, 0x02/*ACT_PIX_HIGH*/,\r
- 0x3e/*HSYNC_WIDTH_LOW*/, 0x00/*HSYNC_WIDTH_HIGH*/, 0x3c/*H_BP_LOW*/, 0x00/*H_BP_HIGH*/,\r
- 0xe0/*ACT_LINE_LOW*/, 0x01/*ACT_LINE_HIGH*/, 0x06/*VSYNC_WIDTH*/, 0x1e/*V_BP_LINE*/,\r
- 0x09/*V_FP_LINE*/, 0x10/*H_FP_LOW*/, 0x00/*H_FP_HIGH*/,\r
- ANX7150_Progressive, ANX7150_Neg_Hsync_pol, ANX7150_Neg_Vsync_pol},\r
- //720p-60hz\r
- {0x72/*H_RES_LOW*/, 0x06/*H_RES_HIGH*/, 0x00/*ACT_PIX_LOW*/, 0x05/*ACT_PIX_HIGH*/,\r
- 0x28/*HSYNC_WIDTH_LOW*/, 0x00/*HSYNC_WIDTH_HIGH*/, 0xdc/*H_BP_LOW*/, 0x00/*H_BP_HIGH*/,\r
- 0xd0/*ACT_LINE_LOW*/, 0x02/*ACT_LINE_HIGH*/, 0x05/*VSYNC_WIDTH*/, 0x14/*V_BP_LINE*/,\r
- 0x05/*V_FP_LINE*/, 0x6e/*H_FP_LOW*/, 0x00/*H_FP_HIGH*/,\r
- ANX7150_Progressive, ANX7150_Pos_Hsync_pol, ANX7150_Pos_Vsync_pol},\r
- //1080i-60hz\r
- {0x98/*H_RES_LOW*/, 0x08/*H_RES_HIGH*/, 0x80/*ACT_PIX_LOW*/, 0x07/*ACT_PIX_HIGH*/,\r
- 0x2c/*HSYNC_WIDTH_LOW*/, 0x00/*HSYNC_WIDTH_HIGH*/, 0x94/*H_BP_LOW*/, 0x00/*H_BP_HIGH*/,\r
- 0x38/*ACT_LINE_LOW*/, 0x04/*ACT_LINE_HIGH*/, 0x05/*VSYNC_WIDTH*/, 0x0f/*V_BP_LINE*/,\r
- 0x02/*V_FP_LINE*/, 0x58/*H_FP_LOW*/, 0x00/*H_FP_HIGH*/,\r
- ANX7150_Interlace, ANX7150_Pos_Hsync_pol, ANX7150_Pos_Vsync_pol},\r
- //720x480i-60hz\r
- {0x5a/*H_RES_LOW*/,0x03 /*H_RES_HIGH*/,0xd0/*ACT_PIX_LOW*/, 0x02/*ACT_PIX_HIGH*/,\r
- 0x3e/*HSYNC_WIDTH_LOW*/, 0x00/*HSYNC_WIDTH_HIGH*/, 0x39/*H_BP_LOW*/, 0x00/*H_BP_HIGH*/,\r
- 0xe0/*ACT_LINE_LOW*/, 0x01/*ACT_LINE_HIGH*/, 0x03/*VSYNC_WIDTH*/, 0x0f/*V_BP_LINE*/,\r
- 0x04/*V_FP_LINE*/, 0x13/*H_FP_LOW*/, 0x00/*H_FP_HIGH*/,\r
- ANX7150_Interlace, ANX7150_Neg_Hsync_pol, ANX7150_Neg_Vsync_pol}, //update\r
- //1080p-60hz\r
- {0x98/*H_RES_LOW*/, 0x08/*H_RES_HIGH*/, 0x80/*ACT_PIX_LOW*/, 0x07/*ACT_PIX_HIGH*/,\r
- 0x2c/*HSYNC_WIDTH_LOW*/, 0x00/*HSYNC_WIDTH_HIGH*/, 0x94/*H_BP_LOW*/, 0x00/*H_BP_HIGH*/,\r
- 0x38/*ACT_LINE_LOW*/, 0x04/*ACT_LINE_HIGH*/, 0x05/*VSYNC_WIDTH*/, 0x24/*V_BP_LINE*/,\r
- 0x04/*V_FP_LINE*/, 0x58/*H_FP_LOW*/, 0x00/*H_FP_HIGH*/,\r
- ANX7150_Interlace, ANX7150_Pos_Hsync_pol, ANX7150_Pos_Vsync_pol},\r
- //576p-50hz\r
- {0x60/*H_RES_LOW*/,0x03 /*H_RES_HIGH*/,0xd0 /*ACT_PIX_LOW*/, 0x02/*ACT_PIX_HIGH*/,\r
- 0x40/*HSYNC_WIDTH_LOW*/, 0x00/*HSYNC_WIDTH_HIGH*/, 0x44/*H_BP_LOW*/,0x00 /*H_BP_HIGH*/,\r
- 0x40/*ACT_LINE_LOW*/, 0x02/*ACT_LINE_HIGH*/, 0x05/*VSYNC_WIDTH*/, 0x27/*V_BP_LINE*/,\r
- 0x05/*V_FP_LINE*/, 0x0c/*H_FP_LOW*/, 0x00/*H_FP_HIGH*/,\r
- ANX7150_Progressive, ANX7150_Neg_Hsync_pol, ANX7150_Neg_Vsync_pol},\r
- //720p-50hz\r
- {0xbc/*H_RES_LOW*/, 0x07/*H_RES_HIGH*/, 0x00/*ACT_PIX_LOW*/, 0x05/*ACT_PIX_HIGH*/,\r
- 0x28/*HSYNC_WIDTH_LOW*/, 0x00/*HSYNC_WIDTH_HIGH*/, 0xdc/*H_BP_LOW*/, 0x00/*H_BP_HIGH*/,\r
- 0xd0/*ACT_LINE_LOW*/, 0x02/*ACT_LINE_HIGH*/, 0x05/*VSYNC_WIDTH*/, 0x14/*V_BP_LINE*/,\r
- 0x05/*V_FP_LINE*/, 0xb8/*H_FP_LOW*/, 0x01/*H_FP_HIGH*/,\r
- ANX7150_Progressive, ANX7150_Pos_Hsync_pol, ANX7150_Pos_Vsync_pol},\r
- //1080i-50hz\r
- {0x50/*H_RES_LOW*/, 0x0a/*H_RES_HIGH*/, 0x80/*ACT_PIX_LOW*/, 0x07/*ACT_PIX_HIGH*/,\r
- 0x2c/*HSYNC_WIDTH_LOW*/, 0x00/*HSYNC_WIDTH_HIGH*/, 0x94/*H_BP_LOW*/, 0x00/*H_BP_HIGH*/,\r
- 0x38/*ACT_LINE_LOW*/, 0x04/*ACT_LINE_HIGH*/, 0x05/*VSYNC_WIDTH*/, 0x0f/*V_BP_LINE*/,\r
- 0x02/*V_FP_LINE*/, 0x10/*H_FP_LOW*/, 0x02/*H_FP_HIGH*/,\r
- ANX7150_Interlace, ANX7150_Pos_Hsync_pol, ANX7150_Pos_Vsync_pol},\r
- //576i-50hz\r
- {0x60/*H_RES_LOW*/,0x03 /*H_RES_HIGH*/,0xd0 /*ACT_PIX_LOW*/, 0x02/*ACT_PIX_HIGH*/,\r
- 0x3f/*HSYNC_WIDTH_LOW*/, 0x00/*HSYNC_WIDTH_HIGH*/, 0x45/*H_BP_LOW*/,0x00 /*H_BP_HIGH*/,\r
- 0x40/*ACT_LINE_LOW*/,0x02 /*ACT_LINE_HIGH*/, 0x03/*VSYNC_WIDTH*/, 0x13/*V_BP_LINE*/,\r
- 0x02/*V_FP_LINE*/, 0x0c/*H_FP_LOW*/, 0x00/*H_FP_HIGH*/,\r
- ANX7150_Interlace, ANX7150_Neg_Hsync_pol, ANX7150_Neg_Vsync_pol},\r
- \r
- //1080p-50hz\r
- {0x50/*H_RES_LOW*/, 0x0a/*H_RES_HIGH*/, 0x80/*ACT_PIX_LOW*/, 0x07/*ACT_PIX_HIGH*/,\r
- 0x2c/*HSYNC_WIDTH_LOW*/, 0x00/*HSYNC_WIDTH_HIGH*/, 0x94/*H_BP_LOW*/, 0x00/*H_BP_HIGH*/,\r
- 0x38/*ACT_LINE_LOW*/, 0x04/*ACT_LINE_HIGH*/, 0x05/*VSYNC_WIDTH*/, 0x24/*V_BP_LINE*/,\r
- 0x04/*V_FP_LINE*/, 0x10/*H_FP_LOW*/, 0x02/*H_FP_HIGH*/,\r
- ANX7150_Interlace, ANX7150_Pos_Hsync_pol, ANX7150_Pos_Vsync_pol},\r
-};\r
-//#endif\r
-int anx7150_mass_read_need_delay = 0;\r
-\r
-u8 g_video_format = 0x00;\r
-u8 g_audio_format = 0x00;\r
-\r
-\r
-u8 timer_slot = 0;\r
-u8 *ANX7150_EDID_Buf = NULL;\r
-u8 ANX7150_avi_data[19];//, ANX7150_avi_checksum;\r
-u8 ANX7150_system_state = HDMI_INITIAL;\r
-u8 spdif_error_cnt = 0x00;\r
-u8 misc_reset_needed;\r
-u8 ANX7150_stdaddr,ANX7150_stdreg,ANX7150_ext_block_num;\r
-u8 ANX7150_svd_length,ANX7150_sau_length;\r
-u8 ANX7150_edid_dtd[18];\r
-u32 ANX7150_edid_length;\r
-ANX7150_edid_result_4_system ANX7150_edid_result;\r
-\r
-u8 ANX7150_ddc_fifo_full;\r
-u8 ANX7150_ddc_progress;\r
-u8 ANX7150_hdcp_auth_en;\r
-//u8 ANX7150_bksv_ready; //replace by srm_checked xy 01.09\r
-u8 ANX7150_HDCP_enable;\r
-u8 ANX7150_ksv_srm_pass;\r
-u8 ANX7150_hdcp_bcaps;\r
-u8 ANX7150_hdcp_bstatus[2];\r
-u8 ANX7150_srm_checked;\r
-u8 ANX7150_hdcp_auth_pass;\r
-u8 ANX7150_avmute_enable;\r
-u8 ANX7150_send_blue_screen;\r
-u8 ANX7150_hdcp_encryption;\r
-u8 ANX7150_hdcp_init_done;\r
-u8 ANX7150_hdcp_wait_100ms_needed;\r
-u8 ANX7150_auth_fully_pass;\r
-u8 ANX7150_parse_edid_done;//060714 XY\r
-//u8 testen;\r
-//u8 ANX7150_avi_data[19], ANX7150_avi_checksum;\r
-u8 ANX7150_hdcp_auth_fail_counter ;\r
-\r
-u8 ANX7150_video_format_config;\r
-u8 ANX7150_emb_sync_mode,ANX7150_de_gen_en,ANX7150_demux_yc_en,ANX7150_ddr_bus_mode;\r
-u8 ANX7150_ddr_edge,ANX7150_ycmux_u8_sel;\r
-u8 ANX7150_system_config_done;\r
-u8 ANX7150_RGBorYCbCr; //modified by zy 060814\r
-u8 ANX7150_in_pix_rpt,ANX7150_tx_pix_rpt;\r
-u8 ANX7150_in_pix_rpt_bkp,ANX7150_tx_pix_rpt_bkp;\r
-u8 ANX7150_video_timing_id;\r
-u8 ANX7150_pix_rpt_set_by_sys;\r
-u8 ANX7150_video_timing_parameter[18];\r
-u8 switch_value_sw_backup,switch_value_pc_backup;\r
-u8 switch_value,bist_switch_value_pc;\r
-u8 ANX7150_new_csc,ANX7150_new_vid_id,ANX7150_new_HW_interface;\r
-u8 ANX7150_INT_Done;\r
-\r
-audio_config_struct s_ANX7150_audio_config;\r
-config_packets s_ANX7150_packet_config;\r
-\r
-u8 FREQ_MCLK; //0X72:0X50 u82:0\r
-//000b:Fm = 128*Fs\r
-//001b:Fm = 256*Fs\r
-//010b:Fm = 384*Fs\r
-//011b:Fm = 512*Fs\r
-u8 ANX7150_audio_clock_edge;\r
-int ANX7150_DDC_Mass_Read(struct i2c_client *client, u8 *buf, u16 len);\r
-\r
-int anx7150_detect_device(struct anx7150_pdata *anx)\r
-{\r
- int i, rc = 0; \r
- char d1, d2;\r
- \r
- for (i=0; i<10; i++) \r
- { \r
- if((rc = anx7150_i2c_read_p0_reg(anx->client, ANX7150_DEV_IDL_REG, &d1)) < 0) \r
- continue;\r
- if((rc = anx7150_i2c_read_p0_reg(anx->client, ANX7150_DEV_IDH_REG, &d2)) < 0) \r
- continue;\r
- if (d1 == 0x50 && d2 == 0x71)\r
- { \r
- hdmi_dbg(&anx->client->dev, "anx7150 detected!\n");\r
- return 0;\r
- } \r
- } \r
- \r
- hdmi_dbg(&anx->client->dev, "anx7150 not detected");\r
- return -1;\r
-}\r
-u8 ANX7150_Get_System_State(void)\r
-{\r
- return ANX7150_system_state;\r
-}\r
-void ANX7150_Set_System_State(struct i2c_client *client, u8 new_state)\r
-{\r
- ANX7150_system_state = new_state;\r
- switch (ANX7150_system_state)\r
- {\r
- case HDMI_INITIAL:\r
- hdmi_dbg(&client->dev, "INITIAL\n");\r
- break;\r
- case WAIT_HOTPLUG:\r
- hdmi_dbg(&client->dev, "WAIT_HOTPLUG\n");\r
- break;\r
- case READ_PARSE_EDID:\r
- hdmi_dbg(&client->dev, "READ_PARSE_EDID\n");\r
- break;\r
- case WAIT_RX_SENSE:\r
- hdmi_dbg(&client->dev, "WAIT_RX_SENSE\n");\r
- break;\r
- case WAIT_HDMI_ENABLE:\r
- hdmi_dbg(&client->dev, "WAIT_HDMI_ENABLE\n");\r
- break;\r
- case SYSTEM_CONFIG:\r
- hdmi_dbg(&client->dev, "SYSTEM_CONFIG\n");\r
- break;\r
- case CONFIG_VIDEO:\r
- dev_info(&client->dev, "CONFIG_VIDEO\n");\r
- break;\r
- case CONFIG_AUDIO:\r
- hdmi_dbg(&client->dev, "CONFIG_AUDIO\n");\r
- break;\r
- case CONFIG_PACKETS:\r
- hdmi_dbg(&client->dev, "CONFIG_PACKETS\n");\r
- break;\r
- case HDCP_AUTHENTICATION:\r
- hdmi_dbg(&client->dev, "HDCP_AUTHENTICATION\n");\r
- break;\r
- ////////////////////////////////////////////////\r
- // System ANX7150_RESET_LINK is kept for RX clock recovery error case, not used in normal case.\r
- case RESET_LINK:\r
- hdmi_dbg(&client->dev, "RESET_LINK\n");\r
- break;\r
- ////////////////////////////////////////////////\r
- case PLAY_BACK:\r
- dev_info(&client->dev, "PLAY_BACK\n");\r
- break;\r
- default:\r
- hdmi_dbg(&client->dev, "unknown state\n");\r
- break;\r
- }\r
-}\r
-\r
-int anx7150_get_hpd(struct i2c_client *client)\r
-{\r
- int rc = 0;\r
- char sys_ctl3, intr_state, sys_state, hpd_state;\r
- \r
- if((rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_CTRL3_REG, &sys_ctl3)) < 0)\r
- return rc;\r
- if(sys_ctl3 & ANX7150_SYS_CTRL3_PWON_ALL)\r
- {\r
- if((rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_STATE_REG, &sys_state)) < 0)\r
- return rc;\r
- hpd_state = (sys_state & ANX7150_SYS_STATE_HP)? 1:0;\r
- }\r
- else\r
- {\r
- if((rc = anx7150_i2c_read_p0_reg(client, ANX7150_INTR_STATE_REG, &intr_state)) < 0)\r
- return rc;\r
- hpd_state = (intr_state)? 1:0;\r
- }\r
- return hpd_state;\r
-}\r
-static int anx7150_get_interrupt_status(struct i2c_client *client, struct anx7150_interrupt_s *interrupt_staus)\r
-{\r
- int rc = 0;\r
- u8 int_s1;\r
- u8 int_s2;\r
- u8 int_s3;\r
- \r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_INTR1_STATUS_REG, &int_s1);//jack wen, for spdif input from SD0.\r
- rc |= anx7150_i2c_write_p0_reg(client, ANX7150_INTR1_STATUS_REG, &int_s1);//power down all, 090630\r
- rc |= anx7150_i2c_read_p0_reg(client, ANX7150_INTR2_STATUS_REG, &int_s2);//jack wen, for spdif input from SD0.\r
- rc |= anx7150_i2c_write_p0_reg(client, ANX7150_INTR2_STATUS_REG, &int_s2);//power down all, 090630\r
- rc |= anx7150_i2c_read_p0_reg(client, ANX7150_INTR3_STATUS_REG, &int_s3);//jack wen, for spdif input from SD0.\r
- rc |= anx7150_i2c_write_p0_reg(client, ANX7150_INTR3_STATUS_REG, &int_s3);//power down all, 090630\r
-\r
- interrupt_staus->hotplug_change = (int_s1 & ANX7150_INTR1_STATUS_HP_CHG) ? 1 : 0;\r
- interrupt_staus->video_format_change = (int_s3 & ANX7150_INTR3_STATUS_VIDF_CHG) ? 1 : 0;\r
- interrupt_staus->auth_done = (int_s2 & ANX7150_INTR2_STATUS_AUTH_DONE) ? 1 : 0;\r
- interrupt_staus->auth_state_change = (int_s2 & ANX7150_INTR2_STATUS_AUTH_CHG) ? 1 : 0;\r
- interrupt_staus->pll_lock_change = (int_s2 & ANX7150_INTR2_STATUS_PLLLOCK_CHG) ? 1 : 0;\r
- interrupt_staus->rx_sense_change = (int_s3 & ANX7150_INTR3_STATUS_RXSEN_CHG) ? 1 : 0;\r
- interrupt_staus->HDCP_link_change = (int_s2 & ANX7150_INTR2_STATUS_HDCPLINK_CHK) ? 1 : 0;\r
- interrupt_staus->audio_clk_change = (int_s3 & ANX7150_INTR3_STATUS_AUDCLK_CHG) ? 1 : 0;\r
- interrupt_staus->audio_FIFO_overrun = (int_s1 & ANX7150_INTR1_STATUS_AFIFO_OVER) ? 1 : 0;\r
- interrupt_staus->SPDIF_error = (int_s1 & ANX7150_INTR1_STATUS_SPDIF_ERR) ? 1 : 0;\r
- interrupt_staus->SPDIF_bi_phase_error = ((int_s3 & ANX7150_INTR3_STATUS_SPDIFBI_ERR) ? 1 : 0) \r
- || ((int_s3 & ANX7150_INTR3_STATUS_SPDIF_UNSTBL) ? 1 : 0);\r
- return 0;\r
-}\r
-static void ANX7150_Variable_Initial(void)\r
-{\r
- u8 i;\r
-\r
- ANX7150_hdcp_auth_en = 0;\r
- ANX7150_ksv_srm_pass =0;\r
- ANX7150_srm_checked = 0;\r
- ANX7150_hdcp_auth_pass = 0;\r
- ANX7150_avmute_enable = 1;\r
- ANX7150_hdcp_auth_fail_counter =0;\r
- ANX7150_hdcp_encryption = 0;\r
- ANX7150_send_blue_screen = 0;\r
- ANX7150_hdcp_init_done = 0;\r
- ANX7150_hdcp_wait_100ms_needed = 1;\r
- ANX7150_auth_fully_pass = 0;\r
- timer_slot = 0;\r
- //********************for video config**************\r
- ANX7150_video_timing_id = 0;\r
- ANX7150_in_pix_rpt = 0;\r
- ANX7150_tx_pix_rpt = 0;\r
- ANX7150_new_csc = 0;\r
- ANX7150_new_vid_id = 0;\r
- ANX7150_new_HW_interface = 0;\r
- //********************end of video config*********\r
-\r
- //********************for edid parse***********\r
- ANX7150_edid_result.is_HDMI = 1;\r
- ANX7150_edid_result.ycbcr422_supported = 0;\r
- ANX7150_edid_result.ycbcr444_supported = 0;\r
- ANX7150_edid_result.supported_720p_60Hz = 0;\r
- ANX7150_edid_result.supported_720p_50Hz = 0;\r
- ANX7150_edid_result.supported_576p_50Hz = 0;\r
- ANX7150_edid_result.supported_576i_50Hz = 0;\r
- ANX7150_edid_result.supported_1080i_60Hz = 0;\r
- ANX7150_edid_result.supported_1080i_50Hz = 0;\r
- ANX7150_edid_result.supported_640x480p_60Hz = 0;\r
- ANX7150_edid_result.supported_720x480p_60Hz = 0;\r
- ANX7150_edid_result.supported_720x480i_60Hz = 0;\r
- ANX7150_edid_result.edid_errcode = 0;\r
- ANX7150_edid_result.SpeakerFormat = 0;\r
- for (i = 0; i < 8; i ++)\r
- {\r
- ANX7150_edid_result.AudioChannel[i] = 0;\r
- ANX7150_edid_result.AudioFormat[i] = 0;\r
- ANX7150_edid_result.AudioFs[i] = 0;\r
- ANX7150_edid_result.AudioLength[i] = 0;\r
- }\r
- //********************end of edid**************\r
-\r
- s_ANX7150_packet_config.packets_need_config = 0x03; //new avi infoframe\r
- s_ANX7150_packet_config.avi_info.type = 0x82;\r
- s_ANX7150_packet_config.avi_info.version = 0x02;\r
- s_ANX7150_packet_config.avi_info.length = 0x0d;\r
- s_ANX7150_packet_config.avi_info.pb_u8[1] = 0x21;//YCbCr422\r
- s_ANX7150_packet_config.avi_info.pb_u8[2] = 0x08;\r
- s_ANX7150_packet_config.avi_info.pb_u8[3] = 0x00;\r
- s_ANX7150_packet_config.avi_info.pb_u8[4] = 0x00;\r
- s_ANX7150_packet_config.avi_info.pb_u8[5] = 0x00;\r
- s_ANX7150_packet_config.avi_info.pb_u8[6] = 0x00;\r
- s_ANX7150_packet_config.avi_info.pb_u8[7] = 0x00;\r
- s_ANX7150_packet_config.avi_info.pb_u8[8] = 0x00;\r
- s_ANX7150_packet_config.avi_info.pb_u8[9] = 0x00;\r
- s_ANX7150_packet_config.avi_info.pb_u8[10] = 0x00;\r
- s_ANX7150_packet_config.avi_info.pb_u8[11] = 0x00;\r
- s_ANX7150_packet_config.avi_info.pb_u8[12] = 0x00;\r
- s_ANX7150_packet_config.avi_info.pb_u8[13] = 0x00;\r
-\r
- // audio infoframe\r
- s_ANX7150_packet_config.audio_info.type = 0x84;\r
- s_ANX7150_packet_config.audio_info.version = 0x01;\r
- s_ANX7150_packet_config.audio_info.length = 0x0a;\r
- s_ANX7150_packet_config.audio_info.pb_u8[1] = 0x00; //zy 061123 for ATC\r
- s_ANX7150_packet_config.audio_info.pb_u8[2] = 0x00;\r
- s_ANX7150_packet_config.audio_info.pb_u8[3] = 0x00;\r
- s_ANX7150_packet_config.audio_info.pb_u8[4] = 0x00;\r
- s_ANX7150_packet_config.audio_info.pb_u8[5] = 0x00;\r
- s_ANX7150_packet_config.audio_info.pb_u8[6] = 0x00;\r
- s_ANX7150_packet_config.audio_info.pb_u8[7] = 0x00;\r
- s_ANX7150_packet_config.audio_info.pb_u8[8] = 0x00;\r
- s_ANX7150_packet_config.audio_info.pb_u8[9] = 0x00;\r
- s_ANX7150_packet_config.audio_info.pb_u8[10] = 0x00;\r
-\r
- ANX7150_INT_Done = 0;\r
-}\r
-static void ANX7150_HW_Interface_Variable_Initial(void)\r
-{\r
- u8 c;\r
-\r
- ANX7150_video_format_config = 0x00;\r
- ANX7150_RGBorYCbCr = 0x00;\r
- ANX7150_ddr_edge = ANX7150_IDCK_EDGE_DDR;\r
-\r
- c = 0;\r
- c = (ANX7150_I2S_CH0_ENABLE << 2) | (ANX7150_I2S_CH1_ENABLE << 3) |\r
- (ANX7150_I2S_CH2_ENABLE << 4) | (ANX7150_I2S_CH3_ENABLE << 5);\r
- s_ANX7150_audio_config.audio_type = ANX7150_AUD_HW_INTERFACE; // input I2S\r
- s_ANX7150_audio_config.down_sample = 0x00;\r
- s_ANX7150_audio_config.i2s_config.audio_channel = c;//0x04;\r
- s_ANX7150_audio_config.i2s_config.Channel_status1 =0x00;\r
- s_ANX7150_audio_config.i2s_config.Channel_status1 = 0x00;\r
- s_ANX7150_audio_config.i2s_config.Channel_status2 = 0x00;\r
- s_ANX7150_audio_config.i2s_config.Channel_status3 = 0x00;\r
- s_ANX7150_audio_config.i2s_config.Channel_status4 = 0x00;//0x02;//48k\r
- s_ANX7150_audio_config.i2s_config.Channel_status5 = ANX7150_I2S_WORD_LENGTH;//0x0b;\r
- s_ANX7150_audio_config.audio_layout = 0x00;\r
-\r
- c = (ANX7150_I2S_SHIFT_CTRL << 3) | (ANX7150_I2S_DIR_CTRL << 2) |\r
- (ANX7150_I2S_WS_POL << 1) | ANX7150_I2S_JUST_CTRL;\r
- s_ANX7150_audio_config.i2s_config.i2s_format = c;//0x00;\r
-\r
- FREQ_MCLK = ANX7150_MCLK_Fs_RELATION;//set the relation of MCLK and WS\r
- ANX7150_audio_clock_edge = ANX7150_AUD_CLK_EDGE;\r
-\r
-\r
-}\r
-static int anx7150_hardware_initial(struct i2c_client *client)\r
-{\r
- int rc = 0;\r
- char c = 0;\r
- \r
- //clear HDCP_HPD_RST\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_CTRL2_REG, &c);\r
- c |= (0x01);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL2_REG, &c);\r
-\r
- mdelay(10);\r
-\r
- c &= (~0x01);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL2_REG, &c);\r
- \r
- //Power on I2C\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_CTRL3_REG, &c);\r
- c |= (ANX7150_SYS_CTRL3_I2C_PWON);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL3_REG, &c);\r
-\r
- c = 0x00;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL2_REG, &c);\r
- c= 0x00;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_SRST_REG, &c);\r
-\r
- //clear HDCP_HPD_RST\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_CTRL1_REG, &c);\r
- c &= (0xbf);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL1_REG, &c);\r
-\r
- //Power on Audio capture and Video capture module clock\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_PD_REG, &c);\r
- c |= (0x06);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_PD_REG, &c);\r
-\r
- //Enable auto set clock range for video PLL\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_CHIP_CTRL_REG, &c);\r
- c &= (0x00);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_CHIP_CTRL_REG, &c);\r
-\r
- //Set registers value of Blue Screen when HDCP authentication failed--RGB mode,green field\r
- c = 0x10;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_BLUESCREEN0_REG, &c);\r
- c = 0xeb;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_BLUESCREEN1_REG, &c);\r
- c = 0x10;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_BLUESCREEN2_REG, &c);\r
-\r
- //ANX7150_i2c_read_p0_reg(ANX7150_TMDS_CLKCH_CONFIG_REG, &c);\r
- //ANX7150_i2c_write_p0_reg(ANX7150_TMDS_CLKCH_CONFIG_REG, (c | 0x80));\r
-\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_PLL_CTRL0_REG, &c);\r
- c = 0x00;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_PLL_CTRL0_REG, &c);\r
-\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_CHIP_DEBUG1_CTRL_REG, &c);\r
- c |= (0x08);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_CHIP_DEBUG1_CTRL_REG, &c);\r
-\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_PLL_TX_AMP, &c);//jack wen\r
- c |= (0x01);\r
-\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_PLL_TX_AMP, &c); //TMDS swing\r
-\r
- c = 0x00;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_PLL_CTRL1_REG, &c); //Added for PLL unlock issue in high temperature - Feiw\r
- //if (ANX7150_AUD_HW_INTERFACE == 0x02) //jack wen, spdif\r
-\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_I2S_CTRL_REG, &c);//jack wen, for spdif input from SD0.\r
- c &= (0xef);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_I2S_CTRL_REG, &c);\r
-\r
- c = 0xc7;\r
- rc = anx7150_i2c_write_p0_reg(client, 0xE1, &c);\r
-\r
- //ANX7150_i2c_read_p0_reg(ANX7150_SYS_CTRL1_REG, &c);\r
- c = 0x00;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL1_REG, &c);//power down HDCP, 090630\r
-\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_CTRL3_REG, &c);//jack wen, for spdif input from SD0.\r
- c &= (0xfe);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL3_REG, &c);//power down all, 090630\r
-\r
- return rc;\r
-}\r
-\r
-int anx7150_rst_ddcchannel(struct i2c_client *client)\r
-{\r
- int rc = 0;\r
- char c;\r
- //Reset the DDC channel\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_CTRL2_REG, &c);\r
-\r
- c |= (ANX7150_SYS_CTRL2_DDC_RST);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL2_REG, &c);\r
-\r
- c &= (~ANX7150_SYS_CTRL2_DDC_RST);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL2_REG, &c);\r
-\r
-\r
- c = 0x00;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_DDC_ACC_CMD_REG, &c);//abort current operation\r
-\r
- c = 0x06;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_DDC_ACC_CMD_REG, &c);//reset I2C command\r
-\r
- //Clear FIFO\r
- c = 0x05;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_DDC_ACC_CMD_REG, &c);//reset I2C command\r
-\r
- return rc;\r
-}\r
-\r
-int anx7150_initial(struct i2c_client *client)
-{
- ANX7150_Variable_Initial(); //simon\r
- ANX7150_HW_Interface_Variable_Initial(); //simon\r
- \r
- anx7150_hardware_initial(client); //simon\r
- return 0;
-}
-int anx7150_unplug(struct i2c_client *client)\r
-{\r
- int rc = 0;\r
- char c;\r
- dev_info(&client->dev, "anx7150 unplug\n");\r
- \r
- //wen HDCP CTS\r
- ANX7150_Variable_Initial(); //simon\r
- ANX7150_HW_Interface_Variable_Initial(); //simon\r
- \r
- rc = anx7150_hardware_initial(client); //simon\r
- if(rc < 0)\r
- dev_err(&client->dev, "%s>> i2c transfer err\n", __func__);\r
-\r
- c = 0x00;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c); //simon\r
- if(rc < 0)\r
- dev_err(&client->dev, "%s>> i2c transfer err\n", __func__);\r
- //wen HDCP CTS\r
- ANX7150_hdcp_wait_100ms_needed = 1;\r
- ANX7150_auth_fully_pass = 0;\r
-\r
- // clear ANX7150_parse_edid_done & ANX7150_system_config_done\r
- ANX7150_parse_edid_done = 0;\r
-// ANX7150_system_config_done = 0;\r
- ANX7150_srm_checked = 0;\r
-\r
- return rc;\r
-}\r
-int anx7150_plug(struct i2c_client *client)\r
-{\r
- int rc = 0;\r
- char c;\r
-\r
- dev_info(&client->dev, "anx7150 plug\n");\r
-\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_CTRL3_REG, &c);\r
- c |= (0x01);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL3_REG, &c);//power up all, 090630\r
-\r
- //disable audio & video & hdcp & TMDS and init begin\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- c &= (~ANX7150_HDMI_AUDCTRL1_IN_EN);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
-\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
- c &= (~ANX7150_VID_CTRL_IN_EN);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
-\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_TMDS_CLKCH_CONFIG_REG, &c);\r
- c &= (~ANX7150_TMDS_CLKCH_MUTE);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_TMDS_CLKCH_CONFIG_REG, &c);\r
-\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
- c &= (~ANX7150_HDCP_CTRL0_HW_AUTHEN);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
-\r
- ANX7150_Variable_Initial();\r
- //disable video & audio & hdcp & TMDS and init end\r
-\r
- \r
- //Power on chip and select DVI mode\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_CTRL1_REG, &c);\r
- c |= (0x05);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL1_REG, &c);// cwz change 0x01 -> 0x05\r
-\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_CTRL1_REG, &c);\r
- c &= (0xfd);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL1_REG, &c);\r
-\r
- //D("ANX7150 is set to DVI mode\n");\r
- rc = anx7150_rst_ddcchannel(client);\r
- //Initial Interrupt\r
- // disable video/audio CLK,Format change and before config video. 060713 xy\r
-\r
- c = 0x04;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_INTR1_MASK_REG, &c);\r
-\r
- c = 0x00;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_INTR2_MASK_REG, &c);\r
-\r
- c = 0x00;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_INTR3_MASK_REG, &c);\r
-\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_INTR1_STATUS_REG, &c);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_INTR1_STATUS_REG, &c);\r
-\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_INTR2_STATUS_REG, &c);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_INTR2_STATUS_REG, &c);\r
-\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_INTR3_STATUS_REG, &c);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_INTR3_STATUS_REG, &c);\r
-\r
- c = 0x00;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_INTR_CTRL_REG, &c);\r
-\r
- // clear ANX7150_parse_edid_done & ANX7150_system_config_done\r
- ANX7150_parse_edid_done = 0;\r
-// ANX7150_system_config_done = 0;\r
- ANX7150_srm_checked = 0;\r
-\r
- return rc;\r
-}\r
-\r
-int anx7150_set_avmute(struct i2c_client *client)\r
-{\r
- int rc = 0;\r
- char c;\r
-\r
- c = 0x01;\r
- if((rc = anx7150_i2c_write_p1_reg(client, ANX7150_GNRL_CTRL_PKT_REG, &c)) < 0)\r
- return rc;\r
- \r
- if((rc = anx7150_i2c_read_p1_reg(client, ANX7150_INFO_PKTCTRL1_REG, &c)) < 0)\r
- return rc;\r
- c |= (0x0c);\r
- if((rc = anx7150_i2c_write_p1_reg(client, ANX7150_INFO_PKTCTRL1_REG, &c)) < 0)\r
- return rc;\r
- ANX7150_avmute_enable = 1;\r
-\r
- return rc;\r
-}\r
-int anx7150_clear_avmute(struct i2c_client *client)\r
-{\r
- int rc = 0;\r
- char c;\r
-\r
- c = 0x02;\r
- if((rc = anx7150_i2c_write_p1_reg(client, ANX7150_GNRL_CTRL_PKT_REG, &c)) < 0)\r
- return rc;\r
- \r
- if((rc = anx7150_i2c_read_p1_reg(client, ANX7150_INFO_PKTCTRL1_REG, &c)) < 0)\r
- return rc;\r
- c |= (0x0c);\r
- if((rc = anx7150_i2c_write_p1_reg(client, ANX7150_INFO_PKTCTRL1_REG, &c)) < 0)\r
- return rc;\r
- ANX7150_avmute_enable = 0;\r
-// D("@@@@@@@@@@@@@@@@@@@@ANX7150_Clear_AVMute\n");\r
- return rc;\r
-\r
-}\r
-\r
-static int anx7150_video_format_change(struct i2c_client *client)\r
-{\r
- int rc;\r
- char c;\r
- \r
- hdmi_dbg(&client->dev, "after video format change int \n");\r
- \r
- rc = anx7150_set_avmute(client);//wen\r
- //stop HDCP and reset DDC\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
- c &= (~ANX7150_HDCP_CTRL0_HW_AUTHEN);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
- \r
- rc = anx7150_rst_ddcchannel(client);\r
- \r
- //when format change, clear this reg to avoid error in package config\r
- c = 0x00;\r
- rc = anx7150_i2c_write_p1_reg(client, ANX7150_INFO_PKTCTRL1_REG, &c);\r
- c = 0x00;\r
- rc = anx7150_i2c_write_p1_reg(client, ANX7150_INFO_PKTCTRL2_REG, &c);\r
- //xy 11.06 when format change, need system config again\r
- // ANX7150_system_config_done = 0;\r
- return rc;\r
-}\r
-static int anx7150_blue_screen_disable(struct i2c_client *client)\r
-{\r
- int rc = 0;\r
- char c;\r
-\r
- if((rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_CTRL1_REG, &c)) < 0)\r
- return rc;\r
- c &= (0xfb);\r
- if((rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_CTRL1_REG, &c)) < 0)\r
- return rc;\r
-\r
- ANX7150_send_blue_screen = 0;\r
- \r
- return rc;\r
-}\r
-static int anx7150_blue_screen_enable(struct i2c_client *client)\r
-{\r
- int rc = 0;\r
- char c;\r
- \r
- if((rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_CTRL1_REG, &c)) < 0)\r
- return rc;\r
- c |= (ANX7150_HDCP_CTRL1_BLUE_SCREEN_EN);\r
- if((rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_CTRL1_REG, &c)) < 0)\r
- return rc;\r
- ANX7150_send_blue_screen = 1;\r
-\r
- return rc;\r
-}\r
-static int anx7150_hdcp_encryption_enable(struct i2c_client *client)\r
-{\r
- int rc = 0;\r
- u8 c;\r
- \r
- if((rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c)) < 0)\r
- return rc;\r
- c |= (ANX7150_HDCP_CTRL0_ENC_EN);\r
- if((rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c)) < 0)\r
- return rc;\r
- ANX7150_hdcp_encryption = 1;\r
-\r
- return rc;\r
-}\r
-\r
-static int anx7150_hdcp_encryption_disable(struct i2c_client *client)\r
-{\r
- int rc = 0;\r
- u8 c;\r
- \r
- if((rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c)) < 0)\r
- return rc;\r
- c &= (0xfb);\r
- if((rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c)) < 0)\r
- return rc;\r
-\r
- ANX7150_hdcp_encryption = 0;\r
-\r
- return rc;\r
-}\r
-\r
-static int anx7150_auth_done(struct i2c_client *client)\r
-{\r
- int rc = 0;\r
- char c;\r
-\r
- hdmi_dbg(&client->dev, "anx7150 auth done\n");\r
- \r
- if((rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_STATUS_REG, &c)) < 0)\r
- return rc;\r
- \r
- if (c & ANX7150_HDCP_STATUS_AUTH_PASS)\r
- {\r
- hdmi_dbg(&client->dev, "ANX7150_Authentication pass in Auth_Done\n");\r
- anx7150_blue_screen_disable(client);\r
- ANX7150_hdcp_auth_pass = 1;\r
- ANX7150_hdcp_auth_fail_counter = 0;\r
- }\r
- else\r
- {\r
- hdmi_dbg(&client->dev, "ANX7150_Authentication failed\n");\r
- ANX7150_hdcp_wait_100ms_needed = 1;\r
- ANX7150_auth_fully_pass = 0;\r
- ANX7150_hdcp_auth_pass = 0;\r
- ANX7150_hdcp_auth_fail_counter ++;\r
- if (ANX7150_hdcp_auth_fail_counter >= ANX7150_HDCP_FAIL_THRESHOLD)\r
- {\r
- ANX7150_hdcp_auth_fail_counter = 0;\r
- //ANX7150_bksv_ready = 0;\r
- // TODO: Reset link;\r
- rc = anx7150_blue_screen_enable(client);\r
- rc = anx7150_hdcp_encryption_disable(client);\r
- //disable audio\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- c &= (~ANX7150_HDMI_AUDCTRL1_IN_EN);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- }\r
- }\r
- return rc;\r
-}\r
-\r
-static int anx7150_clean_hdcp(struct i2c_client *client)\r
-{\r
- int rc = 0;\r
- char c;\r
- //mute TMDS link\r
- //ANX7150_i2c_read_p0_reg(ANX7150_TMDS_CLKCH_CONFIG_REG, &c);//jack wen\r
- //ANX7150_i2c_write_p0_reg(ANX7150_TMDS_CLKCH_CONFIG_REG, c & (~ANX7150_TMDS_CLKCH_MUTE));\r
-\r
- //Disable hardware HDCP\r
-\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
- c &= (~ANX7150_HDCP_CTRL0_HW_AUTHEN);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
- \r
- //Reset HDCP logic\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_SRST_REG, &c);\r
- c |= (ANX7150_SRST_HDCP_RST);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_SRST_REG, &c);\r
- c &= (~ANX7150_SRST_HDCP_RST);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_SRST_REG, &c);\r
-\r
- //Set ReAuth\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
- c |= (ANX7150_HDCP_CTRL0_RE_AUTH);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
- c &= (~ANX7150_HDCP_CTRL0_RE_AUTH);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
- ANX7150_hdcp_auth_en = 0;\r
- //ANX7150_bksv_ready = 0;\r
- ANX7150_hdcp_auth_pass = 0;\r
- ANX7150_hdcp_auth_fail_counter =0 ;\r
- ANX7150_hdcp_encryption = 0;\r
- ANX7150_send_blue_screen = 0;\r
- ANX7150_hdcp_init_done = 0;\r
- ANX7150_hdcp_wait_100ms_needed = 1;\r
- ANX7150_auth_fully_pass = 0;\r
- ANX7150_srm_checked = 0;\r
- rc = anx7150_rst_ddcchannel(client);\r
-\r
- return rc;\r
-}\r
-static int anx7150_auth_change(struct i2c_client *client)\r
-{\r
- int rc = 0;\r
- char c;\r
- \r
- int state = ANX7150_Get_System_State();\r
- \r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_STATUS_REG, &c);\r
- if (c & ANX7150_HDCP_STATUS_AUTH_PASS)\r
- {\r
- ANX7150_hdcp_auth_pass = 1;\r
- hdmi_dbg(&client->dev, "ANX7150_Authentication pass in Auth_Change\n");\r
- }\r
- else\r
- {\r
- rc = anx7150_set_avmute(client); //wen\r
- hdmi_dbg(&client->dev, "ANX7150_Authentication failed_by_Auth_change\n");\r
- ANX7150_hdcp_auth_pass = 0;\r
- ANX7150_hdcp_wait_100ms_needed = 1;\r
- ANX7150_auth_fully_pass = 0;\r
- ANX7150_hdcp_init_done=0; //wen HDCP CTS\r
- ANX7150_hdcp_auth_en=0; //wen HDCP CTS\r
- rc = anx7150_hdcp_encryption_disable(client);\r
- if (state == PLAY_BACK)\r
- {\r
- ANX7150_auth_fully_pass = 0;\r
- //disable audio\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- c &= (~ANX7150_HDMI_AUDCTRL1_IN_EN);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- rc = anx7150_clean_hdcp(client); //wen updated for Changhong TV\r
- }\r
- }\r
- return rc;\r
-}\r
-int ANX7150_GET_RECIVER_TYPE(void)\r
-{
- return ANX7150_edid_result.is_HDMI;
-}\r
-static int anx7150_audio_clk_change(struct i2c_client *client)\r
-{\r
- int rc = 0;\r
- char c;\r
-\r
- hdmi_dbg(&client->dev, "ANX7150: audio clock changed interrupt,disable audio.\n");\r
- // disable audio\r
-\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- c &= (~ANX7150_HDMI_AUDCTRL1_IN_EN);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
-\r
- //xy 11.06 when format change, need system config again\r
-// ANX7150_system_config_done = 0;\r
- return rc;\r
-}\r
-\r
-static int anx7150_afifo_overrun(struct i2c_client *client)\r
-{\r
- int rc = 0;\r
- char c;\r
- hdmi_dbg(&client->dev, "ANX7150: AFIFO overrun interrupt,disable audio.\n");\r
- // disable audio\r
-\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- c &= (~ANX7150_HDMI_AUDCTRL1_IN_EN);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
-\r
- return rc;\r
-}\r
-static int anx7150_spdif_error(struct i2c_client *client, int cur_state, int SPDIF_bi_phase_err, int SPDIF_error)\r
-{\r
- int rc = 0;\r
- char c;\r
- int state = cur_state;\r
-\r
- if(SPDIF_bi_phase_err || SPDIF_error)\r
- {\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- if( c & ANX7150_HDMI_AUDCTRL1_SPDIFIN_EN) \r
- {\r
- \r
- if ((state == CONFIG_AUDIO \r
- || state == CONFIG_PACKETS \r
- || state == HDCP_AUTHENTICATION \r
- || state == PLAY_BACK ))\r
- {\r
- if(SPDIF_bi_phase_err){\r
- hdmi_dbg(&client->dev, "SPDIF BI Phase or Unstable error.\n");\r
- spdif_error_cnt += 0x03;\r
- }\r
-\r
- if(SPDIF_error){\r
- hdmi_dbg(&client->dev, "SPDIF Parity error.\n");\r
- spdif_error_cnt += 0x01;\r
- }\r
-\r
- }\r
-\r
- // adjust spdif phase\r
- if (spdif_error_cnt >= spdif_error_th)\r
- {\r
- char freq_mclk,c1,c2;\r
- spdif_error_cnt = 0x00;\r
- hdmi_dbg(&client->dev, "adjust mclk phase!\n");\r
- \r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL0_REG, &c2);\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_I2S_CTRL_REG, &c1);\r
-\r
- freq_mclk = c2 & 0x07;\r
- switch (freq_mclk)\r
- {\r
- case ANX7150_mclk_128_Fs: //invert 0x50[3]\r
- hdmi_dbg(&client->dev, "adjust mclk phase when 128*Fs!\n");\r
- if ( c2 & 0x08 ) c2 &= 0xf7;\r
- else c2 |= 0x08;\r
-\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL0_REG, &c2);\r
- break;\r
-\r
- case ANX7150_mclk_256_Fs:\r
- case ANX7150_mclk_384_Fs:\r
- hdmi_dbg(&client->dev, "adjust mclk phase when 256*Fs or 384*Fs!\n");\r
- if ( c1 & 0x60 ) c1 &= 0x9f;\r
- else c1 |= 0x20;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_I2S_CTRL_REG, &c1);\r
- break;\r
-\r
- case ANX7150_mclk_512_Fs:\r
- hdmi_dbg(&client->dev, "adjust mclk phase when 512*Fs!\n");\r
- if ( c1 & 0x60 ) c1 &= 0x9f;\r
- else c1 |= 0x40;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_I2S_CTRL_REG, &c1);\r
- break;\r
- default:\r
- break;\r
-\r
- }\r
- }\r
- }\r
- }\r
- else{\r
- if(spdif_error_cnt > 0 && state == PLAY_BACK) spdif_error_cnt --;\r
- if(spdif_error_cnt > 0 && state < CONFIG_AUDIO) spdif_error_cnt = 0x00;\r
-\r
- }\r
-\r
- return rc;\r
-}\r
-static int anx7150_plllock(struct i2c_client *client)\r
-{\r
- int rc = 0;\r
- char c;\r
- \r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_CHIP_STATUS_REG, &c);\r
- if((c&0x01) == 0)\r
- {\r
- rc = anx7150_set_avmute(client);//wen\r
- hdmi_dbg(&client->dev, "ANX7150: PLL unlock interrupt,disable audio.\n");\r
- // disable audio & video\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- c &= (~ANX7150_HDMI_AUDCTRL1_IN_EN);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
-\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
- c &= (~ANX7150_VID_CTRL_IN_EN);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
-\r
- //when pll change, clear this reg to avoid error in package config\r
- c = 0x00;\r
- rc = anx7150_i2c_write_p1_reg(client, ANX7150_INFO_PKTCTRL1_REG, &c);//wen\r
- c = 0x00;\r
- rc = anx7150_i2c_write_p1_reg(client, ANX7150_INFO_PKTCTRL2_REG, &c);\r
-\r
-// ANX7150_system_config_done = 0;//jack wen\r
- }\r
- return rc;\r
-}\r
-static int anx7150_rx_sense_change(struct i2c_client *client, int cur_state)\r
-{\r
- int rc = 0;\r
- char c;\r
- int state = cur_state;\r
-\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_STATE_REG, &c);\r
- hdmi_dbg(&client->dev, "ANX7150_Rx_Sense_Interrupt, ANX7150_SYS_STATE_REG = %.2x\n", (unsigned int)c); //wen\r
-\r
- if ( c & ANX7150_SYS_STATE_RSV_DET)\r
- {\r
- //xy 11.06 Power on chip\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_CTRL1_REG, &c);\r
- c |= (0x01);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL1_REG, &c);\r
-\r
- s_ANX7150_packet_config.packets_need_config = 0x03; //new avi infoframe wen\r
- }\r
- else\r
- {\r
- // Rx is not active\r
- if (state > WAIT_HOTPLUG)\r
- {\r
- //stop HDCP and reset DDC when lost Rx sense\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
- c &= (~ANX7150_HDCP_CTRL0_REG);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
- \r
- rc = anx7150_rst_ddcchannel(client);\r
-\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_CTRL1_REG, &c);\r
- c &= (0xfd);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL1_REG, &c);\r
- \r
- // mute TMDS link\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_TMDS_CLKCH_CONFIG_REG, &c);\r
- c &= (~ANX7150_TMDS_CLKCH_MUTE);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_TMDS_CLKCH_CONFIG_REG, &c);\r
- }\r
- //Power down chip\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_CTRL1_REG, &c);\r
- c &= (0xfe);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL1_REG, &c);\r
- }\r
- //xy 11.06 when format change, need system config again\r
-// ANX7150_system_config_done = 0;//wen HDCP CTS\r
-\r
- return rc;\r
-}\r
-int ANX7150_Interrupt_Process(struct anx7150_pdata *anx, int cur_state)\r
-{\r
- struct anx7150_interrupt_s interrupt_staus;\r
-\r
- int state;\r
- int hot_plug;\r
- int rc;\r
-\r
- state = cur_state;\r
-\r
- hot_plug = anx7150_get_hpd(anx->client);\r
-\r
- rc = anx7150_get_interrupt_status(anx->client, &interrupt_staus);\r
- if(rc < 0){\r
- goto out;\r
- } \r
-\r
- if(anx->dev.HPD_status != hot_plug){\r
- anx->dev.HPD_change_cnt++;\r
- }\r
- else{\r
- anx->dev.HPD_change_cnt = 0;\r
- }\r
-\r
- if(anx->dev.HPD_change_cnt > 1){\r
- hdmi_dbg(&anx->client->dev, "hotplug_change\n");\r
-\r
- if(hot_plug == HDMI_RECIVER_UNPLUG){\r
- anx7150_unplug(anx->client);\r
- state = HDMI_INITIAL;\r
- anx->dev.reciver_status = HDMI_RECIVER_INACTIVE;\r
- }\r
-\r
- anx->dev.HPD_change_cnt = 0;\r
- anx->dev.HPD_status = hot_plug;\r
- }\r
- return state;\r
- if(state != HDMI_INITIAL && state != WAIT_HOTPLUG){\r
- if(interrupt_staus.video_format_change){\r
- if(state > SYSTEM_CONFIG){\r
- rc = anx7150_video_format_change(anx->client);\r
- state = CONFIG_VIDEO;\r
- }\r
- }\r
-\r
- if(interrupt_staus.auth_done){\r
- rc = anx7150_auth_done(anx->client);\r
- state = CONFIG_AUDIO;\r
- }\r
-\r
- if(interrupt_staus.auth_state_change){\r
- rc = anx7150_auth_change(anx->client);\r
- if(state == PLAY_BACK){\r
- state = HDCP_AUTHENTICATION;\r
- }\r
- }\r
-\r
- if(ANX7150_GET_RECIVER_TYPE() == 1){\r
- /*\r
- if(interrupt_staus.audio_clk_change){\r
- if(state > CONFIG_VIDEO){\r
- rc = anx7150_audio_clk_change(anx->client);\r
- state = SYSTEM_CONFIG;\r
- }\r
- }\r
- \r
- if(interrupt_staus.audio_FIFO_overrun){\r
- if(state > CONFIG_VIDEO){\r
- rc = anx7150_afifo_overrun(anx->client);\r
- state = CONFIG_AUDIO;\r
- }\r
- }\r
-\r
-*/\r
- rc = anx7150_spdif_error(anx->client, state, interrupt_staus.SPDIF_bi_phase_error, interrupt_staus.SPDIF_error);\r
- }\r
-\r
- if(interrupt_staus.pll_lock_change){\r
- if(state > SYSTEM_CONFIG){\r
- rc = anx7150_plllock(anx->client);\r
- state = SYSTEM_CONFIG;\r
- }\r
- }\r
-\r
- if(interrupt_staus.rx_sense_change){\r
- anx7150_rx_sense_change(anx->client, state);\r
- if(state > WAIT_RX_SENSE) \r
- state = WAIT_RX_SENSE;\r
- }\r
- }\r
-\r
-out:\r
- return state;\r
-}\r
-\r
-int ANX7150_API_Initial(struct i2c_client *client)\r
-{\r
- int rc = 0;\r
- hdmi_dbg(&client->dev, "%s\n", __func__);\r
-\r
- ANX7150_Variable_Initial();\r
- ANX7150_HW_Interface_Variable_Initial();\r
- rc = anx7150_hardware_initial(client);\r
-\r
- return rc;\r
-}\r
-\r
-void ANX7150_Shutdown(struct i2c_client *client)\r
-{\r
- hdmi_dbg(&client->dev, "%s\n", __func__);\r
- ANX7150_API_Initial(client);\r
- ANX7150_Set_System_State(client, HDMI_INITIAL);\r
-}\r
-\r
-static int anx7150_initddc_read(struct i2c_client *client, \r
- u8 devaddr, u8 segmentpointer,\r
- u8 offset, u8 access_num_Low,u8 access_num_high)\r
-{\r
- int rc = 0;\r
- char c;\r
-\r
- //Write slave device address\r
- c = devaddr;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_DDC_SLV_ADDR_REG, &c);\r
- // Write segment address\r
- c = segmentpointer;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_DDC_SLV_SEGADDR_REG, &c);\r
- //Write offset\r
- c = offset;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_DDC_SLV_OFFADDR_REG, &c);\r
- //Write number for access\r
- c = access_num_Low;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_DDC_ACCNUM0_REG, &c);\r
- c = access_num_high;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_DDC_ACCNUM1_REG, &c);\r
- //Clear FIFO\r
- c = 0x05;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_DDC_ACC_CMD_REG, &c);\r
- //EDDC sequential Read\r
- c = 0x04;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_DDC_ACC_CMD_REG, &c);\r
-\r
- return rc;\r
-}\r
-static int ANX7150_GetEDIDLength(struct i2c_client *client)\r
-{\r
- u8 edid_data_length;\r
- int rc = 0;\r
-\r
- anx7150_rst_ddcchannel(client);\r
-\r
- rc = anx7150_initddc_read(client, 0xa0, 0x00, 0x7e, 0x01, 0x00);\r
-\r
- mdelay(10);\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_DDC_FIFO_ACC_REG, &edid_data_length);\r
-\r
- ANX7150_edid_length = edid_data_length * 128 + 128;\r
-\r
- return rc;\r
-\r
-}\r
-/*** DDC fetch and block validation ***/\r
-\r
-static const u8 edid_header[] = {\r
- 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00\r
-};\r
-\r
-\r
-/*\r
- * Sanity check the EDID block (base or extension). Return 0 if the block\r
- * doesn't check out, or 1 if it's valid.\r
- */\r
- \r
-int anx7150_edid_block_valid(struct i2c_client *client, u8 *raw_edid)\r
-{\r
- int i;\r
- u8 csum = 0;\r
- struct edid *edid = (struct edid *)raw_edid;\r
-\r
- if (raw_edid[0] == 0x00) {\r
- int score = 0;\r
-\r
- for (i = 0; i < sizeof(edid_header); i++)\r
- if (raw_edid[i] == edid_header[i])\r
- score++;\r
-\r
- if (score == 8) ;\r
- else if (score >= 6) {\r
- hdmi_dbg(&client->dev, "Fixing EDID header, your hardware may be failing\n");\r
- memcpy(raw_edid, edid_header, sizeof(edid_header));\r
- } else {\r
- goto bad;\r
- }\r
- }\r
-\r
-#if 0\r
- for (i = 0; i < EDID_LENGTH; i++)\r
- csum += raw_edid[i];\r
- if (csum) {\r
- hdmi_dbg(&client->dev, "EDID checksum is invalid, remainder is %d\n", csum);\r
-\r
- /* allow CEA to slide through, switches mangle this */\r
- if (raw_edid[0] != 0x02)\r
- goto bad;\r
- }\r
-#endif\r
-\r
- /* per-block-type checks */\r
- switch (raw_edid[0]) {\r
- case 0: /* base */\r
- if (edid->version != 1) {\r
- dev_err(&client->dev, "EDID has major version %d, instead of 1\n", edid->version);\r
- goto bad;\r
- }\r
-\r
- if (edid->revision > 4)\r
- dev_err(&client->dev,"EDID minor > 4, assuming backward compatibility\n");\r
- break;\r
-\r
- default:\r
- break;\r
- }\r
-\r
- return 1;\r
-\r
-bad:\r
- if (raw_edid) {\r
- dev_err(&client->dev, "Raw EDID:\n");\r
- print_hex_dump_bytes(KERN_ERR, DUMP_PREFIX_NONE, raw_edid, EDID_LENGTH);\r
- printk("\n");\r
- }\r
- return 0;\r
-}\r
-int ANX7150_DDC_EDID(struct i2c_client *client, u8 *buf, u8 block, u16 len)\r
-{\r
- u8 offset;\r
- u8 segment;\r
- u8 len_low;\r
- u8 len_high;\r
- \r
- offset = EDID_LENGTH * (block & 0x01);\r
- segment = block >> 1;\r
- len_low = len & 0xFF;\r
- len_high = (len >> 8) & 0xFF;\r
-\r
- anx7150_initddc_read(client, 0xa0, segment, offset, len_low, len_high);\r
- if(ANX7150_DDC_Mass_Read(client, buf, len) == len)\r
- return 0;\r
- else\r
- return -1;\r
-}\r
-u8 *ANX7150_Read_EDID(struct i2c_client *client)\r
-{\r
- u8 *block = NULL;\r
- u8 *raw_edid = NULL;\r
- u8 extend_block_num;\r
- int i = 0;\r
- int j = 0;\r
-\r
- anx7150_rst_ddcchannel(client);\r
-\r
- if ((block = (u8 *)kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL)\r
- return NULL;\r
-\r
- /* base block fetch */\r
- hdmi_dbg(&client->dev, "Read base block\n");\r
- for (i = 0; i < 4; i++) {\r
- if(ANX7150_DDC_EDID(client, block, 0, EDID_LENGTH))\r
- goto out;\r
- if(anx7150_edid_block_valid(client, block))\r
- break;\r
- else\r
- dev_err(&client->dev, "Read base block err, retry...\n");\r
- \r
- mdelay(10);\r
- }\r
-\r
- if(i == 4){\r
- dev_err(&client->dev, "Read base block failed\n");\r
- goto out;\r
- }\r
-\r
- /* if there's no extensions, we're done */\r
- extend_block_num = block[0x7e];\r
- if(extend_block_num == 0)\r
- goto out;\r
- \r
- dev_err(&client->dev, "extend_block_num = %d\n", extend_block_num);\r
-\r
- raw_edid = krealloc(block, (extend_block_num + 1) * EDID_LENGTH, GFP_KERNEL);\r
- if(!raw_edid)\r
- goto out;\r
-\r
- block = raw_edid;\r
-\r
- hdmi_dbg(&client->dev, "Read extend block\n");\r
- for(j=1; j<=extend_block_num; j++){\r
- for(i=0; i<4; i++){\r
- if(ANX7150_DDC_EDID(client, raw_edid + j * EDID_LENGTH, j, EDID_LENGTH))\r
- goto out;\r
- if(anx7150_edid_block_valid(client, raw_edid + j * EDID_LENGTH))\r
- break;\r
- else\r
- dev_err(&client->dev, "Read extend block %d err, retry...\n", j);\r
-\r
- mdelay(10);\r
- }\r
-\r
- if(i == 4){\r
- dev_err(&client->dev, "Read extend block %d failed\n", j);\r
- goto out;\r
- }\r
- }\r
-\r
- dev_err(&client->dev, "\n\nRaw EDID(extend_block_num = %d, total_len = %d):\n\n", extend_block_num, EDID_LENGTH*(extend_block_num+1));\r
- print_hex_dump_bytes(KERN_ERR, DUMP_PREFIX_NONE, raw_edid, EDID_LENGTH*(extend_block_num+1));\r
- printk("\n\n");\r
-\r
- return raw_edid;\r
-\r
-out:\r
- kfree(block);\r
- return NULL;\r
-}\r
-int ANX7150_DDC_Mass_Read(struct i2c_client *client, u8 *buf, u16 len)\r
-{\r
- int rc = 0;\r
- u32 i, j;\r
- char c, c1,ddc_empty_cnt;\r
-\r
- i = len;\r
- while (i > 0)\r
- {\r
- //check DDC FIFO statue\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_DDC_CHSTATUS_REG, &c);\r
- if (c & ANX7150_DDC_CHSTATUS_DDC_OCCUPY)\r
- {\r
- hdmi_dbg(&client->dev, "ANX7150 DDC channel is accessed by an external device, break!.\n");\r
- break;\r
- }\r
- if (c & ANX7150_DDC_CHSTATUS_FIFO_FULL)\r
- ANX7150_ddc_fifo_full = 1;\r
- else\r
- ANX7150_ddc_fifo_full = 0;\r
- if (c & ANX7150_DDC_CHSTATUS_INPRO)\r
- ANX7150_ddc_progress = 1;\r
- else\r
- ANX7150_ddc_progress = 0;\r
- if (ANX7150_ddc_fifo_full)\r
- {\r
- hdmi_dbg(&client->dev, "DDC FIFO is full during edid reading");\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_DDC_FIFOCNT_REG, &c);\r
- hdmi_dbg(&client->dev, "FIFO counter is %.2x\n", (u32) c);\r
- for (j=0; j<c; j++)\r
- {\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_DDC_FIFO_ACC_REG, &c1);\r
- buf[len - i + j] = c1;\r
-\r
- ANX7150_ddc_fifo_full = 0;\r
- if(anx7150_mass_read_need_delay)\r
- mdelay(1);\r
- }\r
- i = i - c;\r
- //D("\n");\r
- }\r
- else if (!ANX7150_ddc_progress)\r
- {\r
- //D("ANX7150 DDC FIFO access finished.\n");\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_DDC_FIFOCNT_REG, &c);\r
- //D("FIFO counter is %.2x\n", (u32) c);\r
- if (!c)\r
- {\r
- i =0;\r
- break;\r
- }\r
- for (j=0; j<c; j++)\r
- {\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_DDC_FIFO_ACC_REG, &c1);\r
- buf[len - i + j] = c1;\r
- }\r
- i = i - c;\r
- //D("\ni=%d\n", i);\r
- }\r
- else\r
- {\r
- ddc_empty_cnt = 0x00;\r
- for (c1=0; c1<0x0a; c1++)\r
- {\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_DDC_CHSTATUS_REG, &c);\r
- //D("DDC FIFO access is progressing.\n");\r
- //D("DDC Channel status is 0x%.2x\n",(u32)c);\r
- if (c & ANX7150_DDC_CHSTATUS_FIFO_EMPT)\r
- ddc_empty_cnt++;\r
- mdelay(1);\r
- //D("ddc_empty_cnt = 0x%.2x\n",(u32)ddc_empty_cnt);\r
- }\r
- if (ddc_empty_cnt >= 0x0a)\r
- break;\r
- }\r
- }\r
- return (len - i);\r
-}\r
-\r
-static u8 ANX7150_Read_EDID_u8(u8 segmentpointer,u8 offset)\r
-{
- /*u8 c;
- anx7150_initddc_read(0xa0, segmentpointer, offset, 0x01, 0x00);\r
- ANX7150_i2c_read_p0_reg(ANX7150_DDC_FIFOCNT_REG, &c);
- while(c==0)
- ANX7150_i2c_read_p0_reg(ANX7150_DDC_FIFO_ACC_REG, &c);
- return c;*/
-
- return ANX7150_EDID_Buf[offset];
-}\r
-static u8 ANX7150_Parse_EDIDHeader(void)\r
-{\r
- u8 i,temp;\r
- temp = 0;\r
- // the EDID header should begin with 0x00,0xff,0xff,0xff,0xff,0xff,0xff,0x00\r
- if ((ANX7150_Read_EDID_u8(0, 0) == 0x00) && (ANX7150_Read_EDID_u8(0, 7) == 0x00))\r
- {\r
- for (i = 1; i < 7; i++)\r
- {\r
- if (ANX7150_Read_EDID_u8(0, i) != 0xff)\r
- {\r
- temp = 0x01;\r
- break;\r
- }\r
- }\r
- }\r
- else\r
- {\r
- temp = 0x01;\r
- }\r
- if (temp == 0x01)\r
- {\r
- return 0;\r
- }\r
- else\r
- {\r
- return 1;\r
- }\r
-}\r
-static u8 ANX7150_Parse_EDIDVersion(void)\r
-{\r
-\r
- if (!((ANX7150_Read_EDID_u8(0, 0x12) == 1) && (ANX7150_Read_EDID_u8(0, 0x13) >= 3) ))\r
- {\r
- return 0;\r
- }\r
- else\r
- {\r
- return 1;\r
- }\r
-}\r
-static void ANX7150_Parse_DTD(void)\r
-{
- u32 temp;
- unsigned long temp1,temp2;
- u32 Hresolution,Vresolution,Hblanking,Vblanking;
- u32 PixelCLK,Vtotal,H_image_size,V_image_size;
- u8 Hz;
- //float Ratio;
-
- temp = ANX7150_edid_dtd[1];
- temp = temp << 8;
- PixelCLK = temp + ANX7150_edid_dtd[0];
- // D("Pixel clock is 10000 * %u\n", temp);
-
- temp = ANX7150_edid_dtd[4];
- temp = (temp << 4) & 0x0f00;
- Hresolution = temp + ANX7150_edid_dtd[2];
- //D("Horizontal Active is %u\n", Hresolution);
-
- temp = ANX7150_edid_dtd[4];
- temp = (temp << 8) & 0x0f00;
- Hblanking = temp + ANX7150_edid_dtd[3];
- //D("Horizontal Blanking is %u\n", temp);
-
- temp = ANX7150_edid_dtd[7];
- temp = (temp << 4) & 0x0f00;
- Vresolution = temp + ANX7150_edid_dtd[5];
- //D("Vertical Active is %u\n", Vresolution);
-
- temp = ANX7150_edid_dtd[7];
- temp = (temp << 8) & 0x0f00;
- Vblanking = temp + ANX7150_edid_dtd[6];
- //D("Vertical Blanking is %u\n", temp);
-
- temp = ANX7150_edid_dtd[11];
- temp = (temp << 2) & 0x0300;
- temp = temp + ANX7150_edid_dtd[8];
- //D("Horizontal Sync Offset is %u\n", temp);
-
- temp = ANX7150_edid_dtd[11];
- temp = (temp << 4) & 0x0300;
- temp = temp + ANX7150_edid_dtd[9];
- //D("Horizontal Sync Pulse is %u\n", temp);
-
- temp = ANX7150_edid_dtd[11];
- temp = (temp << 2) & 0x0030;
- temp = temp + (ANX7150_edid_dtd[10] >> 4);
- //D("Vertical Sync Offset is %u\n", temp);
-
- temp = ANX7150_edid_dtd[11];
- temp = (temp << 4) & 0x0030;
- temp = temp + (ANX7150_edid_dtd[8] & 0x0f);
- //D("Vertical Sync Pulse is %u\n", temp);
-
- temp = ANX7150_edid_dtd[14];
- temp = (temp << 4) & 0x0f00;
- H_image_size = temp + ANX7150_edid_dtd[12];
- //D("Horizontal Image size is %u\n", temp);
-
- temp = ANX7150_edid_dtd[14];
- temp = (temp << 8) & 0x0f00;
- V_image_size = temp + ANX7150_edid_dtd[13];
- //D("Vertical Image size is %u\n", temp);
-
- //D("Horizontal Border is %bu\n", ANX7150_edid_dtd[15]);
-
- //D("Vertical Border is %bu\n", ANX7150_edid_dtd[16]);
-
- temp1 = Hresolution + Hblanking;
- Vtotal = Vresolution + Vblanking;
- temp1 = temp1 * Vtotal;
- temp2 = PixelCLK;
- temp2 = temp2 * 10000;
- if (temp1 == 0) //update
- Hz=0;
- else
- Hz = temp2 / temp1;
- //Hz = temp2 / temp1;
- if ((Hz == 59) || (Hz == 60))
- {
- Hz = 60;
- //D("_______________Vertical Active is %u\n", Vresolution);
- if (Vresolution == 540)
- ANX7150_edid_result.supported_1080i_60Hz = 1;
- if (Vresolution == 1080)
- ANX7150_edid_result.supported_1080p_60Hz = 1;
- if (Vresolution == 720)
- ANX7150_edid_result.supported_720p_60Hz = 1;
- if ((Hresolution == 640) && (Vresolution == 480))
- ANX7150_edid_result.supported_640x480p_60Hz = 1;
- if ((Hresolution == 720) && (Vresolution == 480))
- ANX7150_edid_result.supported_720x480p_60Hz = 1;
- if ((Hresolution == 720) && (Vresolution == 240))
- ANX7150_edid_result.supported_720x480i_60Hz = 1;
- }
- if (Hz == 50)
- {
- //D("+++++++++++++++Vertical Active is %u\n", Vresolution);
- if (Vresolution == 540)
- ANX7150_edid_result.supported_1080i_50Hz = 1;
- if (Vresolution == 1080)
- ANX7150_edid_result.supported_1080p_50Hz = 1;
- if (Vresolution == 720)
- ANX7150_edid_result.supported_720p_50Hz = 1;
- if (Vresolution == 576)
- ANX7150_edid_result.supported_576p_50Hz = 1;
- if (Vresolution == 288)
- ANX7150_edid_result.supported_576i_50Hz = 1;
- }
- //D("Fresh rate :% bu Hz\n", Hz);
- //Ratio = H_image_size;
- //Ratio = Ratio / V_image_size;
- //D("Picture ratio : %f \n", Ratio);
-}\r
-static void ANX7150_Parse_DTDinBlockONE(void)\r
-{
- u8 i;
- for (i = 0; i < 18; i++)
- {
- ANX7150_edid_dtd[i] = ANX7150_Read_EDID_u8(0, (i + 0x36));
- }
- //D("Parse the first DTD in Block one:\n");
- ANX7150_Parse_DTD();
-
- if ((ANX7150_Read_EDID_u8(0, 0x48) == 0)
- && (ANX7150_Read_EDID_u8(0, 0x49) == 0)
- && (ANX7150_Read_EDID_u8(0, 0x4a) == 0))
- {
- ;//D("the second DTD in Block one is not used to descript video timing.\n");
- }
- else
- {
- for (i = 0; i < 18; i++)
- {
- ANX7150_edid_dtd[i] = ANX7150_Read_EDID_u8(0, (i + 0x48));
- }
- ANX7150_Parse_DTD();
- }
-
- if ((ANX7150_Read_EDID_u8(0,0x5a) == 0)
- && (ANX7150_Read_EDID_u8(0,0x5b) == 0)
- && (ANX7150_Read_EDID_u8(0,0x5c) == 0))
- {
- ;//D("the third DTD in Block one is not used to descript video timing.\n");
- }
- else
- {
- for (i = 0; i < 18; i++)
- {
- ANX7150_edid_dtd[i] = ANX7150_Read_EDID_u8(0, (i + 0x5a));
- }
- ANX7150_Parse_DTD();
- }
-
- if ((ANX7150_Read_EDID_u8(0,0x6c) == 0)
- && (ANX7150_Read_EDID_u8(0,0x6d) == 0)
- && (ANX7150_Read_EDID_u8(0,0x6e) == 0))
- {
- ;//D("the fourth DTD in Block one is not used to descript video timing.\n");
- }
- else
- {
- for (i = 0; i < 18; i++)
- {
- ANX7150_edid_dtd[i] = ANX7150_Read_EDID_u8(0,(i + 0x6c));
- }
- ANX7150_Parse_DTD();
- }
-}\r
-static void ANX7150_Parse_NativeFormat(void)\r
-{
- u8 temp;
- temp = ANX7150_Read_EDID_u8(0,0x83) & 0xf0;
- /*if(temp & 0x80)
- ;//D("DTV supports underscan.\n");
- if(temp & 0x40)
- ;//D("DTV supports BasicAudio.\n");*/
- if (temp & 0x20)
- {
- //D("DTV supports YCbCr 4:4:4.\n");
- ANX7150_edid_result.ycbcr444_supported= 1;
- }
- if (temp & 0x10)
- {
- //D("DTV supports YCbCr 4:2:2.\n");
- ANX7150_edid_result.ycbcr422_supported= 1;
- }
-}\r
-static void ANX7150_Parse_DTDinExtBlock(void)\r
-{
- u8 i,DTDbeginAddr;
- DTDbeginAddr = ANX7150_Read_EDID_u8(ANX7150_ext_block_num/2, 0x82)
- + 0x80;
- while (DTDbeginAddr < (0x6c + 0x80))
- {
- if ((ANX7150_Read_EDID_u8(ANX7150_ext_block_num/2,DTDbeginAddr) == 0)
- && (ANX7150_Read_EDID_u8(ANX7150_ext_block_num/2,(DTDbeginAddr + 1)) == 0)
- && (ANX7150_Read_EDID_u8(ANX7150_ext_block_num/2,(DTDbeginAddr + 2)) == 0))
- {
- ;//D("this DTD in Extension Block is not used to descript video timing.\n");
- }
- else
- {
- for (i = 0; i < 18; i++)
- {
- ANX7150_edid_dtd[i] = ANX7150_Read_EDID_u8(ANX7150_ext_block_num/2,(i + DTDbeginAddr));
- }
- //D("Parse the DTD in Extension Block :\n");
- ANX7150_Parse_DTD();
- }
- DTDbeginAddr = DTDbeginAddr + 18;
- }
-}\r
-static void ANX7150_Parse_AudioSTD(void)\r
-{
- u8 i,AudioFormat,STDReg_tmp,STDAddr_tmp;
- STDReg_tmp = ANX7150_stdreg & 0x1f;
- STDAddr_tmp = ANX7150_stdaddr + 1;
- i = 0;
- while (i < STDReg_tmp)
- {
- AudioFormat = (ANX7150_Read_EDID_u8(ANX7150_ext_block_num/2,STDAddr_tmp ) & 0xF8) >> 3;
- ANX7150_edid_result.AudioChannel[i/3] = (ANX7150_Read_EDID_u8(ANX7150_ext_block_num/2,STDAddr_tmp) & 0x07) + 1;
- ANX7150_edid_result.AudioFormat[i/3] = AudioFormat;
- ANX7150_edid_result.AudioFs[i/3] = ANX7150_Read_EDID_u8(ANX7150_ext_block_num/2,(STDAddr_tmp + 1)) & 0x7f;
-
- if (AudioFormat == 1)
- ANX7150_edid_result.AudioLength[i/3] = ANX7150_Read_EDID_u8(ANX7150_ext_block_num/2,(STDAddr_tmp + 2)) & 0x07;
- else
- ANX7150_edid_result.AudioLength[i/3] = ANX7150_Read_EDID_u8(ANX7150_ext_block_num/2,(STDAddr_tmp + 2)) << 3;
-
- i = i + 3;
- STDAddr_tmp = STDAddr_tmp + 3;
- }
-}\r
-static void ANX7150_Parse_VideoSTD(void)\r
-{
- u8 i,STDReg_tmp,STDAddr_tmp;
- u8 SVD_ID[34];
- STDReg_tmp = ANX7150_stdreg & 0x1f;
- STDAddr_tmp = ANX7150_stdaddr + 1;
- i = 0;
- while (i < STDReg_tmp)
- {
- SVD_ID[i] = ANX7150_Read_EDID_u8(ANX7150_ext_block_num/2,STDAddr_tmp) & 0x7F;
- //D("ANX7150_edid_result.SVD_ID[%.2x]=0x%.2x\n",(u32)i,(u32)ANX7150_edid_result.SVD_ID[i]);
- //if(ANX7150_Read_EDID_u8(ANX7150_ext_block_num/2,STDAddr_tmp) & 0x80)
- // D(" Native mode");
- if (SVD_ID[i] == 1)
- ANX7150_edid_result.supported_640x480p_60Hz = 1;
- else if (SVD_ID[i] == 4)
- ANX7150_edid_result.supported_720p_60Hz = 1;
- else if (SVD_ID[i] == 19)
- ANX7150_edid_result.supported_720p_50Hz = 1;
- else if (SVD_ID[i] == 16)
- ANX7150_edid_result.supported_1080p_60Hz = 1;
- else if (SVD_ID[i] == 31)
- ANX7150_edid_result.supported_1080p_50Hz = 1;
- else if (SVD_ID[i] == 5)
- ANX7150_edid_result.supported_1080i_60Hz = 1;
- else if (SVD_ID[i] == 20)
- ANX7150_edid_result.supported_1080i_50Hz = 1;
- else if ((SVD_ID[i] == 2) ||(SVD_ID[i] == 3))
- ANX7150_edid_result.supported_720x480p_60Hz = 1;
- else if ((SVD_ID[i] == 6) ||(SVD_ID[i] == 7))
- ANX7150_edid_result.supported_720x480i_60Hz = 1;
- else if ((SVD_ID[i] == 17) ||(SVD_ID[i] == 18))
- ANX7150_edid_result.supported_576p_50Hz = 1;
- else if ((SVD_ID[i] == 21) ||(SVD_ID[i] == 22))
- ANX7150_edid_result.supported_576i_50Hz = 1;
-
- i = i + 1;
- STDAddr_tmp = STDAddr_tmp + 1;
- }
-}\r
-static void ANX7150_Parse_SpeakerSTD(void)\r
-{
- ANX7150_edid_result.SpeakerFormat = ANX7150_Read_EDID_u8(ANX7150_ext_block_num/2,(ANX7150_stdaddr + 1)) ;
-}\r
-static void ANX7150_Parse_VendorSTD(void)\r
-{\r
- //u8 c;\r
- if ((ANX7150_Read_EDID_u8(ANX7150_ext_block_num/2,(ANX7150_stdaddr + 1)) == 0x03)\r
- && (ANX7150_Read_EDID_u8(ANX7150_ext_block_num/2,(ANX7150_stdaddr + 2)) == 0x0c)\r
- && (ANX7150_Read_EDID_u8(ANX7150_ext_block_num/2,(ANX7150_stdaddr + 3)) == 0x00))\r
- {\r
- ANX7150_edid_result.is_HDMI = 1;\r
- //ANX7150_i2c_read_p0_reg(ANX7150_SYS_CTRL1_REG, &c);\r
- //ANX7150_i2c_write_p0_reg(ANX7150_SYS_CTRL1_REG, c |ANX7150_SYS_CTRL1_HDMI);\r
- }\r
- else\r
- {\r
- ANX7150_edid_result.is_HDMI = 0;\r
- //ANX7150_i2c_read_p0_reg(ANX7150_SYS_CTRL1_REG, &c);\r
- //ANX7150_i2c_write_p0_reg(ANX7150_SYS_CTRL1_REG, c & (~ANX7150_SYS_CTRL1_HDMI));\r
- }\r
-}\r
-\r
-static void ANX7150_Parse_STD(void)\r
-{
- u8 DTDbeginAddr;
- ANX7150_stdaddr = 0x84;
- DTDbeginAddr = ANX7150_Read_EDID_u8(ANX7150_ext_block_num/2,0x82) + 0x80;
- // D("Video DTDbeginAddr Register :%.2x\n", (u32) DTDbeginAddr);
- while (ANX7150_stdaddr < DTDbeginAddr)
- {
- ANX7150_stdreg = ANX7150_Read_EDID_u8(ANX7150_ext_block_num/2,ANX7150_stdaddr);
- switch (ANX7150_stdreg & 0xe0)
- {
- case 0x20:
- ANX7150_Parse_AudioSTD();
- ANX7150_sau_length = ANX7150_stdreg & 0x1f;
- break;
- case 0x40:
- ANX7150_Parse_VideoSTD();
- ANX7150_svd_length = ANX7150_stdreg & 0x1f;
- break;
- case 0x80:
- ANX7150_Parse_SpeakerSTD();
- break;
- case 0x60:
- ANX7150_Parse_VendorSTD();
- break;
- default:
- break;
- }
- ANX7150_stdaddr = ANX7150_stdaddr + (ANX7150_stdreg & 0x1f) + 0x01;
- }
-}\r
-static u8 ANX7150_EDID_Checksum(u8 block_number)\r
-{
- u8 i, real_checksum;
- u8 edid_block_checksum;
-
- edid_block_checksum = 0;
- for (i = 0; i < 127; i ++)
- {
- if ((block_number / 2) * 2 == block_number)
- edid_block_checksum = edid_block_checksum + ANX7150_Read_EDID_u8(block_number/2, i);
- else
- edid_block_checksum = edid_block_checksum + ANX7150_Read_EDID_u8(block_number/2, i + 0x80);
- }
- edid_block_checksum = (~edid_block_checksum) + 1;
- // D("edid_block_checksum = 0x%.2x\n",(u32)edid_block_checksum);
- if ((block_number / 2) * 2 == block_number)
- real_checksum = ANX7150_Read_EDID_u8(block_number/2, 0x7f);
- else
- real_checksum = ANX7150_Read_EDID_u8(block_number/2, 0xff);
- if (real_checksum == edid_block_checksum)
- return 1;
- else
- return 0;
-}\r
-static u8 ANX7150_Parse_ExtBlock(void)\r
-{
- u8 i,c;
-
- for (i = 0; i < ANX7150_Read_EDID_u8(0, 0x7e); i++) //read in blocks
- {
- c = ANX7150_Read_EDID_u8(i/2, 0x80);
- if ( c == 0x02)
- {
- ANX7150_ext_block_num = i + 1;
- ANX7150_Parse_DTDinExtBlock();
- ANX7150_Parse_STD();
- if (!(ANX7150_EDID_Checksum(ANX7150_ext_block_num)))
- {
- ANX7150_edid_result.edid_errcode = ANX7150_EDID_CheckSum_ERR;
- return ANX7150_edid_result.edid_errcode;
- }
- }
- else
- {
- ANX7150_edid_result.edid_errcode = ANX7150_EDID_ExtBlock_NotFor_861B;
- return ANX7150_edid_result.edid_errcode;
- }
- }
-
- return 0;
-}\r
-int ANX7150_Parse_EDID(struct i2c_client *client, struct anx7150_dev_s *dev)\r
-{\r
- int rc = 0, i;\r
- char c;\r
-\r
- if(dev->rk29_output_status == RK29_OUTPUT_STATUS_LCD)\r
- anx7150_mass_read_need_delay = 1;\r
- else\r
- anx7150_mass_read_need_delay = 0;\r
-\r
- /* Clear HDCP Authentication indicator */\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
- c &= (~ANX7150_HDCP_CTRL0_HW_AUTHEN);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
- ANX7150_hdcp_auth_en = 0;\r
-\r
-\r
- ANX7150_EDID_Buf = ANX7150_Read_EDID(client);\r
- \r
- if(!ANX7150_EDID_Buf){\r
- ANX7150_edid_result.edid_errcode = ANX7150_EDID_BadHeader;\r
- dev_err(&client->dev, "READ EDID ERROR\n");\r
- goto err;\r
- }\r
-\r
-/*\r
- if(ANX7150_EDID_Checksum(0) == 0)\r
- {\r
- D("EDID Block one check sum error, Stop parsing\n");\r
- ANX7150_edid_result.edid_errcode = ANX7150_EDID_CheckSum_ERR;\r
- return ANX7150_edid_result.edid_errcode;\r
- }\r
-*/\r
-\r
- //ANX7150_Parse_BasicDis();\r
- ANX7150_Parse_DTDinBlockONE();\r
-\r
- if(ANX7150_EDID_Buf[0x7e] == 0)\r
- {\r
- hdmi_dbg(&client->dev, "No EDID extension blocks.\n");\r
- ANX7150_edid_result.edid_errcode = ANX7150_EDID_No_ExtBlock;\r
- return ANX7150_edid_result.edid_errcode;\r
- }\r
- \r
- ANX7150_Parse_NativeFormat();\r
- ANX7150_Parse_ExtBlock();\r
-\r
- if (ANX7150_edid_result.edid_errcode == ANX7150_EDID_ExtBlock_NotFor_861B){\r
- dev_err(&client->dev,"EDID ExtBlock not support for 861B, Stop parsing\n");\r
- goto err;\r
- }\r
-\r
- if (ANX7150_edid_result.edid_errcode == ANX7150_EDID_CheckSum_ERR){\r
- dev_err(&client->dev,"EDID Block check sum error, Stop parsing\n");\r
- goto err;\r
- }\r
-\r
- hdmi_dbg(&client->dev,"EDID parsing finished!\n");\r
-\r
- {\r
- hdmi_dbg(&client->dev,"ANX7150_edid_result.edid_errcode = 0x%.2x\n",(u32)ANX7150_edid_result.edid_errcode);\r
- hdmi_dbg(&client->dev,"ANX7150_edid_result.is_HDMI = 0x%.2x\n",(u32)ANX7150_edid_result.is_HDMI);\r
- hdmi_dbg(&client->dev,"ANX7150_edid_result.ycbcr422_supported = 0x%.2x\n",(u32)ANX7150_edid_result.ycbcr422_supported);\r
- hdmi_dbg(&client->dev,"ANX7150_edid_result.ycbcr444_supported = 0x%.2x\n",(u32)ANX7150_edid_result.ycbcr444_supported);\r
- hdmi_dbg(&client->dev,"ANX7150_edid_result.supported_1080i_60Hz = 0x%.2x\n",(u32)ANX7150_edid_result.supported_1080i_60Hz);\r
- hdmi_dbg(&client->dev,"ANX7150_edid_result.supported_1080i_50Hz = 0x%.2x\n",(u32)ANX7150_edid_result.supported_1080i_50Hz);\r
- hdmi_dbg(&client->dev,"ANX7150_edid_result.supported_1080p_60Hz = 0x%.2x\n",(u32)ANX7150_edid_result.supported_1080p_60Hz);\r
- hdmi_dbg(&client->dev,"ANX7150_edid_result.supported_1080p_50Hz = 0x%.2x\n",(u32)ANX7150_edid_result.supported_1080p_50Hz);\r
- hdmi_dbg(&client->dev,"ANX7150_edid_result.supported_720p_60Hz = 0x%.2x\n",(u32)ANX7150_edid_result.supported_720p_60Hz);\r
- hdmi_dbg(&client->dev,"ANX7150_edid_result.supported_720p_50Hz = 0x%.2x\n",(u32)ANX7150_edid_result.supported_720p_50Hz);\r
- hdmi_dbg(&client->dev,"ANX7150_edid_result.supported_640x480p_60Hz = 0x%.2x\n",(u32)ANX7150_edid_result.supported_640x480p_60Hz);\r
- hdmi_dbg(&client->dev,"ANX7150_edid_result.supported_720x480p_60Hz = 0x%.2x\n",(u32)ANX7150_edid_result.supported_720x480p_60Hz);\r
- hdmi_dbg(&client->dev,"ANX7150_edid_result.supported_720x480i_60Hz = 0x%.2x\n",(u32)ANX7150_edid_result.supported_720x480i_60Hz);\r
- hdmi_dbg(&client->dev,"ANX7150_edid_result.supported_576p_50Hz = 0x%.2x\n",(u32)ANX7150_edid_result.supported_576p_50Hz);\r
- hdmi_dbg(&client->dev,"ANX7150_edid_result.supported_576i_50Hz = 0x%.2x\n",(u32)ANX7150_edid_result.supported_576i_50Hz);\r
- if (!ANX7150_edid_result.edid_errcode)\r
- {\r
- for (i = 0; i < ANX7150_sau_length/3; i++)\r
- {\r
- hdmi_dbg(&client->dev,"ANX7150_edid_result.AudioChannel = 0x%.2x\n",(u32)ANX7150_edid_result.AudioChannel[i]);\r
- hdmi_dbg(&client->dev,"ANX7150_edid_result.AudioFormat = 0x%.2x\n",(u32)ANX7150_edid_result.AudioFormat[i]);\r
- hdmi_dbg(&client->dev,"ANX7150_edid_result.AudioFs = 0x%.2x\n",(u32)ANX7150_edid_result.AudioFs[i]);\r
- hdmi_dbg(&client->dev,"ANX7150_edid_result.AudioLength = 0x%.2x\n",(u32)ANX7150_edid_result.AudioLength[i]);\r
- }\r
- hdmi_dbg(&client->dev,"ANX7150_edid_result.SpeakerFormat = 0x%.2x\n",(u32)ANX7150_edid_result.SpeakerFormat);\r
- }\r
- }\r
- \r
- ANX7150_parse_edid_done = 1;\r
- kfree(ANX7150_EDID_Buf);\r
- ANX7150_EDID_Buf = NULL;\r
- return 0;\r
- \r
-err:\r
- if(ANX7150_EDID_Buf){\r
- kfree(ANX7150_EDID_Buf);\r
- ANX7150_EDID_Buf = NULL;\r
- }\r
- return ANX7150_edid_result.edid_errcode;\r
-}\r
-int ANX7150_GET_SENSE_STATE(struct i2c_client *client)\r
-{\r
- int rc = 0;\r
- char c;\r
-\r
- hdmi_dbg(&client->dev, "enter\n");\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_STATE_REG, &c);\r
-\r
- return (c & ANX7150_SYS_STATE_RSV_DET) ? 1 : 0;\r
-}\r
-int ANX7150_Get_Optimal_resolution(int resolution_set)\r
-{\r
- int resolution_real;\r
- int find_resolution = 0;\r
-\r
- switch(resolution_set){\r
- case HDMI_1280x720p_50Hz:\r
- if(ANX7150_edid_result.supported_720p_50Hz){\r
- resolution_real = HDMI_1280x720p_50Hz;\r
- find_resolution = 1;\r
- }\r
- break;\r
- case HDMI_1280x720p_60Hz:\r
- if(ANX7150_edid_result.supported_720p_60Hz){\r
- resolution_real = HDMI_1280x720p_60Hz;\r
- find_resolution = 1;\r
- }\r
- break;\r
- case HDMI_720x576p_50Hz_4x3:\r
- if(ANX7150_edid_result.supported_576p_50Hz){\r
- resolution_real = HDMI_720x576p_50Hz_4x3;\r
- find_resolution = 1;\r
- }\r
- break;\r
- case HDMI_720x576p_50Hz_16x9:\r
- if(ANX7150_edid_result.supported_576p_50Hz){\r
- resolution_real = HDMI_720x576p_50Hz_16x9;\r
- find_resolution = 1;\r
- }\r
- break;\r
- case HDMI_720x480p_60Hz_4x3:\r
- if(ANX7150_edid_result.supported_720x480p_60Hz){\r
- resolution_real = HDMI_720x480p_60Hz_4x3;\r
- find_resolution = 1;\r
- }\r
- break;\r
- case HDMI_720x480p_60Hz_16x9:\r
- if(ANX7150_edid_result.supported_720x480p_60Hz){\r
- resolution_real = HDMI_720x480p_60Hz_16x9;\r
- find_resolution = 1;\r
- }\r
- break;\r
- case HDMI_1920x1080p_50Hz:\r
- if(ANX7150_edid_result.supported_1080p_50Hz){\r
- resolution_real = HDMI_1920x1080p_50Hz;\r
- find_resolution = 1;\r
- }\r
- break;\r
- case HDMI_1920x1080p_60Hz:\r
- if(ANX7150_edid_result.supported_1080p_60Hz){\r
- resolution_real = HDMI_1920x1080p_60Hz;\r
- find_resolution = 1;\r
- }\r
- break;\r
- default:\r
- break;\r
- }\r
-\r
- if(find_resolution == 0){\r
-\r
- if(ANX7150_edid_result.supported_720p_50Hz)\r
- resolution_real = HDMI_1280x720p_50Hz;\r
- else if(ANX7150_edid_result.supported_720p_60Hz)\r
- resolution_real = HDMI_1280x720p_60Hz;\r
- else if(ANX7150_edid_result.supported_576p_50Hz)\r
- resolution_real = HDMI_720x576p_50Hz_4x3;\r
- else if(ANX7150_edid_result.supported_720x480p_60Hz)\r
- resolution_real = HDMI_720x480p_60Hz_4x3;\r
- else if(ANX7150_edid_result.supported_1080p_50Hz)\r
- resolution_real = HDMI_1920x1080p_50Hz;\r
- else if(ANX7150_edid_result.supported_1080p_60Hz)\r
- resolution_real = HDMI_1920x1080p_60Hz;\r
- else\r
- resolution_real = HDMI_1280x720p_50Hz;\r
- }\r
-\r
- return resolution_real;\r
-}\r
-void ANX7150_API_HDCP_ONorOFF(u8 HDCP_ONorOFF)\r
-{ \r
- ANX7150_HDCP_enable = HDCP_ONorOFF;// 1: on; 0:off\r
-}\r
-static void ANX7150_API_Video_Config(u8 video_id,u8 input_pixel_rpt_time)\r
-{
- ANX7150_video_timing_id = video_id;
- ANX7150_in_pix_rpt = input_pixel_rpt_time;
-}\r
-static void ANX7150_API_Packets_Config(u8 pkt_sel)\r
-{
- s_ANX7150_packet_config.packets_need_config = pkt_sel;
-}\r
-static void ANX7150_API_AVI_Config(u8 pb1,u8 pb2,u8 pb3,u8 pb4,u8 pb5,\r
- u8 pb6,u8 pb7,u8 pb8,u8 pb9,u8 pb10,u8 pb11,u8 pb12,u8 pb13)
-{
- s_ANX7150_packet_config.avi_info.pb_u8[1] = pb1;
- s_ANX7150_packet_config.avi_info.pb_u8[2] = pb2;
- s_ANX7150_packet_config.avi_info.pb_u8[3] = pb3;
- s_ANX7150_packet_config.avi_info.pb_u8[4] = pb4;
- s_ANX7150_packet_config.avi_info.pb_u8[5] = pb5;
- s_ANX7150_packet_config.avi_info.pb_u8[6] = pb6;
- s_ANX7150_packet_config.avi_info.pb_u8[7] = pb7;
- s_ANX7150_packet_config.avi_info.pb_u8[8] = pb8;
- s_ANX7150_packet_config.avi_info.pb_u8[9] = pb9;
- s_ANX7150_packet_config.avi_info.pb_u8[10] = pb10;
- s_ANX7150_packet_config.avi_info.pb_u8[11] = pb11;
- s_ANX7150_packet_config.avi_info.pb_u8[12] = pb12;
- s_ANX7150_packet_config.avi_info.pb_u8[13] = pb13;
-}\r
-static void ANX7150_API_AUD_INFO_Config(u8 pb1,u8 pb2,u8 pb3,u8 pb4,u8 pb5,\r
- u8 pb6,u8 pb7,u8 pb8,u8 pb9,u8 pb10)
-{
- s_ANX7150_packet_config.audio_info.pb_u8[1] = pb1;
- s_ANX7150_packet_config.audio_info.pb_u8[2] = pb2;
- s_ANX7150_packet_config.audio_info.pb_u8[3] = pb3;
- s_ANX7150_packet_config.audio_info.pb_u8[4] = pb4;
- s_ANX7150_packet_config.audio_info.pb_u8[5] = pb5;
- s_ANX7150_packet_config.audio_info.pb_u8[6] = pb6;
- s_ANX7150_packet_config.audio_info.pb_u8[7] = pb7;
- s_ANX7150_packet_config.audio_info.pb_u8[8] = pb8;
- s_ANX7150_packet_config.audio_info.pb_u8[9] = pb9;
- s_ANX7150_packet_config.audio_info.pb_u8[10] = pb10;
-}\r
-static void ANX7150_API_AUD_CHStatus_Config(u8 MODE,u8 PCM_MODE,u8 SW_CPRGT,u8 NON_PCM,\r
- u8 PROF_APP,u8 CAT_CODE,u8 CH_NUM,u8 SOURCE_NUM,u8 CLK_ACCUR,u8 Fs)
-{
- //MODE: 0x00 = PCM Audio
- //PCM_MODE: 0x00 = 2 audio channels without pre-emphasis;
- //0x01 = 2 audio channels with 50/15 usec pre-emphasis;
- //SW_CPRGT: 0x00 = copyright is asserted;
- // 0x01 = copyright is not asserted;
- //NON_PCM: 0x00 = Represents linear PCM
- //0x01 = For other purposes
- //PROF_APP: 0x00 = consumer applications;
- // 0x01 = professional applications;
-
- //CAT_CODE: Category code
- //CH_NUM: 0x00 = Do not take into account
- // 0x01 = left channel for stereo channel format
- // 0x02 = right channel for stereo channel format
- //SOURCE_NUM: source number
- // 0x00 = Do not take into account
- // 0x01 = 1; 0x02 = 2; 0x03 = 3
- //CLK_ACCUR: 0x00 = level II
- // 0x01 = level I
- // 0x02 = level III
- // else reserved;
-
- s_ANX7150_audio_config.i2s_config.Channel_status1 = (MODE << 7) | (PCM_MODE << 5) |
- (SW_CPRGT << 2) | (NON_PCM << 1) | PROF_APP;
- s_ANX7150_audio_config.i2s_config.Channel_status2 = CAT_CODE;
- s_ANX7150_audio_config.i2s_config.Channel_status3 = (CH_NUM << 7) | SOURCE_NUM;
- s_ANX7150_audio_config.i2s_config.Channel_status4 = (CLK_ACCUR << 5) | Fs;\r
-}\r
-void ANX7150_API_System_Config(void)\r
-{\r
- ANX7150_API_Video_Config(g_video_format,input_pixel_clk_1x_repeatition);\r
- ANX7150_API_Packets_Config(ANX7150_avi_sel | ANX7150_audio_sel);\r
- if (s_ANX7150_packet_config.packets_need_config & ANX7150_avi_sel)\r
- ANX7150_API_AVI_Config( 0x00,source_ratio,null,null,null,null,null,null,null,null,null,null,null);\r
- if (s_ANX7150_packet_config.packets_need_config & ANX7150_audio_sel)\r
- ANX7150_API_AUD_INFO_Config(null,null,null,null,null,null,null,null,null,null);\r
- ANX7150_API_AUD_CHStatus_Config(null,null,null,null,null,null,null,null,null,g_audio_format);\r
-\r
-// ANX7150_system_config_done = 1;\r
-}\r
-\r
-static int anx7150_blue_screen_format_config(struct i2c_client *client)\r
-{\r
- int rc = 0 ;\r
- char c;\r
- \r
- // TODO:Add ITU 601 format.(Now only ITU 709 format added)\r
- switch (ANX7150_RGBorYCbCr)\r
- {\r
- case ANX7150_RGB: //select RGB mode\r
- c = 0x10;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_BLUESCREEN0_REG, &c);\r
- c = 0xeb;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_BLUESCREEN1_REG, &c);\r
- c = 0x10;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_BLUESCREEN2_REG, &c);\r
- break;\r
- case ANX7150_YCbCr422: //select YCbCr4:2:2 mode\r
- c = 0x00;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_BLUESCREEN0_REG, &c);\r
- c = 0xad;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_BLUESCREEN1_REG, &c);\r
- c = 0x2a;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_BLUESCREEN2_REG, &c);\r
- break;\r
- case ANX7150_YCbCr444: //select YCbCr4:4:4 mode\r
- c = 0x1a;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_BLUESCREEN0_REG, &c);\r
- c = 0xad;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_BLUESCREEN1_REG, &c);\r
- c = 0x2a;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_BLUESCREEN2_REG, &c);\r
- break;\r
- default:\r
- break;\r
- }\r
- return rc;\r
-}\r
-static void ANX7150_Get_Video_Timing(void)\r
-{\r
- u8 i;\r
- \r
-//#ifdef ITU656\r
- for (i = 0; i < 18; i++)\r
- {\r
- switch (ANX7150_video_timing_id)\r
- {\r
- case ANX7150_V640x480p_60Hz:\r
- //D("640x480p_60Hz!\n");\r
- ANX7150_video_timing_parameter[i] = ANX7150_video_timingtype_table.ANX7150_640x480p_60Hz[i];\r
- break;\r
- case ANX7150_V720x480p_60Hz_4x3:\r
- case ANX7150_V720x480p_60Hz_16x9:\r
- //D("720x480p_60Hz!\n");\r
- ANX7150_video_timing_parameter[i] = ANX7150_video_timingtype_table.ANX7150_720x480p_60Hz[i];\r
- break;\r
- case ANX7150_V1280x720p_60Hz:\r
- //D("1280x720p_60Hz!\n");\r
- ANX7150_video_timing_parameter[i] = ANX7150_video_timingtype_table.ANX7150_1280x720p_60Hz[i];\r
- break;\r
- case ANX7150_V1920x1080i_60Hz:\r
- //D("1920x1080i_60Hz!\n");\r
- ANX7150_video_timing_parameter[i] = ANX7150_video_timingtype_table.ANX7150_1920x1080i_60Hz[i];\r
- break;\r
- case ANX7150_V720x480i_60Hz_4x3:\r
- case ANX7150_V720x480i_60Hz_16x9:\r
- //D("720x480i_60Hz!\n");\r
- ANX7150_video_timing_parameter[i] = ANX7150_video_timingtype_table.ANX7150_720x480i_60Hz[i];\r
- break;\r
- case ANX7150_V720x576p_50Hz_4x3:\r
- case ANX7150_V720x576p_50Hz_16x9:\r
- //D("720x576p_50Hz!\n");\r
- ANX7150_video_timing_parameter[i] = ANX7150_video_timingtype_table.ANX7150_720x576p_50Hz[i];\r
- break;\r
- case ANX7150_V1280x720p_50Hz:\r
- //D("1280x720p_50Hz!\n");\r
- ANX7150_video_timing_parameter[i] = ANX7150_video_timingtype_table.ANX7150_1280x720p_50Hz[i];\r
- break;\r
- case ANX7150_V1920x1080i_50Hz:\r
- //D("1920x1080i_50Hz!\n");\r
- ANX7150_video_timing_parameter[i] = ANX7150_video_timingtype_table.ANX7150_1920x1080i_50Hz[i];\r
- break;\r
- case ANX7150_V720x576i_50Hz_4x3:\r
- case ANX7150_V720x576i_50Hz_16x9:\r
- //D("720x576i_50Hz!\n");\r
- ANX7150_video_timing_parameter[i] = ANX7150_video_timingtype_table.ANX7150_720x576i_50Hz[i];\r
- break;\r
-\r
- default:\r
- break;\r
- }\r
- //D("Video_Timing_Parameter[%.2x]=%.2x\n", (u32)i, (u32) ANX7150_video_timing_parameter[i]);\r
- }\r
- /*#else\r
- for(i = 0; i < 18; i++)\r
- {\r
- switch(ANX7150_video_timing_id)\r
- {\r
- case ANX7150_V640x480p_60Hz:\r
- //D("640x480p_60Hz!\n");\r
- ANX7150_video_timing_parameter[i] = Load_from_EEPROM(0, i);\r
- DRVDelayMs(3);\r
- break;\r
- case ANX7150_V720x480p_60Hz_4x3:\r
- case ANX7150_V720x480p_60Hz_16x9:\r
- //D("720x480p_60Hz!\n");\r
- ANX7150_video_timing_parameter[i] = Load_from_EEPROM(0, 18 + i);\r
- DRVDelayMs(3);\r
- break;\r
- case ANX7150_V1280x720p_60Hz:\r
- //D("1280x720p_60Hz!\n");\r
- ANX7150_video_timing_parameter[i] = Load_from_EEPROM(0, 36 + i);\r
- DRVDelayMs(3);\r
- break;\r
- case ANX7150_V1920x1080i_60Hz:\r
- //D("1920x1080i_60Hz!\n");\r
- ANX7150_video_timing_parameter[i] = Load_from_EEPROM(0, 54 + i);\r
- DRVDelayMs(3);\r
- break;\r
- case ANX7150_V720x480i_60Hz_4x3:\r
- case ANX7150_V720x480i_60Hz_16x9:\r
- //D("720x480i_60Hz!\n");\r
- ANX7150_video_timing_parameter[i] = Load_from_EEPROM(0, 72 + i);\r
- DRVDelayMs(3);\r
- break;\r
- case ANX7150_V720x576p_50Hz_4x3:\r
- case ANX7150_V720x576p_50Hz_16x9:\r
- //D("720x576p_50Hz!\n");\r
- ANX7150_video_timing_parameter[i] = Load_from_EEPROM(0, 90 + i);\r
- DRVDelayMs(3);\r
- break;\r
- case ANX7150_V1280x720p_50Hz:\r
- //D("1280x720p_50Hz!\n");\r
- ANX7150_video_timing_parameter[i] = Load_from_EEPROM(0, 108 + i);\r
- DRVDelayMs(3);\r
- break;\r
- case ANX7150_V1920x1080i_50Hz:\r
- //D("1920x1080i_50Hz!\n");\r
- ANX7150_video_timing_parameter[i] = Load_from_EEPROM(0, 126 + i);\r
- DRVDelayMs(3);\r
- break;\r
- case ANX7150_V720x576i_50Hz_4x3:\r
- case ANX7150_V720x576i_50Hz_16x9:\r
- //D("720x576i_50Hz!\n");\r
- ANX7150_video_timing_parameter[i] = Load_from_EEPROM(0, 144 + i);\r
- DRVDelayMs(3);\r
- break;\r
-\r
- default:\r
- break;\r
- }\r
- //D("Video_Timing_Parameter[%.2x]=%.2x\n", (u32)i, (u32) ANX7150_video_timing_parameter[i]);\r
- }\r
- #endif*/\r
-}\r
-static void ANX7150_Parse_Video_Format(void)\r
-{\r
- switch (ANX7150_video_format_config)\r
- {\r
- case ANX7150_RGB_YCrCb444_SepSync:\r
- ANX7150_emb_sync_mode = 0;\r
- ANX7150_demux_yc_en = 0;\r
- ANX7150_ddr_bus_mode = 0;\r
- ANX7150_de_gen_en = 0;\r
- //D("RGB_YCrCb444_SepSync mode!\n");\r
- break;\r
- case ANX7150_YCrCb422_SepSync:\r
- ANX7150_emb_sync_mode = 0;\r
- ANX7150_demux_yc_en = 0;\r
- ANX7150_ddr_bus_mode = 0;\r
- ANX7150_de_gen_en = 0;\r
- //D("YCrCb422_SepSync mode!\n");\r
- break;\r
- case ANX7150_YCrCb422_EmbSync:\r
- //D("YCrCb422_EmbSync mode!\n");\r
- ANX7150_demux_yc_en = 0;\r
- ANX7150_ddr_bus_mode = 0;\r
- ANX7150_de_gen_en = 0;\r
- ANX7150_emb_sync_mode = 1;\r
- ANX7150_Get_Video_Timing();\r
- break;\r
- case ANX7150_YCMux422_SepSync_Mode1:\r
- //D("YCMux422_SepSync_Mode1 mode!\n");\r
- ANX7150_emb_sync_mode = 0;\r
- ANX7150_ddr_bus_mode = 0;\r
- ANX7150_de_gen_en = 0;\r
- ANX7150_ycmux_u8_sel = 0;\r
- ANX7150_demux_yc_en = 1;\r
- break;\r
- case ANX7150_YCMux422_SepSync_Mode2:\r
- //D("YCMux422_SepSync_Mode2 mode!\n");\r
- ANX7150_emb_sync_mode = 0;\r
- ANX7150_ddr_bus_mode = 0;\r
- ANX7150_de_gen_en = 0;\r
- ANX7150_ycmux_u8_sel = 1;\r
- ANX7150_demux_yc_en = 1;\r
- break;\r
- case ANX7150_YCMux422_EmbSync_Mode1:\r
- //D("YCMux422_EmbSync_Mode1 mode!\n");\r
- ANX7150_ddr_bus_mode = 0;\r
- ANX7150_de_gen_en = 0;\r
- ANX7150_emb_sync_mode = 1;\r
- ANX7150_ycmux_u8_sel = 0;\r
- ANX7150_demux_yc_en = 1;\r
- ANX7150_Get_Video_Timing();\r
- break;\r
- case ANX7150_YCMux422_EmbSync_Mode2:\r
- //D("YCMux422_EmbSync_Mode2 mode!\n");\r
- ANX7150_ddr_bus_mode = 0;\r
- ANX7150_de_gen_en = 0;\r
- ANX7150_emb_sync_mode = 1;\r
- ANX7150_ycmux_u8_sel = 1;\r
- ANX7150_demux_yc_en = 1;\r
- ANX7150_Get_Video_Timing();\r
- break;\r
- case ANX7150_RGB_YCrCb444_DDR_SepSync:\r
- //D("RGB_YCrCb444_DDR_SepSync mode!\n");\r
- ANX7150_emb_sync_mode = 0;\r
- ANX7150_demux_yc_en = 0;\r
- ANX7150_de_gen_en = 0;\r
- ANX7150_ddr_bus_mode = 1;\r
- break;\r
- case ANX7150_RGB_YCrCb444_DDR_EmbSync:\r
- //D("RGB_YCrCb444_DDR_EmbSync mode!\n");\r
- ANX7150_demux_yc_en = 0;\r
- ANX7150_de_gen_en = 0;\r
- ANX7150_emb_sync_mode = 1;\r
- ANX7150_ddr_bus_mode = 1;\r
- ANX7150_Get_Video_Timing();\r
- break;\r
- case ANX7150_RGB_YCrCb444_SepSync_No_DE:\r
- //D("RGB_YCrCb444_SepSync_No_DE mode!\n");\r
- ANX7150_emb_sync_mode = 0;\r
- ANX7150_demux_yc_en = 0;\r
- ANX7150_ddr_bus_mode = 0;\r
- ANX7150_de_gen_en = 1;\r
- ANX7150_Get_Video_Timing();\r
- break;\r
- case ANX7150_YCrCb422_SepSync_No_DE:\r
- //D("YCrCb422_SepSync_No_DE mode!\n");\r
- ANX7150_emb_sync_mode = 0;\r
- ANX7150_demux_yc_en = 0;\r
- ANX7150_ddr_bus_mode = 0;\r
- ANX7150_de_gen_en = 1;\r
- ANX7150_Get_Video_Timing();\r
- break;\r
- default:\r
- break;\r
- }\r
-}\r
-static int anx7150_de_generator(struct i2c_client *client)\r
-{\r
- int rc = 0;\r
- char c;\r
- u8 video_type,hsync_pol,vsync_pol,v_fp,v_bp,vsync_width;\r
- u8 hsync_width_low,hsync_width_high,v_active_low,v_active_high;\r
- u8 h_active_low,h_active_high,h_res_low,h_res_high,h_bp_low,h_bp_high;\r
- u32 hsync_width,h_active,h_res,h_bp;\r
-\r
- video_type = ANX7150_video_timing_parameter[15];\r
- hsync_pol = ANX7150_video_timing_parameter[16];\r
- vsync_pol = ANX7150_video_timing_parameter[17];\r
- v_fp = ANX7150_video_timing_parameter[12];\r
- v_bp = ANX7150_video_timing_parameter[11];\r
- vsync_width = ANX7150_video_timing_parameter[10];\r
- hsync_width = ANX7150_video_timing_parameter[5];\r
- hsync_width = (hsync_width << 8) + ANX7150_video_timing_parameter[4];\r
- v_active_high = ANX7150_video_timing_parameter[9];\r
- v_active_low = ANX7150_video_timing_parameter[8];\r
- h_active = ANX7150_video_timing_parameter[3];\r
- h_active = (h_active << 8) + ANX7150_video_timing_parameter[2];\r
- h_res = ANX7150_video_timing_parameter[1];\r
- h_res = (h_res << 8) + ANX7150_video_timing_parameter[0];\r
- h_bp = ANX7150_video_timing_parameter[7];\r
- h_bp = (h_bp << 8) + ANX7150_video_timing_parameter[6];\r
- if (ANX7150_demux_yc_en)\r
- {\r
- hsync_width = 2* hsync_width;\r
- h_active = 2 * h_active;\r
- h_res = 2 * h_res;\r
- h_bp = 2 * h_bp;\r
- }\r
- hsync_width_low = hsync_width & 0xff;\r
- hsync_width_high = (hsync_width >> 8) & 0xff;\r
- h_active_low = h_active & 0xff;\r
- h_active_high = (h_active >> 8) & 0xff;\r
- h_res_low = h_res & 0xff;\r
- h_res_high = (h_res >> 8) & 0xff;\r
- h_bp_low = h_bp & 0xff;\r
- h_bp_high = (h_bp >> 8) & 0xff;\r
-\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CAPCTRL1_REG, &c);\r
- c = (c & 0xf7) | video_type;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CAPCTRL1_REG, &c);\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CAPCTRL1_REG, &c);\r
- c = (c & 0xdf) | hsync_pol;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CAPCTRL1_REG, &c);\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CAPCTRL1_REG, &c);\r
- c = (c & 0xbf) | vsync_pol;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CAPCTRL1_REG, &c);\r
- c = v_active_low;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_ACT_LINEL_REG, &c);\r
- c = v_active_high;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_ACT_LINEH_REG, &c);\r
- c = vsync_width;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VSYNC_WID_REG, &c);\r
- c = v_bp;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VSYNC_TAIL2VIDLINE_REG, &c);\r
- c = h_active_low;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_PIXL_REG, &c);\r
- c = h_active_high;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_PIXH_REG, &c);\r
- c = h_res_low;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_H_RESL_REG, &c);\r
- c = h_res_high;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_H_RESH_REG, &c);\r
- c = hsync_width_low;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HSYNC_ACT_WIDTHL_REG, &c);\r
- c = hsync_width_high;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HSYNC_ACT_WIDTHH_REG, &c);\r
- c = h_bp_low;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_H_BACKPORCHL_REG, &c);\r
- c = h_bp_high;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_H_BACKPORCHH_REG, &c);\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CAPCTRL0_REG, &c);\r
- c |= ANX7150_VID_CAPCTRL0_DEGEN_EN;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CAPCTRL0_REG, &c);\r
-\r
- return rc;\r
-}\r
-static int anx7150_embed_sync_decode(struct i2c_client *client)\r
-{\r
- int rc = 0;\r
- char c;\r
- u8 video_type,hsync_pol,vsync_pol,v_fp,vsync_width;\r
- u8 h_fp_low,h_fp_high,hsync_width_low,hsync_width_high;\r
- u32 h_fp,hsync_width;\r
- \r
- video_type = ANX7150_video_timing_parameter[15];\r
- hsync_pol = ANX7150_video_timing_parameter[16];\r
- vsync_pol = ANX7150_video_timing_parameter[17];\r
- v_fp = ANX7150_video_timing_parameter[12];\r
- vsync_width = ANX7150_video_timing_parameter[10];\r
- h_fp = ANX7150_video_timing_parameter[14];\r
- h_fp = (h_fp << 8) + ANX7150_video_timing_parameter[13];\r
- hsync_width = ANX7150_video_timing_parameter[5];\r
- hsync_width = (hsync_width << 8) + ANX7150_video_timing_parameter[4];\r
- if (ANX7150_demux_yc_en)\r
- {\r
- h_fp = 2 * h_fp;\r
- hsync_width = 2* hsync_width;\r
- }\r
- h_fp_low = h_fp & 0xff;\r
- h_fp_high = (h_fp >> 8) & 0xff;\r
- hsync_width_low = hsync_width & 0xff;\r
- hsync_width_high = (hsync_width >> 8) & 0xff;\r
-\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CAPCTRL1_REG, &c);\r
- c = (c & 0xf7) | video_type;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CAPCTRL1_REG, &c);\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CAPCTRL1_REG, &c);\r
- c = (c & 0xdf) | hsync_pol;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CAPCTRL1_REG, &c);\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CAPCTRL1_REG, &c);\r
- c = (c & 0xbf) | vsync_pol;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CAPCTRL1_REG, &c);\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CAPCTRL0_REG, &c);\r
- c = c | ANX7150_VID_CAPCTRL0_EMSYNC_EN;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CAPCTRL0_REG, &c);\r
-\r
- c = v_fp;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_ACT_LINE2VSYNC_REG, &c);\r
- c = vsync_width;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VSYNC_WID_REG, &c);\r
- c = h_fp_low;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_H_FRONTPORCHL_REG, &c);\r
- c = h_fp_high;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_H_FRONTPORCHH_REG, &c);\r
- c = hsync_width_low;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HSYNC_ACT_WIDTHL_REG, &c);\r
- c = hsync_width_high;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HSYNC_ACT_WIDTHH_REG, &c);\r
- return rc;\r
-}\r
-int ANX7150_Blue_Screen(struct anx7150_pdata *anx)\r
-{\r
- return anx7150_blue_screen_format_config(anx->client);\r
-}\r
-//******************************Video Config***************************************\r
-int ANX7150_Config_Video(struct i2c_client *client)\r
-{\r
- int rc = 0;\r
- int retry = 0;\r
- char c,TX_is_HDMI;\r
- char cspace_y2r, y2r_sel, up_sample,range_y2r;\r
-\r
- cspace_y2r = 0;\r
- y2r_sel = 0;\r
- up_sample = 0;\r
- range_y2r = 0;\r
-\r
- //ANX7150_RGBorYCbCr = 0x00; //RGB\r
- //ANX7150_RGBorYCbCr = ANX7150_INPUT_COLORSPACE; //update\r
- c = 0x00;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_MODE_REG, &c);\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
- c &= (~ANX7150_VID_CTRL_u8CTRL_EN);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
-/*\r
- if (!ANX7150_system_config_done)\r
- {\r
- D("System has not finished config!\n");\r
- return;\r
- }\r
-*/\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_STATE_REG, &c);\r
- if (!(c & 0x02))\r
- {\r
- hdmi_dbg(&client->dev, "No clock detected !\n");\r
- //ANX7150_i2c_write_p0_reg(ANX7150_SYS_CTRL2_REG, 0x02);\r
- return -1;\r
- }\r
-\r
- rc = anx7150_clean_hdcp(client);\r
-\r
- //color space issue\r
- switch (ANX7150_video_timing_id)\r
- {\r
- case ANX7150_V1280x720p_50Hz:\r
- case ANX7150_V1280x720p_60Hz:\r
- case ANX7150_V1920x1080i_60Hz:\r
- case ANX7150_V1920x1080i_50Hz:\r
- case ANX7150_V1920x1080p_60Hz:\r
- case ANX7150_V1920x1080p_50Hz:\r
- y2r_sel = ANX7150_CSC_BT709;\r
- break;\r
- default:\r
- y2r_sel = ANX7150_CSC_BT601;\r
- break;\r
- }\r
- //rang[0~255]/[16~235] select\r
- if (ANX7150_video_timing_id == ANX7150_V640x480p_60Hz)\r
- range_y2r = 1;//rang[0~255]\r
- else\r
- range_y2r = 0;//rang[16~235]\r
- if ((ANX7150_RGBorYCbCr == ANX7150_YCbCr422) && (!ANX7150_edid_result.ycbcr422_supported))\r
- {\r
- up_sample = 1;\r
- if (ANX7150_edid_result.ycbcr444_supported)\r
- cspace_y2r = 0;\r
- else\r
- cspace_y2r = 1;\r
- }\r
- if ((ANX7150_RGBorYCbCr == ANX7150_YCbCr444) && (!ANX7150_edid_result.ycbcr444_supported))\r
- {\r
- cspace_y2r = 1;\r
- }\r
- //Config the embeded blue screen format according to output video format.\r
- rc = anx7150_blue_screen_format_config(client);\r
-\r
- ANX7150_Parse_Video_Format();\r
-\r
- if (ANX7150_de_gen_en)\r
- {\r
- hdmi_dbg(&client->dev, "ANX7150_de_gen_en!\n");\r
- rc = anx7150_de_generator(client);\r
- }\r
- else\r
- {\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CAPCTRL0_REG, &c);\r
- c &= (~ANX7150_VID_CAPCTRL0_DEGEN_EN);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CAPCTRL0_REG, &c);\r
- }\r
- if (ANX7150_emb_sync_mode)\r
- {\r
- hdmi_dbg(&client->dev, "ANX7150_Embed_Sync_Decode!\n");\r
- rc = anx7150_embed_sync_decode(client);\r
- \r
- if (ANX7150_ddr_bus_mode) //jack wen; for DDR embeded sync\r
- {\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_CTRL4_REG, &c);\r
- c |= (0x04);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL4_REG, &c);\r
- }\r
- else\r
- {\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_CTRL4_REG, &c);\r
- c &= (0xfb);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL4_REG, &c);\r
- }\r
- }\r
- else\r
- {\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CAPCTRL0_REG, &c);\r
- c &= (~ANX7150_VID_CAPCTRL0_EMSYNC_EN);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CAPCTRL0_REG, &c);\r
- }\r
- if (ANX7150_demux_yc_en)\r
- {\r
- hdmi_dbg(&client->dev, "ANX7150_demux_yc_en!\n");\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CAPCTRL0_REG, &c);\r
- c |= (ANX7150_VID_CAPCTRL0_DEMUX_EN);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CAPCTRL0_REG, &c);\r
- \r
- if (ANX7150_ycmux_u8_sel)\r
- {\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
- c |= (ANX7150_VID_CTRL_YCu8_SEL);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
- //jack wen, u8 mapping for yc mux, D3-8,1-0 -->D1-4\r
- hdmi_dbg(&client->dev, "ANX7150_demux_yc_en!####D1-4\n");\r
-\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
- c |= (ANX7150_VID_CTRL_u8CTRL_EN);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
-\r
- c = 0x0d;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL11, &c);\r
- c = 0x0c;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL10, &c);\r
- c = 0x0b;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL9, &c);\r
- c = 0x0a;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL8, &c);\r
- c = 0x09;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL7, &c);\r
- c = 0x08;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL6, &c);\r
- c = 0x01;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL5, &c);\r
- c = 0x00;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL4, &c);\r
- //\r
- }\r
- else\r
- {\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
- c &= (~ANX7150_VID_CTRL_YCu8_SEL);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
- //jack wen, u8 mapping for yc mux, D3-8,1-0 -->D5-8,\r
- hdmi_dbg(&client->dev, "ANX7150_demux_yc_en!####D5-8\n");\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
- c |= (ANX7150_VID_CTRL_u8CTRL_EN);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
- \r
- c = 0x0d;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL15, &c);\r
- c = 0x0c;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL14, &c);\r
- c = 0x0b;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL3, &c);\r
- c = 0x0a;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL12, &c);\r
- c = 0x09;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL11, &c);\r
- c = 0x08;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL10, &c);\r
- c = 0x01;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL9, &c);\r
- c = 0x00;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL8, &c);\r
- //\r
- }\r
- }\r
- else\r
- {\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CAPCTRL0_REG, &c);\r
- c &= (~ANX7150_VID_CAPCTRL0_DEMUX_EN);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CAPCTRL0_REG, &c);\r
- //jack wen\r
-\r
- //\r
-\r
- }\r
- if (ANX7150_ddr_bus_mode)\r
- {\r
- //D("ANX7150_ddr_bus_mode!\n");\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CAPCTRL0_REG, &c);\r
- c |= (ANX7150_VID_CAPCTRL0_DV_BUSMODE);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CAPCTRL0_REG, &c);\r
- //jack wen\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_CTRL4_REG, &c);\r
- c = (c & 0xfc) | 0x02;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL4_REG, &c);\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
- c |= (ANX7150_VID_CTRL_YCu8_SEL);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
- \r
- //jack wen\r
-\r
- if (ANX7150_ddr_edge)\r
- {\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CAPCTRL0_REG, &c);\r
- c |= (ANX7150_VID_CAPCTRL0_DDR_EDGE);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CAPCTRL0_REG, &c);\r
- }\r
- else\r
- {\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CAPCTRL0_REG, &c);\r
- c &= (~ANX7150_VID_CAPCTRL0_DDR_EDGE);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CAPCTRL0_REG, &c);\r
- }\r
-\r
- //jack wen for DDR+seperate maping\r
- if (ANX7150_video_format_config == 0x07)//jack wen, DDR yc422, 601,\r
- {\r
- hdmi_dbg(&client->dev, "ANX7150_DDR_601_Maping!\n");\r
- \r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
- c |= (ANX7150_VID_CTRL_u8CTRL_EN);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
-\r
- c = 0x0b;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL23, &c);\r
- c = 0x0a;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL22, &c);\r
- c = 0x09;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL21, &c);\r
- c = 0x08;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL20, &c);\r
- c = 0x07;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL19, &c);\r
- c = 0x06;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL18, &c);\r
- c = 0x05;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL17, &c);\r
- c = 0x04;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL16, &c);\r
-\r
- c = 0x17;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL15, &c);\r
- c = 0x16;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL14, &c);\r
- c = 0x15;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL13, &c);\r
- c = 0x14;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL12, &c);\r
- c = 0x13;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL11, &c);\r
- c = 0x12;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL10, &c);\r
- c = 0x11;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL9, &c);\r
- c = 0x10;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL8, &c);\r
-\r
- c = 0x03;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL7, &c);\r
- c = 0x02;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL6, &c);\r
- c = 0x01;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL5, &c);\r
- c = 0x00;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL4, &c);\r
- c = 0x0f;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL3, &c);\r
- c = 0x0e;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL2, &c);\r
- c = 0x0d;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL1, &c);\r
- c = 0x0c;\r
- rc = anx7150_i2c_write_p0_reg(client, VID_u8_CTRL0, &c);\r
-\r
- }\r
- else if (ANX7150_video_format_config == 0x08)//jack wen, DDR yc422, 656,\r
- {\r
- hdmi_dbg(&client->dev, "ANX7150_DDR_656_Maping!\n");\r
-\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
- c &= (~ANX7150_VID_CTRL_u8CTRL_EN);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
- }\r
- }\r
- else\r
- {\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CAPCTRL0_REG, &c);\r
- c &= (~ANX7150_VID_CAPCTRL0_DV_BUSMODE);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CAPCTRL0_REG, &c);\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CAPCTRL0_REG, &c);\r
- c &= (~ANX7150_VID_CAPCTRL0_DDR_EDGE);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CAPCTRL0_REG, &c);\r
-\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_CTRL4_REG, &c);\r
- c &= (0xfc);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL4_REG, &c);\r
- }\r
-\r
- if (cspace_y2r)\r
- {\r
- hdmi_dbg(&client->dev, "Color space Y2R enabled********\n");\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_MODE_REG, &c);\r
- c |= (ANX7150_VID_MODE_CSPACE_Y2R);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_MODE_REG, &c);\r
- if (y2r_sel)\r
- {\r
- hdmi_dbg(&client->dev, "Y2R_SEL!\n");\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_MODE_REG, &c);\r
- c |= (ANX7150_VID_MODE_Y2R_SEL);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_MODE_REG, &c);\r
- }\r
- else\r
- {\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_MODE_REG, &c);\r
- c &= (~ANX7150_VID_MODE_Y2R_SEL);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_MODE_REG, &c); \r
- }\r
- }\r
- else\r
- {\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_MODE_REG, &c);\r
- c &= (~ANX7150_VID_MODE_CSPACE_Y2R);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_MODE_REG, &c);\r
- }\r
-\r
- if (up_sample)\r
- {\r
- hdmi_dbg(&client->dev, "UP_SAMPLE!\n");\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_MODE_REG, &c);\r
- c |= (ANX7150_VID_MODE_UPSAMPLE);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_MODE_REG, &c);\r
- }\r
- else\r
- {\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_MODE_REG, &c);\r
- c &= (~ANX7150_VID_MODE_UPSAMPLE);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_MODE_REG, &c);\r
- }\r
-\r
- if (range_y2r)\r
- {\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_MODE_REG, &c);\r
- c |= (ANX7150_VID_MODE_RANGE_Y2R);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_MODE_REG, &c);\r
- }\r
- else\r
- {\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_MODE_REG, &c);\r
- c &= (~ANX7150_VID_MODE_RANGE_Y2R);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_MODE_REG, &c);\r
- }\r
-\r
- if (!ANX7150_pix_rpt_set_by_sys)\r
- {\r
- if ((ANX7150_video_timing_id == ANX7150_V720x480i_60Hz_16x9)\r
- || (ANX7150_video_timing_id == ANX7150_V720x576i_50Hz_16x9)\r
- || (ANX7150_video_timing_id == ANX7150_V720x480i_60Hz_4x3)\r
- || (ANX7150_video_timing_id == ANX7150_V720x576i_50Hz_4x3))\r
- ANX7150_tx_pix_rpt = 1;\r
- else\r
- ANX7150_tx_pix_rpt = 0;\r
- }\r
- //set input pixel repeat times\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_MODE_REG, &c);\r
- c = ((c & 0xfc) |ANX7150_in_pix_rpt);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_MODE_REG, &c);\r
- //set link pixel repeat times\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
- c = ((c & 0xfc) |ANX7150_tx_pix_rpt);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
-\r
- if ((ANX7150_in_pix_rpt != ANX7150_in_pix_rpt_bkp)\r
- ||(ANX7150_tx_pix_rpt != ANX7150_tx_pix_rpt_bkp) )\r
- {\r
- c = 0x02;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL2_REG, &c);\r
- c = 0x00;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL2_REG, &c);\r
- hdmi_dbg(&client->dev, "MISC_Reset!\n");\r
- ANX7150_in_pix_rpt_bkp = ANX7150_in_pix_rpt;\r
- ANX7150_tx_pix_rpt_bkp = ANX7150_tx_pix_rpt;\r
- }\r
- //enable video input\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
- c |= (ANX7150_VID_CTRL_IN_EN);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_VID_CTRL_REG, &c);\r
- //D("Video configure OK!\n");\r
-\r
- retry = 0;\r
- do{\r
- mdelay(60);\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_VID_STATUS_REG, &c);\r
- if (c & ANX7150_VID_STATUS_VID_STABLE){\r
- hdmi_dbg(&client->dev, "Video stable, continue!\n");\r
- break;\r
- }\r
- else{\r
- hdmi_dbg(&client->dev,"Video not stable!, retry = %d\n", retry);\r
- }\r
- }while(retry++ < 5);\r
-\r
- if (cspace_y2r)\r
- ANX7150_RGBorYCbCr = ANX7150_RGB;\r
- //Enable video CLK,Format change after config video.\r
- // ANX7150_i2c_read_p0_reg(ANX7150_INTR1_MASK_REG, &c);\r
- // ANX7150_i2c_write_p0_reg(ANX7150_INTR1_MASK_REG, c |0x01);//3\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_INTR2_MASK_REG, &c);\r
- c |= (0x48);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_INTR2_MASK_REG, &c);\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_INTR3_MASK_REG, &c);\r
- c |= (0x40);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_INTR3_MASK_REG, &c);\r
- \r
- if (ANX7150_edid_result.is_HDMI)\r
- {\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_CTRL1_REG, &c);\r
- c |= (0x02);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL1_REG, &c);\r
- hdmi_dbg(&client->dev,"ANX7150 is set to HDMI mode\n");\r
- }\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_CTRL1_REG, &c);\r
- TX_is_HDMI = c & 0x02;\r
-\r
- if (TX_is_HDMI == 0x02)\r
- {\r
- anx7150_set_avmute(client);//wen\r
- }\r
-\r
- //reset TMDS link to align 4 channels xy 061120\r
- hdmi_dbg(&client->dev,"reset TMDS link to align 4 channels\n");\r
-\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_SRST_REG, &c);\r
- c |= (ANX7150_TX_RST);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_SRST_REG, &c);\r
- c &= (~ANX7150_TX_RST);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_SRST_REG, &c);\r
- \r
- //Enable TMDS clock output // just enable u87, and let the other u8s along to avoid overwriting.\r
- hdmi_dbg(&client->dev,"Enable TMDS clock output\n");\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_TMDS_CLKCH_CONFIG_REG, &c);\r
- c |= (ANX7150_TMDS_CLKCH_MUTE);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_TMDS_CLKCH_CONFIG_REG, &c);\r
- if(ANX7150_HDCP_enable)\r
- mdelay(100); //400ms only for HDCP CTS\r
-\r
- //ANX7150_i2c_read_p0_reg(ANX7150_VID_MODE_REG, &c); //zy 061110\r
- return 0;\r
-}\r
-static u8 anx7150_config_i2s(struct i2c_client *client)\r
-{\r
- int rc;\r
- char c = 0x00;\r
- u8 exe_result = 0x00;\r
- char c1 = 0x00;\r
-\r
- hdmi_dbg(&client->dev,"ANX7150: config i2s audio.\n");\r
-\r
- //select SCK as source\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- c &= ~ANX7150_HDMI_AUDCTRL1_CLK_SEL;\r
- hdmi_dbg(&client->dev,"select SCK as source, c = 0x%.2x\n",(u32)c);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
-\r
-\r
- //config i2s channel\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- c1 = s_ANX7150_audio_config.i2s_config.audio_channel; // need u8[5:2]\r
- c1 &= 0x3c;\r
- c &= ~0x3c;\r
- c |= c1;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- hdmi_dbg(&client->dev,"config i2s channel, c = 0x%.2x\n",(u32)c);\r
- \r
- //config i2s format\r
- //ANX7150_i2c_read_p0_reg(ANX7150_I2S_CTRL_REG, &c);\r
- c = s_ANX7150_audio_config.i2s_config.i2s_format;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_I2S_CTRL_REG, &c);\r
- hdmi_dbg(&client->dev,"config i2s format, c = 0x%.2x\n",(u32)c);\r
-\r
- //map i2s fifo\r
-\r
- //TODO: config I2S channel map register according to system\r
-\r
-\r
- //ANX7150_i2c_write_p0_reg(ANX7150_I2SCH_CTRL_REG, c);\r
-\r
- //swap right/left channel\r
- /*ANX7150_i2c_read_p0_reg(ANX7150_I2SCH_SWCTRL_REG, &c);\r
- c1 = 0x00;\r
- c1 &= 0xf0;\r
- c &= ~0xf0;\r
- c |= c1;\r
- ANX7150_i2c_write_p0_reg(ANX7150_I2SCH_SWCTRL_REG, c);\r
- D("map i2s ffio, c = 0x%.2x\n",(u32)c);*/\r
-\r
- //down sample\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL0_REG, &c);\r
- c1 = s_ANX7150_audio_config.down_sample;\r
- c1 &= 0x60;\r
- c &= ~0x60;\r
- c |= c1;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL0_REG, &c);\r
- hdmi_dbg(&client->dev,"down sample, c = 0x%.2x\n",(u32)c);\r
-\r
- //config i2s channel status(5 regs)\r
- c = s_ANX7150_audio_config.i2s_config.Channel_status1;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_I2SCH_STATUS1_REG, &c);\r
- c = s_ANX7150_audio_config.i2s_config.Channel_status2;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_I2SCH_STATUS2_REG, &c);\r
- c = s_ANX7150_audio_config.i2s_config.Channel_status3;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_I2SCH_STATUS3_REG, &c);\r
- c = s_ANX7150_audio_config.i2s_config.Channel_status4;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_I2SCH_STATUS4_REG, &c);\r
- hdmi_dbg(&client->dev,"@@@@@@@@config i2s channel status4, c = 0x%.2x\n",(unsigned int)c);//jack wen\r
-\r
- c = s_ANX7150_audio_config.i2s_config.Channel_status5;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_I2SCH_STATUS5_REG, &c);\r
- hdmi_dbg(&client->dev,"config i2s channel status, c = 0x%.2x\n",(u32)c);\r
-\r
- exe_result = ANX7150_i2s_input;\r
- //D("return = 0x%.2x\n",(u32)exe_result);\r
-\r
- // open corresponding interrupt\r
- //ANX7150_i2c_read_p0_reg(ANX7150_INTR1_MASK_REG, &c);\r
- //ANX7150_i2c_write_p0_reg(ANX7150_INTR1_MASK_REG, (c | 0x22) );\r
- //ANX7150_i2c_read_p0_reg(ANX7150_INTR3_MASK_REG, &c);\r
- //ANX7150_i2c_write_p0_reg(ANX7150_INTR3_MASK_REG, (c | 0x20) );\r
-\r
-\r
- return exe_result;\r
-}\r
-\r
-static u8 anx7150_config_spdif(struct i2c_client *client)\r
-{\r
- int rc = 0;\r
- u8 exe_result = 0x00;\r
- char c = 0x00;\r
- char c1 = 0x00;\r
- // u8 c2 = 0x00;\r
- // u8 freq_mclk = 0x00;\r
-\r
- hdmi_dbg(&client->dev, "ANX7150: config SPDIF audio.\n");\r
-\r
-\r
- //Select MCLK\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- c |= (ANX7150_HDMI_AUDCTRL1_CLK_SEL);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
-\r
- //D("ANX7150: enable SPDIF audio.\n");\r
- //Enable SPDIF\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- c |= (ANX7150_HDMI_AUDCTRL1_SPDIFIN_EN);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
-\r
- //adjust MCLK phase in interrupt routine\r
-\r
- // adjust FS_FREQ //FS_FREQ\r
- c1 = s_ANX7150_audio_config.i2s_config.Channel_status4 & 0x0f;\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_SPDIFCH_STATUS_REG, &c);\r
- c &= ANX7150_SPDIFCH_STATUS_FS_FREG;\r
- c = c >> 4;\r
-\r
- if ( c != c1)\r
- {\r
- //D("adjust FS_FREQ by system!\n");\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_I2SCH_STATUS4_REG, &c);\r
- c &= 0xf0;\r
- c |= c1;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_I2SCH_STATUS4_REG, &c);\r
-\r
- //enable using FS_FREQ from 0x59\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- c |= (0x02);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- }\r
-\r
- // down sample\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL0_REG, &c);\r
- c1 = s_ANX7150_audio_config.down_sample;\r
- c1 &= 0x60;\r
- c &= ~0x60;\r
- c |= c1;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL0_REG, &c);\r
-\r
- if (s_ANX7150_audio_config.down_sample) //zy 060816\r
- {\r
- // adjust FS_FREQ by system because down sample\r
- //D("adjust FS_FREQ by system because down sample!\n");\r
-\r
- c1 = s_ANX7150_audio_config.i2s_config.Channel_status4 & 0x0f;\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_I2SCH_STATUS4_REG, &c);\r
- \r
- c &= 0xf0;\r
- c |= c1;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_I2SCH_STATUS4_REG, &c);\r
- }\r
-\r
-\r
- // spdif is stable\r
- hdmi_dbg(&client->dev, "config SPDIF audio done");\r
- exe_result = ANX7150_spdif_input;\r
-\r
- // open corresponding interrupt\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_INTR1_MASK_REG, &c);\r
- c |= (0x32);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_INTR1_MASK_REG, &c);\r
- //ANX7150_i2c_read_p0_reg(ANX7150_INTR3_MASK_REG, &c);\r
- //ANX7150_i2c_write_p0_reg(ANX7150_INTR3_MASK_REG, (c | 0xa1) );\r
- return exe_result;\r
-}\r
-\r
-static u8 anx7150_config_super_audio(struct i2c_client *client)\r
-{\r
- int rc = 0;\r
- u8 exe_result = 0x00;\r
- u8 c = 0x00;\r
-\r
-\r
- //D("ANX7150: config one u8 audio.\n");\r
-\r
- // select sck as source\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- c &= (~ANX7150_HDMI_AUDCTRL1_CLK_SEL);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
-\r
- // Enable stream 0x60\r
- c = s_ANX7150_audio_config.super_audio_config.one_u8_ctrl;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_ONEu8_AUD_CTRL_REG, &c);\r
-\r
-\r
- // Map stream 0x61\r
- // TODO: config super audio map register according to system\r
-\r
- exe_result = ANX7150_super_audio_input;\r
- return exe_result;\r
-\r
-}\r
-\r
-u8 ANX7150_Config_Audio(struct i2c_client *client)\r
-{\r
- int rc;\r
- char c = 0x00;\r
- u8 exe_result = 0x00;\r
- u8 audio_layout = 0x00;\r
- u8 fs = 0x00;\r
- u32 ACR_N = 0x0000;\r
-\r
- //set audio clock edge\r
-\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL0_REG, &c);\r
- c = ((c & 0xf7) | ANX7150_audio_clock_edge);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL0_REG, &c);\r
- \r
- //cts get select from SCK\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL0_REG, &c);\r
- c = (c & 0xef);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL0_REG, &c);\r
- hdmi_dbg(&client->dev, "audio_type = 0x%.2x\n",(u32)s_ANX7150_audio_config.audio_type);\r
- if (s_ANX7150_audio_config.audio_type & ANX7150_i2s_input)\r
- {\r
- hdmi_dbg(&client->dev, "Config I2s.\n");\r
- exe_result |= anx7150_config_i2s(client);\r
- }\r
- else\r
- {\r
- //disable I2S audio input\r
- hdmi_dbg(&client->dev, "Disable I2S audio input.\n");\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- c &= 0xc3;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- }\r
-\r
- if (s_ANX7150_audio_config.audio_type & ANX7150_spdif_input)\r
- {\r
- exe_result |= anx7150_config_spdif(client);\r
- }\r
- else\r
- {\r
- //disable SPDIF audio input\r
- hdmi_dbg(&client->dev, "Disable SPDIF audio input.\n");\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- c &= ~ANX7150_HDMI_AUDCTRL1_SPDIFIN_EN;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- }\r
-\r
- if (s_ANX7150_audio_config.audio_type & ANX7150_super_audio_input)\r
- {\r
- exe_result |= anx7150_config_super_audio(client);\r
- }\r
- else\r
- {\r
- //disable super audio output\r
- hdmi_dbg(&client->dev, "ANX7150: disable super audio output.\n");\r
- c = 0x00;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_ONEu8_AUD_CTRL_REG, &c);\r
- }\r
-\r
- if ((s_ANX7150_audio_config.audio_type & 0x07) == 0x00)\r
- {\r
- hdmi_dbg(&client->dev, "ANX7150 input no audio type.\n");\r
- }\r
-\r
- //audio layout\r
- if (s_ANX7150_audio_config.audio_type & ANX7150_i2s_input)\r
- {\r
- //ANX7150_i2c_read_p0_reg(ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- audio_layout = s_ANX7150_audio_config.audio_layout;\r
-\r
- //HDMI_RX_ReadI2C_RX0(0x15, &c);\r
-#if 0\r
- if ((c & 0x08) ==0x08 ) //u8[5:3]\r
- {\r
- audio_layout = 0x80;\r
- }\r
- else\r
- {\r
- audio_layout = 0x00;\r
- }\r
-#endif\r
- }\r
- if (s_ANX7150_audio_config.audio_type & ANX7150_super_audio_input)\r
- {\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_ONEu8_AUD_CTRL_REG, &c);\r
- if ( c & 0xfc) //u8[5:3]\r
- {\r
- audio_layout = 0x80;\r
- }\r
- }\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL0_REG, &c);\r
- c &= ~0x80;\r
- c |= audio_layout;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL0_REG, &c);\r
-\r
- if ( (s_ANX7150_audio_config.audio_type & 0x07) == exe_result )\r
- {\r
- //Initial N value\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_I2SCH_STATUS4_REG, &c);\r
- fs = c & 0x0f;\r
- // set default value to N\r
- ACR_N = ANX7150_N_48k;\r
- switch (fs)\r
- {\r
- case(0x00)://44.1k\r
- ACR_N = ANX7150_N_44k;\r
- break;\r
- case(0x02)://48k\r
- ACR_N = ANX7150_N_48k;\r
- break;\r
- case(0x03)://32k\r
- ACR_N = ANX7150_N_32k;\r
- break;\r
- case(0x08)://88k\r
- ACR_N = ANX7150_N_88k;\r
- break;\r
- case(0x0a)://96k\r
- ACR_N = ANX7150_N_96k;\r
- break;\r
- case(0x0c)://176k\r
- ACR_N = ANX7150_N_176k;\r
- break;\r
- case(0x0e)://192k\r
- ACR_N = ANX7150_N_192k;\r
- break;\r
- default:\r
- dev_err(&client->dev, "note wrong fs.\n");\r
- break;\r
- }\r
- // write N(ACR) to corresponding regs\r
- c = ACR_N;\r
- rc = anx7150_i2c_write_p1_reg(client, ANX7150_ACR_N1_SW_REG, &c);\r
- c = ACR_N>>8;\r
- rc = anx7150_i2c_write_p1_reg(client, ANX7150_ACR_N2_SW_REG, &c);\r
- c = 0x00;\r
- rc = anx7150_i2c_write_p1_reg(client, ANX7150_ACR_N3_SW_REG, &c);\r
- \r
- // set the relation of MCLK and Fs xy 070117\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL0_REG, &c);\r
- c = (c & 0xf8) | FREQ_MCLK;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL0_REG, &c);\r
- hdmi_dbg(&client->dev, "Audio MCLK input mode is: %.2x\n",(u32)FREQ_MCLK);\r
-\r
- //Enable control of ACR\r
- rc = anx7150_i2c_read_p1_reg(client, ANX7150_INFO_PKTCTRL1_REG, &c);\r
- c |= (ANX7150_INFO_PKTCTRL1_ACR_EN);\r
- rc = anx7150_i2c_write_p1_reg(client, ANX7150_INFO_PKTCTRL1_REG, &c);\r
- //audio enable:\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- c |= (ANX7150_HDMI_AUDCTRL1_IN_EN);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- }\r
-\r
- return exe_result;\r
-\r
-}\r
-static u8 ANX7150_Checksum(infoframe_struct *p)\r
-{
- u8 checksum = 0x00;
- u8 i;
-
- checksum = p->type + p->length + p->version;
- for (i=1; i <= p->length; i++)
- {
- checksum += p->pb_u8[i];
- }
- checksum = ~checksum;
- checksum += 0x01;
-
- return checksum;
-}\r
-static u8 anx7150_load_infoframe(struct i2c_client *client, packet_type member,\r
- infoframe_struct *p)\r
-{\r
- int rc = 0;\r
- u8 exe_result = 0x00;\r
- u8 address[8] = {0x00,0x20,0x40,0x60,0x80,0x80,0xa0,0xa0};\r
- u8 i;\r
- char c;\r
-\r
- p->pb_u8[0] = ANX7150_Checksum(p);\r
-\r
- // write infoframe to according regs\r
- c = p->type;\r
- rc = anx7150_i2c_write_p1_reg(client, address[member], &c);\r
- c = p->version;\r
- rc = anx7150_i2c_write_p1_reg(client, address[member]+1, &c);\r
- c = p->length;\r
- rc = anx7150_i2c_write_p1_reg(client, address[member]+2, &c);\r
-\r
- for (i=0; i <= p->length; i++)\r
- {\r
- c = p->pb_u8[i];\r
- rc = anx7150_i2c_write_p1_reg(client, address[member]+3+i, &c);\r
- rc = anx7150_i2c_read_p1_reg(client, address[member]+3+i, &c);\r
- }\r
- return exe_result;\r
-}\r
-\r
-//*************** Config Packet ****************************\r
-u8 ANX7150_Config_Packet(struct i2c_client *client)\r
-{\r
- int rc = 0;\r
- u8 exe_result = 0x00; // There is no use in current solution\r
- u8 info_packet_sel;\r
- char c;\r
-\r
- info_packet_sel = s_ANX7150_packet_config.packets_need_config;\r
- hdmi_dbg(&client->dev, "info_packet_sel = 0x%.2x\n",(u32) info_packet_sel);\r
- // New packet?\r
- if ( info_packet_sel != 0x00)\r
- {\r
- // avi infoframe\r
- if ( info_packet_sel & ANX7150_avi_sel )\r
- {\r
- c = s_ANX7150_packet_config.avi_info.pb_u8[1]; //color space\r
- c &= 0x9f;\r
- c |= (ANX7150_RGBorYCbCr << 5);\r
- s_ANX7150_packet_config.avi_info.pb_u8[1] = c | 0x10;\r
- switch(ANX7150_video_timing_id) \r
- {\r
- case ANX7150_V720x480p_60Hz_4x3:\r
- case ANX7150_V720x480p_60Hz_16x9:\r
- case ANX7150_V720x576p_50Hz_4x3:\r
- case ANX7150_V720x576p_50Hz_16x9:\r
- s_ANX7150_packet_config.avi_info.pb_u8[2] = 0x58;\r
- break;\r
- case ANX7150_V1280x720p_50Hz:\r
- case ANX7150_V1280x720p_60Hz:\r
- case ANX7150_V1920x1080p_50Hz:\r
- case ANX7150_V1920x1080p_60Hz:\r
- s_ANX7150_packet_config.avi_info.pb_u8[2] = 0xa8;\r
- break;\r
- default:\r
- s_ANX7150_packet_config.avi_info.pb_u8[2] = 0xa8;\r
- break;\r
- }\r
-\r
- c = s_ANX7150_packet_config.avi_info.pb_u8[4];// vid ID\r
- c = c & 0x80;\r
- s_ANX7150_packet_config.avi_info.pb_u8[4] = c | ANX7150_video_timing_id;\r
- c = s_ANX7150_packet_config.avi_info.pb_u8[5]; //repeat times\r
- c = c & 0xf0;\r
- c |= (ANX7150_tx_pix_rpt & 0x0f);\r
- s_ANX7150_packet_config.avi_info.pb_u8[5] = c;\r
- hdmi_dbg(&client->dev, "config avi infoframe packet.\n");\r
- // Disable repeater\r
- rc = anx7150_i2c_read_p1_reg(client, ANX7150_INFO_PKTCTRL1_REG, &c);\r
- c &= ~ANX7150_INFO_PKTCTRL1_AVI_RPT;\r
- rc = anx7150_i2c_write_p1_reg(client, ANX7150_INFO_PKTCTRL1_REG, &c);\r
-\r
- // Enable?wait:go\r
- rc = anx7150_i2c_read_p1_reg(client, ANX7150_INFO_PKTCTRL1_REG, &c);\r
- if (c & ANX7150_INFO_PKTCTRL1_AVI_EN)\r
- {\r
- //D("wait disable, config avi infoframe packet.\n");\r
- return exe_result; //jack wen\r
- }\r
-\r
- // load packet data to regs\r
- rc = anx7150_load_infoframe(client, ANX7150_avi_infoframe,\r
- &(s_ANX7150_packet_config.avi_info));\r
- // Enable and repeater\r
- rc = anx7150_i2c_read_p1_reg(client, ANX7150_INFO_PKTCTRL1_REG, &c);\r
- c |= 0x30;\r
- rc = anx7150_i2c_write_p1_reg(client, ANX7150_INFO_PKTCTRL1_REG, &c);\r
-\r
- // complete avi packet\r
- hdmi_dbg(&client->dev, "config avi infoframe packet done.\n");\r
- s_ANX7150_packet_config.packets_need_config &= ~ANX7150_avi_sel;\r
-\r
- }\r
-\r
- // audio infoframe\r
- if ( info_packet_sel & ANX7150_audio_sel )\r
- {\r
- hdmi_dbg(&client->dev, "config audio infoframe packet.\n");\r
-\r
- // Disable repeater\r
- rc = anx7150_i2c_read_p1_reg(client, ANX7150_INFO_PKTCTRL2_REG, &c);\r
- c &= ~ANX7150_INFO_PKTCTRL2_AIF_RPT;\r
- rc = anx7150_i2c_write_p1_reg(client, ANX7150_INFO_PKTCTRL2_REG, &c);\r
-\r
- // Enable?wait:go\r
- rc = anx7150_i2c_read_p1_reg(client, ANX7150_INFO_PKTCTRL2_REG, &c);\r
- if (c & ANX7150_INFO_PKTCTRL2_AIF_EN)\r
- {\r
- //D("wait disable, config audio infoframe packet.\n");\r
- //return exe_result;//jack wen\r
- }\r
- // config packet\r
-\r
- // load packet data to regs\r
- \r
- anx7150_load_infoframe( client, ANX7150_audio_infoframe,\r
- &(s_ANX7150_packet_config.audio_info));\r
- // Enable and repeater\r
- rc = anx7150_i2c_read_p1_reg(client, ANX7150_INFO_PKTCTRL2_REG, &c);\r
- c |= 0x03;\r
- rc = anx7150_i2c_write_p1_reg(client, ANX7150_INFO_PKTCTRL2_REG, &c);\r
-\r
- // complete avi packet\r
-\r
- hdmi_dbg(&client->dev, "config audio infoframe packet done.\n");\r
- s_ANX7150_packet_config.packets_need_config &= ~ANX7150_audio_sel;\r
-\r
- }\r
-\r
- // config other 4 packets\r
- /*\r
-\r
- if( info_packet_sel & 0xfc )\r
- {\r
- D("other packets.\n");\r
-\r
- //find the current type need config\r
- if(info_packet_sel & ANX7150_spd_sel) type_sel = ANX7150_spd_sel;\r
- else if(info_packet_sel & ANX7150_mpeg_sel) type_sel = ANX7150_mpeg_sel;\r
- else if(info_packet_sel & ANX7150_acp_sel) type_sel = ANX7150_acp_sel;\r
- else if(info_packet_sel & ANX7150_isrc1_sel) type_sel = ANX7150_isrc1_sel;\r
- else if(info_packet_sel & ANX7150_isrc2_sel) type_sel = ANX7150_isrc2_sel;\r
- else type_sel = ANX7150_vendor_sel;\r
-\r
-\r
- // Disable repeater\r
- ANX7150_i2c_read_p1_reg(ANX7150_INFO_PKTCTRL2_REG, &c);\r
- c &= ~ANX7150_INFO_PKTCTRL2_AIF_RPT;\r
- ANX7150_i2c_write_p1_reg(ANX7150_INFO_PKTCTRL2_REG, c);\r
-\r
- switch(type_sel)\r
- {\r
- case ANX7150_spd_sel:\r
- ANX7150_i2c_read_p1_reg(ANX7150_INFO_PKTCTRL1_REG, &c);\r
- c &= ~ANX7150_INFO_PKTCTRL1_SPD_RPT;\r
- ANX7150_i2c_write_p1_reg(ANX7150_INFO_PKTCTRL1_REG, c);\r
-\r
- ANX7150_i2c_read_p1_reg(ANX7150_INFO_PKTCTRL1_REG, &c);\r
- if(c & ANX7150_INFO_PKTCTRL1_SPD_EN)\r
- {\r
- D("wait disable, config spd infoframe packet.\n");\r
- return exe_result;\r
- }\r
- break;\r
-\r
- case ANX7150_mpeg_sel:\r
- ANX7150_i2c_read_p1_reg(ANX7150_INFO_PKTCTRL2_REG, &c);\r
- c &= ~ANX7150_INFO_PKTCTRL2_MPEG_RPT;\r
- ANX7150_i2c_write_p1_reg(ANX7150_INFO_PKTCTRL2_REG, c);\r
-\r
- ANX7150_i2c_read_p1_reg(ANX7150_INFO_PKTCTRL2_REG, &c);\r
- if(c & ANX7150_INFO_PKTCTRL2_MPEG_EN)\r
- {\r
- D("wait disable, config mpeg infoframe packet.\n");\r
- return exe_result;\r
- }\r
- break;\r
-\r
- case ANX7150_acp_sel:\r
- ANX7150_i2c_read_p1_reg(ANX7150_INFO_PKTCTRL2_REG, &c);\r
- c &= ~ANX7150_INFO_PKTCTRL2_UD0_RPT;\r
- ANX7150_i2c_write_p1_reg(ANX7150_INFO_PKTCTRL2_REG, c);\r
-\r
- ANX7150_i2c_read_p1_reg(ANX7150_INFO_PKTCTRL2_REG, &c);\r
- if(c & ANX7150_INFO_PKTCTRL2_UD0_EN)\r
- {\r
- D("wait disable, config mpeg infoframe packet.\n");\r
- return exe_result;\r
- }\r
- break;\r
-\r
- case ANX7150_isrc1_sel:\r
- ANX7150_i2c_read_p1_reg(ANX7150_INFO_PKTCTRL2_REG, &c);\r
- c &= ~ANX7150_INFO_PKTCTRL2_UD0_RPT;\r
- ANX7150_i2c_write_p1_reg(ANX7150_INFO_PKTCTRL2_REG, c);\r
- ANX7150_i2c_read_p1_reg(ANX7150_INFO_PKTCTRL2_REG, &c);\r
- if(c & ANX7150_INFO_PKTCTRL2_UD0_EN)\r
- {\r
- D("wait disable, config isrc1 packet.\n");\r
- return exe_result;\r
- }\r
- break;\r
-\r
- case ANX7150_isrc2_sel:\r
- ANX7150_i2c_read_p1_reg(ANX7150_INFO_PKTCTRL2_REG, &c);\r
- c &= ~ANX7150_INFO_PKTCTRL2_UD_RPT;\r
- ANX7150_i2c_write_p1_reg(ANX7150_INFO_PKTCTRL2_REG, c);\r
- ANX7150_i2c_read_p1_reg(ANX7150_INFO_PKTCTRL2_REG, &c);\r
- if(c & ANX7150_INFO_PKTCTRL2_UD_EN)\r
- {\r
- D("wait disable, config isrc2 packet.\n");\r
- return exe_result;\r
- }\r
- break;\r
-\r
- case ANX7150_vendor_sel:\r
- ANX7150_i2c_read_p1_reg(ANX7150_INFO_PKTCTRL2_REG, &c);\r
- c &= ~ANX7150_INFO_PKTCTRL2_UD_RPT;\r
- ANX7150_i2c_write_p1_reg(ANX7150_INFO_PKTCTRL2_REG, c);\r
- ANX7150_i2c_read_p1_reg(ANX7150_INFO_PKTCTRL2_REG, &c);\r
- if(c & ANX7150_INFO_PKTCTRL2_UD_EN)\r
- {\r
- D("wait disable, config vendor packet.\n");\r
- return exe_result;\r
- }\r
- break;\r
-\r
- default : break;\r
- }\r
-\r
-\r
- // config packet\r
- // TODO: config packet in top level\r
-\r
- // load packet data to regs\r
- switch(type_sel)\r
- {\r
- case ANX7150_spd_sel:\r
- ANX7150_Load_Infoframe( ANX7150_spd_infoframe,\r
- &(s_ANX7150_packet_config.spd_info));\r
- D("config spd done.\n");\r
- ANX7150_i2c_read_p1_reg(ANX7150_INFO_PKTCTRL1_REG, &c);\r
- c |= 0xc0;\r
- ANX7150_i2c_write_p1_reg(ANX7150_INFO_PKTCTRL1_REG, c);\r
- break;\r
-\r
- case ANX7150_mpeg_sel:\r
- ANX7150_Load_Infoframe( ANX7150_mpeg_infoframe,\r
- &(s_ANX7150_packet_config.mpeg_info));\r
- D("config mpeg done.\n");\r
- ANX7150_i2c_read_p1_reg(ANX7150_INFO_PKTCTRL2_REG, &c);\r
- c |= 0x0c;\r
- ANX7150_i2c_write_p1_reg(ANX7150_INFO_PKTCTRL2_REG, c);\r
- break;\r
-\r
- case ANX7150_acp_sel:\r
- ANX7150_Load_Packet( ANX7150_acp_packet,\r
- &(s_ANX7150_packet_config.acp_pkt));\r
- D("config acp done.\n");\r
- ANX7150_i2c_read_p1_reg(ANX7150_INFO_PKTCTRL2_REG, &c);\r
- c |= 0x30;\r
- ANX7150_i2c_write_p1_reg(ANX7150_INFO_PKTCTRL2_REG, c);\r
- break;\r
-\r
- case ANX7150_isrc1_sel:\r
- ANX7150_Load_Packet( ANX7150_isrc1_packet,\r
- &(s_ANX7150_packet_config.acp_pkt));\r
- D("config isrc1 done.\n");\r
- ANX7150_i2c_read_p1_reg(ANX7150_INFO_PKTCTRL2_REG, &c);\r
- c |= 0x30;\r
- ANX7150_i2c_write_p1_reg(ANX7150_INFO_PKTCTRL2_REG, c);\r
- break;\r
-\r
- case ANX7150_isrc2_sel:\r
- ANX7150_Load_Packet( ANX7150_isrc2_packet,\r
- &(s_ANX7150_packet_config.acp_pkt));\r
- D("config isrc2 done.\n");\r
- ANX7150_i2c_read_p1_reg(ANX7150_INFO_PKTCTRL2_REG, &c);\r
- c |= 0xc0;\r
- ANX7150_i2c_write_p1_reg(ANX7150_INFO_PKTCTRL2_REG, c);\r
- break;\r
-\r
- case ANX7150_vendor_sel:\r
- ANX7150_Load_Infoframe( ANX7150_vendor_infoframe,\r
- &(s_ANX7150_packet_config.vendor_info));\r
- D("config vendor done.\n");\r
- ANX7150_i2c_read_p1_reg(ANX7150_INFO_PKTCTRL2_REG, &c);\r
- c |= 0xc0;\r
- ANX7150_i2c_write_p1_reg(ANX7150_INFO_PKTCTRL2_REG, c);\r
- break;\r
-\r
- default : break;\r
- }\r
-\r
- // Enable and repeater\r
- ANX7150_i2c_read_p1_reg(ANX7150_INFO_PKTCTRL2_REG, &c);\r
- c |= 0x03;\r
- ANX7150_i2c_write_p1_reg(ANX7150_INFO_PKTCTRL2_REG, c);\r
-\r
- // complete config packet\r
- D("config other packets done.\n");\r
- s_ANX7150_packet_config.packets_need_config &= ~type_sel;\r
-\r
- }\r
- */\r
- }\r
-\r
-\r
- if ( s_ANX7150_packet_config.packets_need_config == 0x00)\r
- {\r
- hdmi_dbg(&client->dev, "config packets done\n");\r
- //ANX7150_Set_System_State(ANX7150_HDCP_AUTHENTICATION);\r
- }\r
-\r
-\r
- return exe_result;\r
-}\r
-//******************** HDCP process ********************************\r
-static int anx7150_hardware_hdcp_auth_init(struct i2c_client *client)\r
-{\r
- int rc = 0;\r
- u8 c;\r
-\r
-// ANX7150_i2c_read_p0_reg(ANX7150_SYS_CTRL1_REG, &c); //72:07.2 hdcp on\r
-// ANX7150_i2c_write_p0_reg(ANX7150_SYS_CTRL1_REG, (c | ANX7150_SYS_CTRL1_HDCPMODE));\r
- // disable hw hdcp\r
-// ANX7150_i2c_read_p0_reg(ANX7150_HDCP_CTRL0_REG, &c);\r
-// ANX7150_i2c_write_p0_reg(ANX7150_HDCP_CTRL0_REG, (c & (~ANX7150_HDCP_CTRL0_HW_AUTHEN)));\r
-\r
- //ANX7150_i2c_write_p0_reg(ANX7150_HDCP_CTRL0_REG, 0x03); //h/w auth off, jh simplay/hdcp\r
- c = 0x00;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c); //bit 0/1 off, as from start, we don't know if Bksv/srm/KSVList valid or not. SY.\r
-\r
- // DDC reset\r
- rc = anx7150_rst_ddcchannel(client);\r
-\r
- anx7150_initddc_read(client, 0x74, 0x00, 0x40, 0x01, 0x00);\r
- mdelay(5);\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_DDC_FIFO_ACC_REG, &ANX7150_hdcp_bcaps);\r
- hdmi_dbg(&client->dev, "ANX7150_Hardware_HDCP_Auth_Init(): ANX7150_hdcp_bcaps = 0x%.2x\n", (u32)ANX7150_hdcp_bcaps);\r
-\r
- if (ANX7150_hdcp_bcaps & 0x02)\r
- { //enable 1.1 feature\r
- hdmi_dbg(&client->dev, "ANX7150_Hardware_HDCP_Auth_Init(): bcaps supports 1.1\n");\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_CTRL1_REG, &c);\r
- c |= ANX7150_HDCP_CTRL1_HDCP11_EN;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_CTRL1_REG, &c);\r
- }\r
- else\r
- { //disable 1.1 feature and enable HDCP two special point check\r
- hdmi_dbg(&client->dev, "bcaps don't support 1.1\n");\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_CTRL1_REG, &c);\r
- c = ((c & (~ANX7150_HDCP_CTRL1_HDCP11_EN)) | ANX7150_LINK_CHK_12_EN);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_CTRL1_REG, &c);\r
- }\r
- //handle repeater bit. SY.\r
- if (ANX7150_hdcp_bcaps & 0x40)\r
- {\r
- //repeater\r
- hdmi_dbg(&client->dev, "ANX7150_Hardware_HDCP_Auth_Init(): bcaps shows Sink is a repeater\n");\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
- c |= ANX7150_HDCP_CTRL0_RX_REP;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
- }\r
- else\r
- {\r
- //receiver\r
- hdmi_dbg(&client->dev, "ANX7150_Hardware_HDCP_Auth_Init(): bcaps shows Sink is a receiver\n");\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
- c &= ~ANX7150_HDCP_CTRL0_RX_REP;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
- }\r
- anx7150_rst_ddcchannel(client);\r
- ANX7150_hdcp_auth_en = 0;\r
-\r
- return rc;\r
-}\r
-static u8 anx7150_bksv_srm(struct i2c_client *client)\r
-{
- int rc = 0;\r
-#if 1
- u8 bksv[5],i,bksv_one,c1;
- anx7150_initddc_read(client, 0x74, 0x00, 0x00, 0x05, 0x00);\r
- mdelay(15);\r
- for (i = 0; i < 5; i ++)
- {\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_DDC_FIFO_ACC_REG, &bksv[i]);\r
- }
-
- bksv_one = 0;
- for (i = 0; i < 8; i++)
- {
- c1 = 0x01 << i;
- if (bksv[0] & c1)
- bksv_one ++;
- if (bksv[1] & c1)
- bksv_one ++;
- if (bksv[2] & c1)
- bksv_one ++;
- if (bksv[3] & c1)
- bksv_one ++;
- if (bksv[4] & c1)
- bksv_one ++;
- }
- //wen HDCP CTS
- if (bksv_one != 20)
- {
- hdmi_dbg(&client->dev, "BKSV check fail\n");\r
- return 0;
- }
- else
- {
- hdmi_dbg(&client->dev, "BKSV check OK\n");\r
- return 1;
- }
-#endif
-
-#if 0 //wen HDCP CTS
- /*address by gerard.zhu*/
- u8 i,j,bksv_ones_count,bksv_data[Bksv_Data_Nums] = {0};
- ANX7150_DDC_Addr bksv_ddc_addr;
- u32 bksv_length;
- ANX7150_DDC_Type ddc_type;
-
- i = 0;
- j = 0;
- bksv_ones_count = 0;
- bksv_ddc_addr.dev_addr = HDCP_Dev_Addr;
- bksv_ddc_addr.sgmt_addr = 0;
- bksv_ddc_addr.offset_addr = HDCP_Bksv_Offset;
- bksv_length = Bksv_Data_Nums;
- ddc_type = DDC_Hdcp;
-
- if (!ANX7150_DDC_Read(bksv_ddc_addr, bksv_data, bksv_length, ddc_type))
- {
- /*Judge validity for Bksv*/
- while (i < Bksv_Data_Nums)
- {
- while (j < 8)
- {
- if (((bksv_data[i] >> j) & 0x01) == 1)
- {
- bksv_ones_count++;
- }
- j++;
- }
- i++;
- j = 0;
- }
- if (bksv_ones_count != 20)
- {
- rk29printk ("!!!!BKSV 1s ¡Ù20\n"); //update rk29printk ("!!!!BKSV 1s ¡Ù20\n");
- return 0;
- }
- }
- /*end*/
-
- D("bksv is ready.\n");
- // TODO: Compare the bskv[] value to the revocation list to decide if this value is a illegal BKSV. This is system depended.
- //If illegal, return 0; legal, return 1. Now just return 1
- return 1;
-#endif
-}\r
-\r
-static u8 anx7150_is_ksvlist_vld(struct i2c_client *client)\r
-{\r
- int rc = 0;\r
-//wen HDCP CTS\r
-#if 1\r
- hdmi_dbg(&client->dev, "ANX7150_IS_KSVList_VLD() is called.\n");\r
- anx7150_initddc_read(client, 0x74, 0x00, 0x41, 0x02, 0x00); //Bstatus, two u8s\r
- mdelay(5);\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_DDC_FIFO_ACC_REG, &ANX7150_hdcp_bstatus[0]);\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_DDC_FIFO_ACC_REG, &ANX7150_hdcp_bstatus[1]);\r
-\r
- if ((ANX7150_hdcp_bstatus[0] & 0x80) | (ANX7150_hdcp_bstatus[1] & 0x08))\r
- {\r
- hdmi_dbg(&client->dev, "Max dev/cascade exceeded: ANX7150_hdcp_bstatus[0]: 0x%x,ANX7150_hdcp_bstatus[1]:0x%x\n", (u32)ANX7150_hdcp_bstatus[0],(u32)ANX7150_hdcp_bstatus[1]);\r
- return 0;//HDCP topology error. More than 127 RX are attached or more than seven levels of repeater are cascaded.\r
- }\r
- return 1;\r
-#endif\r
-//wen HDCP CTS\r
-\r
-}\r
-\r
-static void anx7150_show_video_parameter(struct i2c_client *client)\r
-{\r
- int rc = 0;\r
- // int h_res,h_act,v_res,v_act,h_fp,hsync_width,h_bp;\r
- char c, c1;\r
-\r
- hdmi_dbg(&client->dev, "\n\n**********************************ANX7150 Info**********************************\n");\r
-\r
- hdmi_dbg(&client->dev, " ANX7150 mode = Normal mode\n");\r
- if ((ANX7150_demux_yc_en == 1) && (ANX7150_emb_sync_mode == 0))\r
- hdmi_dbg(&client->dev, " Input video format = YC_MUX\n");\r
- if ((ANX7150_demux_yc_en == 0) && (ANX7150_emb_sync_mode == 1))\r
- hdmi_dbg(&client->dev, " Input video format = 656\n");\r
- if ((ANX7150_demux_yc_en == 1) && (ANX7150_emb_sync_mode == 1))\r
- hdmi_dbg(&client->dev, " Input video format = YC_MUX + 656\n");\r
- if ((ANX7150_demux_yc_en == 0) && (ANX7150_emb_sync_mode == 0))\r
- hdmi_dbg(&client->dev, " Input video format = Seperate Sync\n");\r
- if (ANX7150_de_gen_en)\r
- hdmi_dbg(&client->dev, " DE generator = Enable\n");\r
- else\r
- hdmi_dbg(&client->dev, " DE generator = Disable\n");\r
- if ((ANX7150_ddr_bus_mode == 1)&& (ANX7150_emb_sync_mode == 0))\r
- hdmi_dbg(&client->dev, " Input video format = DDR mode\n");\r
- else if ((ANX7150_ddr_bus_mode == 1)&& (ANX7150_emb_sync_mode == 1))\r
- hdmi_dbg(&client->dev, " Input video format = DDR mode + 656\n");\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_CTRL1_REG, &c1);\r
- c1 = (c1 & 0x02);\r
- if (c1)\r
- {\r
- hdmi_dbg(&client->dev, " Output video mode = HDMI\n");\r
- rc = anx7150_i2c_read_p0_reg(client, 0x04, &c);\r
- c = (c & 0x60) >> 5;\r
- switch (c)\r
- {\r
- case ANX7150_RGB:\r
- hdmi_dbg(&client->dev, " Output video color format = RGB\n");\r
- break;\r
- case ANX7150_YCbCr422:\r
- hdmi_dbg(&client->dev, " Output video color format = YCbCr422\n");\r
- break;\r
- case ANX7150_YCbCr444:\r
- hdmi_dbg(&client->dev, " Output video color format = YCbCr444\n");\r
- break;\r
- default:\r
- break;\r
- }\r
- }\r
- else\r
- {\r
- hdmi_dbg(&client->dev, " Output video mode = DVI\n");\r
- hdmi_dbg(&client->dev, " Output video color format = RGB\n");\r
- }\r
-\r
- /*for(i = 0x10; i < 0x25; i ++)\r
- {\r
- ANX7150_i2c_read_p0_reg(i, &c );\r
- D("0x%.2x = 0x%.2x\n",(unsigned int)i,(unsigned int)c);\r
- }*/\r
- /* ANX7150_i2c_read_p0_reg(ANX7150_VID_STATUS_REG, &c);\r
- if((c & ANX7150_VID_STATUS_TYPE) == 0x04)\r
- D("Video Type = Interlace");\r
- else\r
- D("Video Type = Progressive");\r
- ANX7150_i2c_read_p0_reg(ANX7150_VIDF_HRESH_REG, &c);\r
- h_res = c;\r
- h_res = h_res << 8;\r
- ANX7150_i2c_read_p0_reg(ANX7150_VIDF_HRESL_REG, &c);\r
- h_res = h_res + c;\r
- D("H_resolution = %u\n",h_res);\r
- ANX7150_i2c_read_p0_reg(ANX7150_VIDF_PIXH_REG, &c);\r
- h_act = c;\r
- h_act = h_act << 8;\r
- ANX7150_i2c_read_p0_reg(ANX7150_VIDF_PIXL_REG, &c);\r
- h_act = h_act + c;\r
- D("H_active = %u\n",h_act);\r
-\r
- ANX7150_i2c_read_p0_reg(ANX7150_VIDF_VRESH_REG, &c);\r
- v_res = c;\r
- v_res = v_res << 8;\r
- ANX7150_i2c_read_p0_reg(ANX7150_VIDF_VRESL_REG, &c);\r
- v_res = v_res + c;\r
- D("V_resolution = %u\n",v_res);\r
- ANX7150_i2c_read_p0_reg(ANX7150_VIDF_ACTVIDLINEH_REG, &c);\r
- v_act = c;\r
- v_act = v_act << 8;\r
- ANX7150_i2c_read_p0_reg(ANX7150_VIDF_ACTVIDLINEL_REG, &c);\r
- v_act = v_act + c;\r
- D("V_active = %u\n",v_act);\r
-\r
- ANX7150_i2c_read_p0_reg(ANX7150_VIDF_HFORNTPORCHH_REG, &c);\r
- h_fp = c;\r
- h_fp = h_fp << 8;\r
- ANX7150_i2c_read_p0_reg(ANX7150_VIDF_HFORNTPORCHL_REG, &c);\r
- h_fp = h_fp + c;\r
- D("H_FP = %u\n",h_fp);\r
-\r
- ANX7150_i2c_read_p0_reg(ANX7150_VIDF_HBACKPORCHH_REG, &c);\r
- h_bp = c;\r
- h_bp = h_bp << 8;\r
- ANX7150_i2c_read_p0_reg(ANX7150_VIDF_HBACKPORCHL_REG, &c);\r
- h_bp = h_bp + c;\r
- D("H_BP = %u\n",h_bp);\r
-\r
- ANX7150_i2c_read_p0_reg(ANX7150_VIDF_HSYNCWIDH_REG, &c);\r
- hsync_width = c;\r
- hsync_width = hsync_width << 8;\r
- ANX7150_i2c_read_p0_reg(ANX7150_VIDF_HSYNCWIDL_REG, &c);\r
- hsync_width = hsync_width + c;\r
- D("Hsync_width = %u\n",hsync_width);\r
-\r
- ANX7150_i2c_read_p0_reg(ANX7150_VIDF_ACTLINE2VSYNC_REG, &c);\r
- D("Vsync_FP = %bu\n",c);\r
-\r
- ANX7150_i2c_read_p0_reg(ANX7150_VIDF_VSYNCTAIL2VIDLINE_REG, &c);\r
- D("Vsync_BP = %bu\n",c);\r
-\r
- ANX7150_i2c_read_p0_reg(ANX7150_VIDF_VSYNCWIDLINE_REG, &c);\r
- D("Vsync_width = %bu\n",c);*/\r
- {\r
- hdmi_dbg(&client->dev, " Normal mode output video format: \n");\r
- switch (ANX7150_video_timing_id)\r
- {\r
- case ANX7150_V720x480p_60Hz_4x3:\r
- case ANX7150_V720x480p_60Hz_16x9:\r
- hdmi_dbg(&client->dev, "720x480p@60\n");\r
- if (ANX7150_edid_result.supported_720x480p_60Hz)\r
- hdmi_dbg(&client->dev, "and sink supports this format.\n");\r
- else\r
- hdmi_dbg(&client->dev, "but sink does not support this format.\n");\r
- break;\r
- case ANX7150_V1280x720p_60Hz:\r
- hdmi_dbg(&client->dev, "1280x720p@60\n");\r
- if (ANX7150_edid_result.supported_720p_60Hz)\r
- hdmi_dbg(&client->dev, "and sink supports this format.\n");\r
- else\r
- hdmi_dbg(&client->dev, "but sink does not support this format.\n");\r
- break;\r
- case ANX7150_V1920x1080i_60Hz:\r
- hdmi_dbg(&client->dev, "1920x1080i@60\n");\r
- if (ANX7150_edid_result.supported_1080i_60Hz)\r
- hdmi_dbg(&client->dev, "and sink supports this format.\n");\r
- else\r
- hdmi_dbg(&client->dev, "but sink does not support this format.\n");\r
- break;\r
- case ANX7150_V1920x1080p_60Hz:\r
- hdmi_dbg(&client->dev, "1920x1080p@60\n");\r
- if (ANX7150_edid_result.supported_1080p_60Hz)\r
- hdmi_dbg(&client->dev, "and sink supports this format.\n");\r
- else\r
- hdmi_dbg(&client->dev, "but sink does not support this format.\n");\r
- break;\r
- case ANX7150_V1920x1080p_50Hz:\r
- hdmi_dbg(&client->dev, "1920x1080p@50\n");\r
- if (ANX7150_edid_result.supported_1080p_50Hz)\r
- hdmi_dbg(&client->dev, "and sink supports this format.\n");\r
- else\r
- hdmi_dbg(&client->dev, "but sink does not support this format.\n");\r
- break;\r
- case ANX7150_V1280x720p_50Hz:\r
- hdmi_dbg(&client->dev, "1280x720p@50\n");\r
- if (ANX7150_edid_result.supported_720p_50Hz)\r
- hdmi_dbg(&client->dev, "and sink supports this format.\n");\r
- else\r
- hdmi_dbg(&client->dev, "but sink does not support this format.\n");\r
- break;\r
- case ANX7150_V1920x1080i_50Hz:\r
- hdmi_dbg(&client->dev, "1920x1080i@50\n");\r
- if (ANX7150_edid_result.supported_1080i_50Hz)\r
- hdmi_dbg(&client->dev, "and sink supports this format.\n");\r
- else\r
- hdmi_dbg(&client->dev, "but sink does not support this format.\n");\r
- break;\r
- case ANX7150_V720x576p_50Hz_4x3:\r
- case ANX7150_V720x576p_50Hz_16x9:\r
- hdmi_dbg(&client->dev, "720x576p@50\n");\r
- if (ANX7150_edid_result.supported_576p_50Hz)\r
- hdmi_dbg(&client->dev, "and sink supports this format.\n");\r
- else\r
- hdmi_dbg(&client->dev, "but sink does not support this format.\n");\r
- break;\r
- case ANX7150_V720x576i_50Hz_4x3:\r
- case ANX7150_V720x576i_50Hz_16x9:\r
- hdmi_dbg(&client->dev, "720x576i@50\n");\r
- if (ANX7150_edid_result.supported_576i_50Hz)\r
- hdmi_dbg(&client->dev, "and sink supports this format.\n");\r
- else\r
- hdmi_dbg(&client->dev, "but sink does not support this format.\n");\r
- break;\r
- case ANX7150_V720x480i_60Hz_4x3:\r
- case ANX7150_V720x480i_60Hz_16x9:\r
- hdmi_dbg(&client->dev, "720x480i@60\n");\r
- if (ANX7150_edid_result.supported_720x480i_60Hz)\r
- hdmi_dbg(&client->dev, "and sink supports this format.\n");\r
- else\r
- hdmi_dbg(&client->dev, "but sink does not support this format.\n");\r
- break;\r
- default:\r
- hdmi_dbg(&client->dev, "unknown(video ID is: %.2x).\n",(u32)ANX7150_video_timing_id);\r
- break;\r
- }\r
- }\r
- if (c1)//HDMI output\r
- {\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL0_REG, &c);\r
- c = c & 0x03;\r
- hdmi_dbg(&client->dev, " MCLK Frequence = ");\r
-\r
- switch (c)\r
- {\r
- case 0x00:\r
- hdmi_dbg(&client->dev, "128 * Fs.\n");\r
- break;\r
- case 0x01:\r
- hdmi_dbg(&client->dev, "256 * Fs.\n");\r
- break;\r
- case 0x02:\r
- hdmi_dbg(&client->dev, "384 * Fs.\n");\r
- break;\r
- case 0x03:\r
- hdmi_dbg(&client->dev, "512 * Fs.\n");\r
- break;\r
- default :\r
- hdmi_dbg(&client->dev, "Wrong MCLK output.\n");\r
- break;\r
- }\r
-\r
- if ( ANX7150_AUD_HW_INTERFACE == 0x01)\r
- {\r
- hdmi_dbg(&client->dev, " Input Audio Interface = I2S.\n");\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_I2SCH_STATUS4_REG, &c);\r
- }\r
- else if (ANX7150_AUD_HW_INTERFACE == 0x02)\r
- {\r
- hdmi_dbg(&client->dev, " Input Audio Interface = SPDIF.\n");\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_SPDIFCH_STATUS_REG, &c);\r
- c=c>>4;\r
- }\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_I2SCH_STATUS4_REG, &c);\r
- hdmi_dbg(&client->dev, " Audio Fs = ");\r
- c &= 0x0f;\r
- switch (c)\r
- {\r
- case 0x00:\r
- hdmi_dbg(&client->dev, " Audio Fs = 44.1 KHz.\n");\r
- break;\r
- case 0x02:\r
- hdmi_dbg(&client->dev, " Audio Fs = 48 KHz.\n");\r
- break;\r
- case 0x03:\r
- hdmi_dbg(&client->dev, " Audio Fs = 32 KHz.\n");\r
- break;\r
- case 0x08:\r
- hdmi_dbg(&client->dev, " Audio Fs = 88.2 KHz.\n");\r
- break;\r
- case 0x0a:\r
- hdmi_dbg(&client->dev, " Audio Fs = 96 KHz.\n\n");\r
- break;\r
- case 0x0c:\r
- hdmi_dbg(&client->dev, " Audio Fs = 176.4 KHz.\n");\r
- break;\r
- case 0x0e:\r
- hdmi_dbg(&client->dev, " Audio Fs = 192 KHz.\n");\r
- hdmi_dbg(&client->dev, "192 KHz.\n");\r
- break;\r
- default :\r
- hdmi_dbg(&client->dev, " Audio Fs = Wrong Fs output.\n");\r
- hdmi_dbg(&client->dev, "Wrong Fs output.\n");\r
- break;\r
- }\r
-\r
- if (ANX7150_HDCP_enable == 1)\r
- hdmi_dbg(&client->dev, " ANX7150_HDCP_Enable.\n");\r
- else\r
- hdmi_dbg(&client->dev, " ANX7150_HDCP_Disable.\n");\r
-\r
- }\r
- hdmi_dbg(&client->dev, "\n********************************************************************************\n\n");\r
-}\r
-void ANX7150_HDCP_Process(struct i2c_client *client, int enable)\r
-{\r
- int rc = 0;\r
- char c,i;\r
- //u8 c1;\r
- u8 Bksv_valid=0;//wen HDCP CTS\r
-\r
- if (ANX7150_HDCP_enable)\r
- { //HDCP_EN =1 means to do HDCP authentication,SWITCH4 = 0 means not to do HDCP authentication.\r
-\r
- //ANX7150_i2c_read_p0_reg(ANX7150_SYS_CTRL1_REG, &c);\r
- //ANX7150_i2c_write_p0_reg(ANX7150_SYS_CTRL1_REG, c | 0x04);//power on HDCP, 090630\r
-\r
- //ANX7150_i2c_read_p0_reg(ANX7150_INTR2_MASK_REG, &c);\r
- //ANX7150_i2c_write_p0_reg(ANX7150_INTR2_MASK_REG, c |0x03);\r
- mdelay(10);//let unencrypted video play a while, required by HDCP CTS. SY//wen HDCP CTS\r
- anx7150_set_avmute(client);//before auth, set_avmute//wen\r
- mdelay(10);//wen HDCP CTS\r
-\r
- if ( !ANX7150_hdcp_init_done )\r
- {\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_CTRL1_REG, &c);\r
- c |= ANX7150_SYS_CTRL1_HDCPMODE;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_SYS_CTRL1_REG, &c);\r
- if (ANX7150_edid_result.is_HDMI)\r
- rc = anx7150_hardware_hdcp_auth_init(client);\r
- else\r
- { //DVI, disable 1.1 feature and enable HDCP two special point check\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_CTRL1_REG, &c);\r
- c = ((c & (~ANX7150_HDCP_CTRL1_HDCP11_EN)) | ANX7150_LINK_CHK_12_EN);\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_CTRL1_REG, &c);\r
- }\r
-\r
- //wen HDCP CTS\r
- if (!anx7150_bksv_srm(client))\r
- {\r
- anx7150_blue_screen_enable(client);\r
- anx7150_clear_avmute(client);\r
- Bksv_valid=0;\r
- return;\r
- }\r
- else //SY.\r
- {\r
- Bksv_valid=1;\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
- c |= 0x03;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
- }\r
-\r
- ANX7150_hdcp_init_done = 1;\r
-//wen HDCP CTS\r
- }\r
-\r
-\r
-//wen HDCP CTS\r
- if ((Bksv_valid) && (!ANX7150_hdcp_auth_en))\r
- {\r
- hdmi_dbg(&client->dev, "enable hw hdcp\n");\r
- anx7150_rst_ddcchannel(client);\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
- c |= ANX7150_HDCP_CTRL0_HW_AUTHEN;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
- ANX7150_hdcp_auth_en = 1;\r
- }\r
-\r
- if ((Bksv_valid) && (ANX7150_hdcp_wait_100ms_needed))\r
- {\r
- ANX7150_hdcp_wait_100ms_needed = 0;\r
- //disable audio\r
-\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- c &= ~ANX7150_HDMI_AUDCTRL1_IN_EN;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- \r
- hdmi_dbg(&client->dev, "++++++++ANX7150_hdcp_wait_100ms_needed+++++++++\n");\r
- mdelay(150); // 100 -> 150\r
- return;\r
- }\r
-//wen HDCP CTS\r
-\r
- if (ANX7150_hdcp_auth_pass) //wen HDCP CTS\r
- {\r
- //Clear the SRM_Check_Pass u8, then when reauthentication occurs, firmware can catch it.\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
- c &= 0xfc;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
-\r
- //Enable HDCP Hardware encryption\r
- if (!ANX7150_hdcp_encryption)\r
- {\r
- anx7150_hdcp_encryption_enable(client);\r
- }\r
- if (ANX7150_send_blue_screen)\r
- {\r
- anx7150_blue_screen_disable(client);\r
- }\r
- if (ANX7150_avmute_enable)\r
- {\r
- anx7150_clear_avmute(client);\r
- }\r
-\r
- i = 0;\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_STATUS_REG, &c);\r
- while((c&0x04)==0x00)//wait for encryption.\r
- {\r
- mdelay(2);\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_STATUS_REG, &c);\r
- i++;\r
- if (i > 10)\r
- break;\r
- }\r
-\r
- //enable audio SY.\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- c |= ANX7150_HDMI_AUDCTRL1_IN_EN;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- hdmi_dbg(&client->dev, "@@@@@ HDCP Auth PASSED! @@@@@\n");\r
-\r
- if (ANX7150_hdcp_bcaps & 0x40) //repeater\r
- {\r
- hdmi_dbg(&client->dev, "Find a repeater!\n");\r
- //actually it is KSVList check. we can't do SRM check due to the lack of SRM file. SY.\r
- if (!ANX7150_srm_checked)\r
- {\r
- if (!anx7150_is_ksvlist_vld(client))\r
- {\r
- hdmi_dbg(&client->dev, "ksvlist not good. disable encryption");\r
- anx7150_hdcp_encryption_disable(client);\r
- anx7150_blue_screen_enable(client);\r
- anx7150_clear_avmute(client);\r
- ANX7150_ksv_srm_pass = 0;\r
- anx7150_clean_hdcp(client);//SY.\r
- //remove below will pass 1b-05/1b-06\r
- //ANX7150_Set_System_State(ANX7150_WAIT_HOTPLUG);//SY.\r
- return;\r
- }\r
- ANX7150_srm_checked=1;\r
- ANX7150_ksv_srm_pass = 1;\r
- }\r
- }\r
- else\r
- {\r
- hdmi_dbg(&client->dev, "Find a receiver.\n");\r
- }\r
- }\r
- else //wen HDCP CTS\r
- {\r
- hdmi_dbg(&client->dev, "##### HDCP Auth FAILED! #####\n");\r
- //also need to disable HW AUTHEN\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
- c &= ~ANX7150_HDCP_CTRL0_HW_AUTHEN;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDCP_CTRL0_REG, &c);\r
- ANX7150_hdcp_auth_en = 0;\r
- //ANX7150_hdcp_init_done = 0;\r
- //ANX7150_hdcp_wait_100ms_needed = 1; //wen, update 080703\r
-\r
- if (ANX7150_hdcp_encryption)\r
- {\r
- anx7150_hdcp_encryption_disable(client);\r
- }\r
- if (!ANX7150_send_blue_screen)\r
- {\r
- anx7150_blue_screen_enable(client);\r
- }\r
- if (ANX7150_avmute_enable)\r
- {\r
- anx7150_clear_avmute(client);\r
- }\r
- //disable audio\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- c &= ~ANX7150_HDMI_AUDCTRL1_IN_EN;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- \r
- return;\r
- }\r
-\r
- }\r
- else //wen HDCP CTS\r
- {\r
- hdmi_dbg(&client->dev, "hdcp pin is off.\n");\r
- if (ANX7150_send_blue_screen)\r
- {\r
- anx7150_blue_screen_disable(client);\r
- }\r
- if (ANX7150_avmute_enable)\r
- {\r
- anx7150_clear_avmute(client);\r
- }\r
- //enable audio SY.\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- c |= ANX7150_HDMI_AUDCTRL1_IN_EN;\r
- rc = anx7150_i2c_write_p0_reg(client, ANX7150_HDMI_AUDCTRL1_REG, &c);\r
- }\r
-\r
-//wen HDCP CTS\r
- rc = anx7150_i2c_read_p0_reg(client, ANX7150_SYS_CTRL1_REG, &c); //72:07.1 hdmi or dvi mode\r
- c = c & 0x02;\r
- if (c == 0x02)\r
- {\r
- hdmi_dbg(&client->dev, "end of ANX7150_HDCP_Process(): in HDMI mode.\n");\r
- }\r
- else\r
- {\r
- hdmi_dbg(&client->dev, "!end of ANX7150_HDCP_Process(): in DVI mode.\n");\r
- //To-Do: Config to DVI mode.\r
- }\r
-\r
- anx7150_show_video_parameter(client);\r
- if(!enable)\r
- anx7150_set_avmute(client);\r
-}\r
-\r
-void HDMI_Set_Video_Format(u8 video_format) //CPU set the lowpower mode\r
-{ \r
- switch (video_format)\r
- {\r
- case HDMI_1280x720p_50Hz:\r
- g_video_format = ANX7150_V1280x720p_50Hz;\r
- break;\r
- case HDMI_1280x720p_60Hz:\r
- g_video_format = ANX7150_V1280x720p_60Hz;\r
- break;\r
- case HDMI_720x576p_50Hz_4x3:\r
- g_video_format = ANX7150_V720x576p_50Hz_4x3;\r
- break;\r
- case HDMI_720x576p_50Hz_16x9:\r
- g_video_format = ANX7150_V720x576p_50Hz_16x9;\r
- break;\r
- case HDMI_720x480p_60Hz_4x3:\r
- g_video_format = ANX7150_V720x480p_60Hz_4x3;\r
- break;\r
- case HDMI_720x480p_60Hz_16x9:\r
- g_video_format = ANX7150_V720x480p_60Hz_16x9;\r
- break;\r
- case HDMI_1920x1080p_50Hz:\r
- g_video_format = ANX7150_V1920x1080p_50Hz;\r
- break;\r
- case HDMI_1920x1080p_60Hz:\r
- g_video_format = ANX7150_V1920x1080p_60Hz;\r
- break;\r
- default:\r
- g_video_format = ANX7150_V1280x720p_50Hz;\r
- break;\r
- }\r
-// ANX7150_system_config_done = 0;\r
-}\r
-void HDMI_Set_Audio_Fs( u8 audio_fs) //ANX7150 call this to check lowpower\r
-{\r
- g_audio_format = audio_fs;\r
-// ANX7150_system_config_done = 0;\r
-}\r
-int ANX7150_PLAYBACK_Process(void)\r
-{\r
-// D("enter\n");\r
-\r
- if ((s_ANX7150_packet_config.packets_need_config != 0x00) && (ANX7150_edid_result.is_HDMI == 1))\r
- {\r
- return 1;\r
- }\r
-\r
- return 0;\r
-}\r
-\r
-\r
+++ /dev/null
-#ifndef _ANX7150_HW_H\r
-#define _ANX7150_HW_H\r
-\r
-#include <linux/hdmi.h>\r
-\r
-#define EDID_LENGTH 128\r
-struct est_timings {\r
- u8 t1;\r
- u8 t2;\r
- u8 mfg_rsvd;\r
-} __attribute__((packed));\r
-\r
-struct std_timing {\r
- u8 hsize; /* need to multiply by 8 then add 248 */\r
- u8 vfreq_aspect;\r
-} __attribute__((packed));\r
-\r
-/* If detailed data is pixel timing */\r
-struct detailed_pixel_timing {\r
- u8 hactive_lo;\r
- u8 hblank_lo;\r
- u8 hactive_hblank_hi;\r
- u8 vactive_lo;\r
- u8 vblank_lo;\r
- u8 vactive_vblank_hi;\r
- u8 hsync_offset_lo;\r
- u8 hsync_pulse_width_lo;\r
- u8 vsync_offset_pulse_width_lo;\r
- u8 hsync_vsync_offset_pulse_width_hi;\r
- u8 width_mm_lo;\r
- u8 height_mm_lo;\r
- u8 width_height_mm_hi;\r
- u8 hborder;\r
- u8 vborder;\r
- u8 misc;\r
-} __attribute__((packed));\r
-\r
-/* If it's not pixel timing, it'll be one of the below */\r
-struct detailed_data_string {\r
- u8 str[13];\r
-} __attribute__((packed));\r
-\r
-struct detailed_data_monitor_range {\r
- u8 min_vfreq;\r
- u8 max_vfreq;\r
- u8 min_hfreq_khz;\r
- u8 max_hfreq_khz;\r
- u8 pixel_clock_mhz; /* need to multiply by 10 */\r
- __le16 sec_gtf_toggle; /* A000=use above, 20=use below */\r
- u8 hfreq_start_khz; /* need to multiply by 2 */\r
- u8 c; /* need to divide by 2 */\r
- __le16 m;\r
- u8 k;\r
- u8 j; /* need to divide by 2 */\r
-} __attribute__((packed));\r
-\r
-struct detailed_data_wpindex {\r
- u8 white_yx_lo; /* Lower 2 bits each */\r
- u8 white_x_hi;\r
- u8 white_y_hi;\r
- u8 gamma; /* need to divide by 100 then add 1 */\r
-} __attribute__((packed));\r
-\r
-struct detailed_data_color_point {\r
- u8 windex1;\r
- u8 wpindex1[3];\r
- u8 windex2;\r
- u8 wpindex2[3];\r
-} __attribute__((packed));\r
-\r
-struct cvt_timing {\r
- u8 code[3];\r
-} __attribute__((packed));\r
-\r
-struct detailed_non_pixel {\r
- u8 pad1;\r
- u8 type; /* ff=serial, fe=string, fd=monitor range, fc=monitor name\r
- fb=color point data, fa=standard timing data,\r
- f9=undefined, f8=mfg. reserved */\r
- u8 pad2;\r
- union {\r
- struct detailed_data_string str;\r
- struct detailed_data_monitor_range range;\r
- struct detailed_data_wpindex color;\r
- struct std_timing timings[6];\r
- struct cvt_timing cvt[4];\r
- } data;\r
-} __attribute__((packed));\r
-\r
-struct detailed_timing {\r
- __le16 pixel_clock; /* need to multiply by 10 KHz */\r
- union {\r
- struct detailed_pixel_timing pixel_data;\r
- struct detailed_non_pixel other_data;\r
- } data;\r
-} __attribute__((packed));\r
-\r
-struct edid {\r
- u8 header[8];\r
- /* Vendor & product info */\r
- u8 mfg_id[2];\r
- u8 prod_code[2];\r
- u32 serial; /* FIXME: byte order */\r
- u8 mfg_week;\r
- u8 mfg_year;\r
- /* EDID version */\r
- u8 version;\r
- u8 revision;\r
- /* Display info: */\r
- u8 input;\r
- u8 width_cm;\r
- u8 height_cm;\r
- u8 gamma;\r
- u8 features;\r
- /* Color characteristics */\r
- u8 red_green_lo;\r
- u8 black_white_lo;\r
- u8 red_x;\r
- u8 red_y;\r
- u8 green_x;\r
- u8 green_y;\r
- u8 blue_x;\r
- u8 blue_y;\r
- u8 white_x;\r
- u8 white_y;\r
- /* Est. timings and mfg rsvd timings*/\r
- struct est_timings established_timings;\r
- /* Standard timings 1-8*/\r
- struct std_timing standard_timings[8];\r
- /* Detailing timings 1-4 */\r
- struct detailed_timing detailed_timings[4];\r
- /* Number of 128 byte ext. blocks */\r
- u8 extensions;\r
- /* Checksum */\r
- u8 checksum;\r
-} __attribute__((packed));\r
-\r
-extern u8 timer_slot,misc_reset_needed;\r
-extern u8 bist_switch_value_pc,switch_value;\r
-extern u8 switch_value_sw_backup,switch_value_pc_backup;\r
-extern u8 ANX7150_system_state;\r
-extern u8 ANX7150_srm_checked;\r
-extern u8 ANX7150_HDCP_enable;\r
-extern u8 ANX7150_INT_Done;\r
-extern u8 FREQ_MCLK;\r
-//extern u8 int_s1, int_s2, int_s3;\r
-extern u8 HDMI_Mode_Auto_Manual,HDMI_Lowpower_Mode;\r
-\r
-struct anx7150_interrupt_s{\r
- int hotplug_change;\r
- int video_format_change;\r
- int auth_done;\r
- int auth_state_change;\r
- int pll_lock_change;\r
- int rx_sense_change;\r
- int HDCP_link_change;\r
- int audio_clk_change;\r
- int audio_FIFO_overrun;\r
- int SPDIF_bi_phase_error;\r
- int SPDIF_error;\r
-};\r
-typedef struct\r
-{\r
- u8 is_HDMI;\r
- u8 ycbcr444_supported;\r
- u8 ycbcr422_supported;\r
- u8 supported_1080p_60Hz;\r
- u8 supported_1080p_50Hz;\r
- u8 supported_1080i_60Hz;\r
- u8 supported_1080i_50Hz;\r
- u8 supported_720p_60Hz;\r
- u8 supported_720p_50Hz;\r
- u8 supported_576p_50Hz;\r
- u8 supported_576i_50Hz;\r
- u8 supported_640x480p_60Hz;\r
- u8 supported_720x480p_60Hz;\r
- u8 supported_720x480i_60Hz;\r
- u8 AudioFormat[10];//MAX audio STD block is 10(0x1f / 3)\r
- u8 AudioChannel[10];\r
- u8 AudioFs[10];\r
- u8 AudioLength[10];\r
- u8 SpeakerFormat;u8 edid_errcode;}ANX7150_edid_result_4_system;\r
- extern ANX7150_edid_result_4_system ANX7150_edid_result;\r
-//#define ITU656\r
-//#ifdef ITU656\r
-struct ANX7150_video_timingtype{ //CEA-861C format\r
- u8 ANX7150_640x480p_60Hz[18];//format 1\r
- u8 ANX7150_720x480p_60Hz[18];//format 2 & 3\r
- u8 ANX7150_1280x720p_60Hz[18];//format 4\r
- u8 ANX7150_1920x1080i_60Hz[18];//format 5\r
- u8 ANX7150_720x480i_60Hz[18];//format 6 & 7\r
- u8 ANX7150_1920x1080p_60Hz[18];\r
- //u8 ANX7150_720x240p_60Hz[18];//format 8 & 9\r
- //u8 ANX7150_2880x480i_60Hz[18];//format 10 & 11\r
- //u8 ANX7150_2880x240p_60Hz[18];//format 12 & 13\r
- //u8 ANX7150_1440x480p_60Hz[18];//format 14 & 15\r
- //u8 ANX7150_1920x1080p_60Hz[18];//format 16\r
- u8 ANX7150_720x576p_50Hz[18];//format 17 & 18\r
- u8 ANX7150_1280x720p_50Hz[18];//format 19\r
- u8 ANX7150_1920x1080i_50Hz[18];//format 20*/\r
- u8 ANX7150_720x576i_50Hz[18];//format 21 & 22\r
- u8 ANX7150_1920x1080p_50Hz[18];\r
- /* u8 ANX7150_720x288p_50Hz[18];//formats 23 & 24\r
- u8 ANX7150_2880x576i_50Hz[18];//formats 25 & 26\r
- u8 ANX7150_2880x288p_50Hz[18];//formats 27 & 28\r
- u8 ANX7150_1440x576p_50Hz[18];//formats 29 & 30\r
- u8 ANX7150_1920x1080p_50Hz[18];//format 31\r
- u8 ANX7150_1920x1080p_24Hz[18];//format 32\r
- u8 ANX7150_1920x1080p_25Hz[18];//format 33\r
- u8 ANX7150_1920x1080p_30Hz[18];//format 34*/\r
-};\r
-//#endif\r
-// 8 type of packets are legal, It is possible to sent 6 types in the same time;\r
-// So select 6 types below at most;\r
-// avi_infoframe and audio_infoframe have fixxed address;\r
-// config other selected types of packet to the rest 4 address with no limits.\r
-typedef enum\r
-{\r
- ANX7150_avi_infoframe,\r
- ANX7150_audio_infoframe,\r
- /*ANX7150_spd_infoframe,\r
- ANX7150_mpeg_infoframe,\r
- ANX7150_acp_packet,\r
- ANX7150_isrc1_packet,\r
- ANX7150_isrc2_packet,\r
- ANX7150_vendor_infoframe,*/\r
-}packet_type;\r
-\r
-typedef struct\r
-{\r
- u8 type;\r
- u8 version;\r
- u8 length;\r
- u8 pb_u8[28];\r
-}infoframe_struct;\r
-\r
-typedef struct\r
-{\r
- u8 packets_need_config; //which infoframe packet is need updated\r
- infoframe_struct avi_info;\r
- infoframe_struct audio_info;\r
- /* for the funture use\r
- infoframe_struct spd_info;\r
- infoframe_struct mpeg_info;\r
- infoframe_struct acp_pkt;\r
- infoframe_struct isrc1_pkt;\r
- infoframe_struct isrc2_pkt;\r
- infoframe_struct vendor_info; */\r
-\r
-} config_packets;\r
-/*\r
- u8 i2s_format;\r
-\r
- u8(s) Name Type Default Description\r
- 7 EXT_VUCP R/W 0x0\r
- Enable indicator of VUCP u8s extraction from input\r
- I2S audio stream. 0 = disable; 1 = enable.\r
- 6:5 MCLK_PHS_CTRL R/W 0x0\r
- MCLK phase control for audio SPDIF input, which value\r
- is depended on the value of MCLK frequency set and not great than it.\r
- 4 Reserved\r
- 3 SHIFT_CTRL R/W 0x0\r
- WS to SD shift first u8. 0 = fist u8 shift (Philips Spec); 1 = no shift.\r
- 2 DIR_CTRL R/W 0x0\r
- SD data Indian (MSB or LSB first) control. 0 = MSB first; 1 = LSB first.\r
- 1 WS_POL R/W 0x0\r
- Word select left/right polarity select. 0 = left polarity\r
- when works select is low; 1 = left polarity when word select is high.\r
- 0 JUST_CTRL R/W 0x0\r
- SD Justification control. 1 = data is right justified;\r
- 0 = data is left justified.\r
-\r
-*/\r
-/*\r
- u8 audio_channel\r
-u8(s) Name Type Default Description\r
-5 AUD_SD3_IN R/W 0x0 Set I2S input channel #3 enable. 0 = disable; 1 = enable.\r
-4 AUD_SD2_IN R/W 0x0 Set I2S input channel #2 enable. 0 = disable; 1 = enable.\r
-3 AUD_SD1_IN R/W 0x0 Set I2S input channel #1 enable. 0 = disable; 1 = enable.\r
-2 AUD_SD0_IN R/W 0x0 Set I2S input channel #0 enable. 0 = disable; 1 = enable.\r
-\r
-\r
-*/\r
-/*\r
- u8 i2s_map0\r
-u8(s) Name Type Default Description\r
-7:6 FIFO3_SEL R/W 0x3 I2S Channel data stream select for audio FIFO 3. 0 = SD 0; 1 = SD 1; 2 = SD 2; 3 = SD 3;\r
-5:4 FIFO2_SEL R/W 0x2 I2S Channel data stream select for audio FIFO 2. 0 = SD 0; 1 = SD 1; 2 = SD 2; 3 = SD 3;\r
-3:2 FIFO1_SEL R/W 0x1 I2S Channel data stream select for audio FIFO 1. 0 = SD 0; 1 = SD 1; 2 = SD 2; 3 = SD 3;\r
-1:0 FIFO0_SEL R/W 0x0 I2S Channel data stream select for audio FIFO 0. 0 = SD 0; 1 = SD 1; 2 = SD 2; 3 = SD 3;\r
-\r
- u8 i2s_map1\r
-u8(s) Name Type Default Description\r
-7 SW3 R/W 0x0 Swap left/right channel on I2S channel 3. 1 = swap; 0 = no swap.\r
-6 SW2 R/W 0x0 Swap left/right channel on I2S channel 2. 1 = swap; 0 = no swap.\r
-5 SW1 R/W 0x0 Swap left/right channel on I2S channel 1. 1 = swap; 0 = no swap.\r
-4 SW0 R/W 0x0 Swap left/right channel on I2S channel 0. 1 = swap; 0 = no swap.\r
-3:1 IN_WORD_LEN R/W 0x5 Input I2S audio word length (corresponding to channel status u8s [35:33]). When IN_WORD_MAX = 0, 001 = 16 u8s; 010 = 18 u8s; 100 = 19 u8s; 101 = 20 u8s; 110 = 17 u8s; when IN_WORD_MAX = 1, 001 = 20 u8s; 010 = 22 u8s; 100 = 23 u8s; 101 = 24 u8s; 110 = 21 u8s.\r
-0 IN_WORD_MAX R/W 0x1 Input I2S audio word length Max (corresponding to channel status u8s 32). 0 = maximal word length is 20 u8s; 1 = maximal word length is 24 u8s.\r
-*/\r
-/*\r
- u8 Channel_status1\r
-u8(s) Name Type Default Description\r
-7:6 MODE R/W 0x0 00 = PCM Audio\r
-5:3 PCM_MODE R/W 0x0 000 = 2 audio channels without pre-emphasis;\r
- 001 = 2 audio channels with 50/15 usec pre-emphasis\r
-2 SW_CPRGT R/W 0x0 0 = software for which copyright is asserted;\r
- 1 = software for which no copyright is asserted\r
-1 NON_PCM R/W 0x0 0 = audio sample word represents linear PCM samples;\r
- 1 = audio sample word used for other purposes.\r
-0 PROF_APP R/W 0x0 0 = consumer applications; 1 = professional applications.\r
-\r
- u8 Channel_status2\r
-u8(s) Name Type Default Description\r
-7:0 CAT_CODE R/W 0x0 Category code (corresponding to channel status u8s [15:8])\r
-\r
- u8 Channel_status3\r
-u8(s) Name Type Default Description\r
-7:4 CH_NUM R/W 0x0 Channel number (corresponding to channel status u8s [23:20])\r
-3:0 SOURCE_NUM R/W 0x0 Source number (corresponding to channel status u8s [19:16])\r
-\r
- u8 Channel_status4\r
-u8(s) Name Type Default Description\r
-7:6 CHNL_u81 R/W 0x0 corresponding to channels status u8s [31:30]\r
-5:4 CLK_ACCUR R/W 0x0 Clock accuracy (corresponding to channels status u8s [29:28]). These two u8s define the sampling frequency tolerance. The u8s are set in the transmitter.\r
-3:0 FS_FREQ R/W 0x0 Sampling clock frequency (corresponding to channel status u8s [27:24]). 0000 = 44.1 KHz; 0010 = 48 KHz; 0011 = 32 KHz; 1000 = 88.2 KHz; 1010 = 96 KHz; 176.4 KHz; 1110 = 192 KHz; others = reserved.\r
-\r
- u8 Channel_status5\r
-u8(s) Name Type Default Description\r
-7:4 CHNL_u82 R/W 0x0 corresponding to channels status u8s [39:36]\r
-3:1 WORD_LENGTH R/W 0x5 Audio word length (corresponding to channel status u8s [35:33]). When WORD_MAX = 0, 001 = 16 u8s; 010 = 18 u8s; 100 = 19 u8s; 101 = 20 u8s; 110 = 17 u8s; when WORD_MAX = 1, 001 = 20 u8s; 010 = 22 u8s; 100 = 23 u8s; 101 = 24 u8s; 110 = 21 u8s.\r
-0 WORD_MAX R/W 0x1 Audio word length Max (corresponding to channel status u8s 32). 0 = maximal word length is 20 u8s; 1 = maximal word length is 24 u8s.\r
-\r
-*/\r
-typedef struct\r
-{\r
- u8 audio_channel;\r
- u8 i2s_format;\r
- u8 i2s_swap;\r
- u8 Channel_status1;\r
- u8 Channel_status2;\r
- u8 Channel_status3;\r
- u8 Channel_status4;\r
- u8 Channel_status5;\r
-} i2s_config_struct;\r
-/*\r
- u8 FS_FREQ;\r
-\r
- 7:4 FS_FREQ R 0x0\r
- Sampling clock frequency (corresponding to channel status u8s [27:24]).\r
- 0000 = 44.1 KHz; 0010 = 48 KHz; 0011 = 32 KHz; 1000 = 88.2 KHz; 1010 = 96 KHz;\r
- 176.4 KHz; 1110 = 192 KHz; others = reserved.\r
-*/\r
-\r
-typedef struct\r
-{\r
- u8 one_u8_ctrl;\r
-\r
-} super_audio_config_struct;\r
-\r
-typedef struct\r
-{\r
- u8 audio_type; // audio type\r
- // #define ANX7150_i2s_input 0x01\r
- // #define ANX7150_spdif_input 0x02\r
- // #define ANX7150_super_audio_input 0x04\r
-\r
- u8 down_sample; // 0x72:0x50\r
- // 0x00: 00 no down sample\r
- // 0x20: 01 2 to 1 down sample\r
- // 0x60: 11 4 to 1 down sample\r
- // 0x40: 10 reserved\r
- u8 audio_layout;//audio layout;\r
- //0x00, 2-channel\r
- //0x80, 8-channel\r
-\r
- i2s_config_struct i2s_config;\r
- super_audio_config_struct super_audio_config;\r
-\r
-} audio_config_struct;\r
-\r
-/*added by gerard.zhu*/\r
-/*DDC type*/\r
-typedef enum {\r
- DDC_Hdcp,\r
- DDC_Edid,\r
-}ANX7150_DDC_Type;\r
-\r
-/*Read DDC status type*/\r
-typedef enum {\r
- report,\r
- Judge,\r
-}ANX7150_DDC_Status_Check_Type;\r
-\r
-/*Define DDC address struction*/\r
-typedef struct {\r
- u8 dev_addr;\r
- u8 sgmt_addr;\r
- u8 offset_addr;\r
-}ANX7150_DDC_Addr;\r
-\r
-/*DDC status u8*/\r
-#define DDC_Error_u8 0x07\r
-#define DDC_Occup_u8 0x06\r
-#define DDC_Fifo_Full_u8 0x05\r
-#define DDC_Fifo_Empt_u8 0x04\r
-#define DDC_No_Ack_u8 0x03\r
-#define DDC_Fifo_Rd_u8 0x02\r
-#define DDC_Fifo_Wr_u8 0x01\r
-#define DDC_Progress_u8 0x00\r
-\r
-#define YCbCr422 0x20\r
-#define null 0\r
-#define source_ratio 0x08\r
-\r
-/*DDC Command*/\r
-#define Abort_Current_Operation 0x00\r
-#define Sequential_u8_Read 0x01\r
-#define Sequential_u8_Write 0x02\r
-#define Implicit_Offset_Address_Read 0x3\r
-#define Enhanced_DDC_Sequenital_Read 0x04\r
-#define Clear_DDC_Fifo 0x05\r
-#define I2c_reset 0x06\r
-\r
-/*DDC result*/\r
-#define DDC_NO_Err 0x00\r
-#define DDC_Status_Err 0x01\r
-#define DDC_Data_Addr_Err 0x02\r
-#define DDC_Length_Err 0x03\r
-\r
-/*checksum result*/\r
-#define Edid_Checksum_No_Err 0x00\r
-#define Edid_Checksum_Err 0x01\r
-\r
-/*HDCP device base address*/\r
-#define HDCP_Dev_Addr 0x74\r
-\r
-/*HDCP Bksv offset*/\r
-#define HDCP_Bksv_Offset 0x00\r
-\r
-/*HDCP Bcaps offset*/\r
-#define HDCP_Bcaps_Offset 0x40\r
-\r
-/*HDCP Bstatus offset*/\r
-#define HDCP_Bstatus_offset 0x41\r
-\r
-/*HDCP KSV Fifo offset */\r
-#define HDCP_Ksv_Fifo_Offset 0x43\r
-\r
-/*HDCP bksv data nums*/\r
-#define Bksv_Data_Nums 5\r
-\r
-/*HDCP ksvs data number by defult*/\r
-#define ksvs_data_nums 50\r
-\r
-/*DDC Max u8s*/\r
-#define DDC_Max_Length 1024\r
-\r
-/*DDC fifo depth*/\r
-#define DDC_Fifo_Depth 16\r
-\r
-/*DDC read delay ms*/\r
-#define DDC_Read_Delay 3\r
-\r
-/*DDC Write delay ms*/\r
-#define DDC_Write_Delay 3\r
-/*end*/\r
-\r
-extern u8 ANX7150_parse_edid_done;\r
-extern u8 ANX7150_system_config_done;\r
-extern u8 ANX7150_video_format_config,ANX7150_video_timing_id;\r
-extern u8 ANX7150_new_csc,ANX7150_new_vid_id,ANX7150_new_HW_interface;\r
-extern u8 ANX7150_ddr_edge;\r
-extern u8 ANX7150_in_pix_rpt_bkp,ANX7150_tx_pix_rpt_bkp;\r
-extern u8 ANX7150_in_pix_rpt,ANX7150_tx_pix_rpt;\r
-extern u8 ANX7150_pix_rpt_set_by_sys;\r
-extern u8 ANX7150_RGBorYCbCr;\r
-extern audio_config_struct s_ANX7150_audio_config;\r
-extern config_packets s_ANX7150_packet_config;\r
-\r
-//********************** BIST Enable***********************************\r
-\r
-\r
-#define ddr_falling_edge 1\r
-#define ddr_rising_edge 0\r
-\r
-#define input_pixel_clk_1x_repeatition 0x00\r
-#define input_pixel_clk_2x_repeatition 0x01\r
-#define input_pixel_clk_4x_repeatition 0x03\r
-\r
-//***********************Video Config***********************************\r
-#define ANX7150_RGB_YCrCb444_SepSync 0\r
-#define ANX7150_YCrCb422_SepSync 1\r
-#define ANX7150_YCrCb422_EmbSync 2\r
-#define ANX7150_YCMux422_SepSync_Mode1 3\r
-#define ANX7150_YCMux422_SepSync_Mode2 4\r
-#define ANX7150_YCMux422_EmbSync_Mode1 5\r
-#define ANX7150_YCMux422_EmbSync_Mode2 6\r
-#define ANX7150_RGB_YCrCb444_DDR_SepSync 7\r
-#define ANX7150_RGB_YCrCb444_DDR_EmbSync 8\r
-\r
-#define ANX7150_RGB_YCrCb444_SepSync_No_DE 9\r
-#define ANX7150_YCrCb422_SepSync_No_DE 10\r
-\r
-#define ANX7150_Progressive 0\r
-#define ANX7150_Interlace 0x08\r
-#define ANX7150_Neg_Hsync_pol 0x20\r
-#define ANX7150_Pos_Hsync_pol 0\r
-#define ANX7150_Neg_Vsync_pol 0x40\r
-#define ANX7150_Pos_Vsync_pol 0\r
-\r
-#define ANX7150_V640x480p_60Hz 1\r
-#define ANX7150_V720x480p_60Hz_4x3 2\r
-#define ANX7150_V720x480p_60Hz_16x9 3\r
-#define ANX7150_V1280x720p_60Hz 4\r
-#define ANX7150_V1280x720p_50Hz 19\r
-#define ANX7150_V1920x1080i_60Hz 5\r
-#define ANX7150_V1920x1080p_60Hz 16\r
-#define ANX7150_V1920x1080p_50Hz 31\r
-#define ANX7150_V1920x1080i_50Hz 20\r
-#define ANX7150_V720x480i_60Hz_4x3 6\r
-#define ANX7150_V720x480i_60Hz_16x9 7\r
-#define ANX7150_V720x576i_50Hz_4x3 21\r
-#define ANX7150_V720x576i_50Hz_16x9 22\r
-#define ANX7150_V720x576p_50Hz_4x3 17\r
-#define ANX7150_V720x576p_50Hz_16x9 18\r
-\r
-#define ANX7150_RGB 0x00\r
-#define ANX7150_YCbCr422 0x01\r
-#define ANX7150_YCbCr444 0x02\r
-#define ANX7150_CSC_BT709 1\r
-#define ANX7150_CSC_BT601 0\r
-\r
-#define ANX7150_EMBEDED_BLUE_SCREEN_ENABLE 1\r
-#define ANX7150_HDCP_FAIL_THRESHOLD 10\r
-\r
-#define ANX7150_avi_sel 0x01\r
-#define ANX7150_audio_sel 0x02\r
-#define ANX7150_spd_sel 0x04\r
-#define ANX7150_mpeg_sel 0x08\r
-#define ANX7150_acp_sel 0x10\r
-#define ANX7150_isrc1_sel 0x20\r
-#define ANX7150_isrc2_sel 0x40\r
-#define ANX7150_vendor_sel 0x80\r
-\r
-// audio type\r
-#define ANX7150_i2s_input 0x01\r
-#define ANX7150_spdif_input 0x02\r
-#define ANX7150_super_audio_input 0x04\r
-// freq_mclk\r
-#define ANX7150_mclk_128_Fs 0x00\r
-#define ANX7150_mclk_256_Fs 0x01\r
-#define ANX7150_mclk_384_Fs 0x02\r
-#define ANX7150_mclk_512_Fs 0x03\r
-// thresholds\r
-#define ANX7150_spdif_stable_th 0x03\r
-// fs -> N(ACR)\r
-#define ANX7150_N_32k 0x1000\r
-#define ANX7150_N_44k 0x1880\r
-#define ANX7150_N_88k 0x3100\r
-#define ANX7150_N_176k 0x6200\r
-#define ANX7150_N_48k 0x1800\r
-#define ANX7150_N_96k 0x3000\r
-#define ANX7150_N_192k 0x6000\r
-\r
-#define spdif_error_th 0x0a\r
-\r
-#define Hresolution_1920 1920\r
-#define Vresolution_540 540\r
-#define Vresolution_1080 1080\r
-#define Hresolution_1280 1280\r
-#define Vresolution_720 720\r
-#define Hresolution_640 640\r
-#define Vresolution_480 480\r
-#define Hresolution_720 720\r
-#define Vresolution_240 240\r
-#define Vresolution_576 576\r
-#define Vresolution_288 288\r
-#define Hz_50 50\r
-#define Hz_60 60\r
-#define Interlace_EDID 0\r
-#define Progressive_EDID 1\r
-#define ratio_16_9 1.777778\r
-#define ratio_4_3 1.333333\r
-\r
-#define ANX7150_EDID_BadHeader 0x01\r
-#define ANX7150_EDID_861B_not_supported 0x02\r
-#define ANX7150_EDID_CheckSum_ERR 0x03\r
-#define ANX7150_EDID_No_ExtBlock 0x04\r
-#define ANX7150_EDID_ExtBlock_NotFor_861B 0x05\r
-\r
-#define ANX7150_VND_IDL_REG 0x00\r
-#define ANX7150_VND_IDH_REG 0x01\r
-#define ANX7150_DEV_IDL_REG 0x02\r
-#define ANX7150_DEV_IDH_REG 0x03\r
-#define ANX7150_DEV_REV_REG 0x04\r
-\r
-#define ANX7150_SRST_REG 0x05\r
-#define ANX7150_TX_RST 0x40\r
-#define ANX7150_SRST_VIDCAP_RST 0x20 // u8 position\r
-#define ANX7150_SRST_AFIFO_RST 0x10 // u8 position\r
-#define ANX7150_SRST_HDCP_RST 0x08 // u8 position\r
-#define ANX7150_SRST_VID_FIFO_RST 0x04 // u8 position\r
-#define ANX7150_SRST_AUD_RST 0x02 // u8 position\r
-#define ANX7150_SRST_SW_RST 0x01 // u8 position\r
-\r
-#define ANX7150_SYS_STATE_REG 0x06\r
-#define ANX7150_SYS_STATE_AUD_CLK_DET 0x20 // u8 position\r
-#define ANX7150_SYS_STATE_AVMUTE 0x10 // u8 position\r
-#define ANX7150_SYS_STATE_HP 0x08 // u8 position\r
-#define ANX7150_SYS_STATE_VSYNC 0x04 // u8 position\r
-#define ANX7150_SYS_STATE_CLK_DET 0x02 // u8 position\r
-#define ANX7150_SYS_STATE_RSV_DET 0x01 // u8 position\r
-\r
-#define ANX7150_SYS_CTRL1_REG 0x07\r
-#define ANX7150_SYS_CTRL1_LINKMUTE_EN 0x80 // u8 position\r
-#define ANX7150_SYS_CTRL1_HDCPHPD_RST 0x40 // u8 position\r
-#define ANX7150_SYS_CTRL1_PDINT_SEL 0x20 // u8 position\r
-#define ANX7150_SYS_CTRL1_DDC_FAST 0x10 // u8 position\r
-#define ANX7150_SYS_CTRL1_DDC_SWCTRL 0x08 // u8 position\r
-#define ANX7150_SYS_CTRL1_HDCPMODE 0x04 // u8 position\r
-#define ANX7150_SYS_CTRL1_HDMI 0x02 // u8 position\r
-#define ANX7150_SYS_CTRL1_PWDN_CTRL 0x01 // u8 position\r
-\r
-#define ANX7150_SYS_CTRL2_REG 0x08\r
-#define ANX7150_SYS_CTRL2_DDC_RST 0x08 // u8 position\r
-#define ANX7150_SYS_CTRL2_TMDSBIST_RST 0x04 // u8 position\r
-#define ANX7150_SYS_CTRL2_MISC_RST 0x02 // u8 position\r
-#define ANX7150_SYS_CTRL2_HW_RST 0x01 // u8 position\r
-\r
-#define ANX7150_SYS_CTRL3_REG 0x09\r
-#define ANX7150_SYS_CTRL3_I2C_PWON 0x02\r
-#define ANX7150_SYS_CTRL3_PWON_ALL 0x01\r
-\r
-#define ANX7150_SYS_CTRL4_REG 0x0b\r
-\r
-#define ANX7150_VID_STATUS_REG 0x10\r
-#define ANX7150_VID_STATUS_VID_STABLE 0x20 // u8 position\r
-#define ANX7150_VID_STATUS_EMSYNC_ERR 0x10 // u8 position\r
-#define ANX7150_VID_STATUS_FLD_POL 0x08 // u8 position\r
-#define ANX7150_VID_STATUS_TYPE 0x04 // u8 position\r
-#define ANX7150_VID_STATUS_VSYNC_POL 0x02 // u8 position\r
-#define ANX7150_VID_STATUS_HSYNC_POL 0x01 // u8 position\r
-\r
-#define ANX7150_VID_MODE_REG 0x11\r
-#define ANX7150_VID_MODE_CHKSHARED_EN 0x80 // u8 position\r
-#define ANX7150_VID_MODE_LINKVID_EN 0x40 // u8 position\r
-#define ANX7150_VID_MODE_RANGE_Y2R 0x20 // u8 position\r
-#define ANX7150_VID_MODE_CSPACE_Y2R 0x10 // u8 position\r
-#define ANX7150_VID_MODE_Y2R_SEL 0x08 // u8 position\r
-#define ANX7150_VID_MODE_UPSAMPLE 0x04 // u8 position\r
-\r
-#define ANX7150_VID_CTRL_REG 0x12\r
-#define ANX7150_VID_CTRL_IN_EN 0x10 // u8 position\r
-#define ANX7150_VID_CTRL_YCu8_SEL 0x08 // u8 position\r
-#define ANX7150_VID_CTRL_u8CTRL_EN 0x04 // u8 position\r
-\r
-#define ANX7150_VID_CAPCTRL0_REG 0x13\r
-#define ANX7150_VID_CAPCTRL0_DEGEN_EN 0x80 // u8 position\r
-#define ANX7150_VID_CAPCTRL0_EMSYNC_EN 0x40 // u8 position\r
-#define ANX7150_VID_CAPCTRL0_DEMUX_EN 0x20 // u8 position\r
-#define ANX7150_VID_CAPCTRL0_INV_IDCK 0x10 // u8 position\r
-#define ANX7150_VID_CAPCTRL0_DV_BUSMODE 0x08 // u8 position\r
-#define ANX7150_VID_CAPCTRL0_DDR_EDGE 0x04 // u8 position\r
-#define ANX7150_VID_CAPCTRL0_VIDu8_SWAP 0x02 // u8 position\r
-#define ANX7150_VID_CAPCTRL0_VIDBIST_EN 0x01 // u8 position\r
-\r
-#define ANX7150_VID_CAPCTRL1_REG 0x14\r
-#define ANX7150_VID_CAPCTRL1_FORMAT_SEL 0x80 // u8 position\r
-#define ANX7150_VID_CAPCTRL1_VSYNC_POL 0x40 // u8 position\r
-#define ANX7150_VID_CAPCTRL1_HSYNC_POL 0x20 // u8 position\r
-#define ANX7150_VID_CAPCTRL1_INV_FLDPOL 0x10 // u8 position\r
-#define ANX7150_VID_CAPCTRL1_VID_TYPE 0x08 // u8 position\r
-\r
-#define ANX7150_H_RESL_REG 0x15\r
-#define ANX7150_H_RESH_REG 0x16\r
-#define ANX7150_VID_PIXL_REG 0x17\r
-#define ANX7150_VID_PIXH_REG 0x18\r
-#define ANX7150_H_FRONTPORCHL_REG 0x19\r
-#define ANX7150_H_FRONTPORCHH_REG 0x1A\r
-#define ANX7150_HSYNC_ACT_WIDTHL_REG 0x1B\r
-#define ANX7150_HSYNC_ACT_WIDTHH_REG 0x1C\r
-#define ANX7150_H_BACKPORCHL_REG 0x1D\r
-#define ANX7150_H_BACKPORCHH_REG 0x1E\r
-#define ANX7150_V_RESL_REG 0x1F\r
-#define ANX7150_V_RESH_REG 0x20\r
-#define ANX7150_ACT_LINEL_REG 0x21\r
-#define ANX7150_ACT_LINEH_REG 0x22\r
-#define ANX7150_ACT_LINE2VSYNC_REG 0x23\r
-#define ANX7150_VSYNC_WID_REG 0x24\r
-#define ANX7150_VSYNC_TAIL2VIDLINE_REG 0x25\r
-#define ANX7150_VIDF_HRESL_REG 0x26\r
-#define ANX7150_VIDF_HRESH_REG 0x27\r
-#define ANX7150_VIDF_PIXL_REG 0x28\r
-#define ANX7150_VIDF_PIXH_REG 0x29\r
-#define ANX7150_VIDF_HFORNTPORCHL_REG 0x2A\r
-#define ANX7150_VIDF_HFORNTPORCHH_REG 0x2B\r
-#define ANX7150_VIDF_HSYNCWIDL_REG 0x2C\r
-#define ANX7150_VIDF_HSYNCWIDH_REG 0x2D\r
-#define ANX7150_VIDF_HBACKPORCHL_REG 0x2E\r
-#define ANX7150_VIDF_HBACKPORCHH_REG 0x2F\r
-#define ANX7150_VIDF_VRESL_REG 0x30\r
-#define ANX7150_VIDF_VRESH_REG 0x31\r
-#define ANX7150_VIDF_ACTVIDLINEL_REG 0x32\r
-#define ANX7150_VIDF_ACTVIDLINEH_REG 0x33\r
-#define ANX7150_VIDF_ACTLINE2VSYNC_REG 0x34\r
-#define ANX7150_VIDF_VSYNCWIDLINE_REG 0x35\r
-#define ANX7150_VIDF_VSYNCTAIL2VIDLINE_REG 0x36\r
-\r
-//Video input data u8 control registers\r
-\r
-#define VID_u8_CTRL0 0x37 //added\r
-#define VID_u8_CTRL1 0x38\r
-#define VID_u8_CTRL2 0x39\r
-#define VID_u8_CTRL3 0x3A\r
-#define VID_u8_CTRL4 0x3B\r
-#define VID_u8_CTRL5 0x3C\r
-#define VID_u8_CTRL6 0x3D\r
-#define VID_u8_CTRL7 0x3E\r
-#define VID_u8_CTRL8 0x3F\r
-#define VID_u8_CTRL9 0x48\r
-#define VID_u8_CTRL10 0x49\r
-#define VID_u8_CTRL11 0x4A\r
-#define VID_u8_CTRL12 0x4B\r
-#define VID_u8_CTRL13 0x4C\r
-#define VID_u8_CTRL14 0x4D\r
-#define VID_u8_CTRL15 0x4E\r
-#define VID_u8_CTRL16 0x4F\r
-#define VID_u8_CTRL17 0x89\r
-#define VID_u8_CTRL18 0x8A\r
-#define VID_u8_CTRL19 0x8B\r
-#define VID_u8_CTRL20 0x8C\r
-#define VID_u8_CTRL21 0x8D\r
-#define VID_u8_CTRL22 0x8E\r
-#define VID_u8_CTRL23 0x8F\r
-\r
-\r
-#define ANX7150_INTR_STATE_REG 0x40\r
-\r
-#define ANX7150_INTR_CTRL_REG 0x41\r
-\r
-#define ANX7150_INTR_CTRL_SOFT_INTR 0x04 // u8 position\r
-#define ANX7150_INTR_CTRL_TYPE 0x02 // u8 position\r
-#define ANX7150_INTR_CTRL_POL 0x01 // u8 position\r
-\r
-#define ANX7150_INTR1_STATUS_REG 0x42\r
-#define ANX7150_INTR1_STATUS_CTS_CHG 0x80 // u8 position\r
-#define ANX7150_INTR1_STATUS_AFIFO_UNDER 0x40 // u8 position\r
-#define ANX7150_INTR1_STATUS_AFIFO_OVER 0x20 // u8 position\r
-#define ANX7150_INTR1_STATUS_SPDIF_ERR 0x10 // u8 position\r
-#define ANX7150_INTR1_STATUS_SW_INT 0x08 // u8 position\r
-#define ANX7150_INTR1_STATUS_HP_CHG 0x04 // u8 position\r
-#define ANX7150_INTR1_STATUS_CTS_OVRWR 0x02 // u8 position\r
-#define ANX7150_INTR1_STATUS_CLK_CHG 0x01 // u8 position\r
-\r
-#define ANX7150_INTR2_STATUS_REG 0x43\r
-#define ANX7150_INTR2_STATUS_ENCEN_CHG 0x80 // u8 position\r
-#define ANX7150_INTR2_STATUS_HDCPLINK_CHK 0x40 // u8 position\r
-#define ANX7150_INTR2_STATUS_HDCPENHC_CHK 0x20 // u8 position\r
-#define ANX7150_INTR2_STATUS_BKSV_RDY 0x10 // u8 position\r
-#define ANX7150_INTR2_STATUS_PLLLOCK_CHG 0x08 // u8 position\r
-#define ANX7150_INTR2_STATUS_SHA_DONE 0x04 // u8 position\r
-#define ANX7150_INTR2_STATUS_AUTH_CHG 0x02 // u8 position\r
-#define ANX7150_INTR2_STATUS_AUTH_DONE 0x01 // u8 position\r
-\r
-#define ANX7150_INTR3_STATUS_REG 0x44\r
-#define ANX7150_INTR3_STATUS_SPDIFBI_ERR 0x80 // u8 position\r
-#define ANX7150_INTR3_STATUS_VIDF_CHG 0x40 // u8 position\r
-#define ANX7150_INTR3_STATUS_AUDCLK_CHG 0x20 // u8 position\r
-#define ANX7150_INTR3_STATUS_DDCACC_ERR 0x10 // u8 position\r
-#define ANX7150_INTR3_STATUS_DDC_NOACK 0x08 // u8 position\r
-#define ANX7150_INTR3_STATUS_VSYNC_DET 0x04 // u8 position\r
-#define ANX7150_INTR3_STATUS_RXSEN_CHG 0x02 // u8 position\r
-#define ANX7150_INTR3_STATUS_SPDIF_UNSTBL 0x01 // u8 position\r
-\r
-#define ANX7150_INTR1_MASK_REG 0x45\r
-#define ANX7150_INTR2_MASK_REG 0x46\r
-#define ANX7150_INTR3_MASK_REG 0x47\r
-\r
-#define ANX7150_HDMI_AUDCTRL0_REG 0x50\r
-#define ANX7150_HDMI_AUDCTRL0_LAYOUT 0x80 // u8 position\r
-#define ANX7150_HDMI_AUDCTRL0_DOWN_SMPL 0x60 // u8 position\r
-#define ANX7150_HDMI_AUDCTRL0_CTSGEN_SC 0x10 // u8 position\r
-#define ANX7150_HDMI_AUDCTRL0_INV_AUDCLK 0x08 // u8 position\r
-\r
-#define ANX7150_HDMI_AUDCTRL1_REG 0x51\r
-#define ANX7150_HDMI_AUDCTRL1_IN_EN 0x80 // u8 position\r
-#define ANX7150_HDMI_AUDCTRL1_SPDIFIN_EN 0x40 // u8 position\r
-#define ANX7150_HDMI_AUDCTRL1_SD3IN_EN 0x20 // u8 position\r
-#define ANX7150_HDMI_AUDCTRL1_SD2IN_EN 0x10 // u8 position\r
-#define ANX7150_HDMI_AUDCTRL1_SD1IN_EN 0x08 // u8 position\r
-#define ANX7150_HDMI_AUDCTRL1_SD0IN_EN 0x04 // u8 position\r
-#define ANX7150_HDMI_AUDCTRL1_SPDIFFS_OVRWR 0x02 // u8 position\r
-#define ANX7150_HDMI_AUDCTRL1_CLK_SEL 0x01 // u8 position\r
-\r
-#define ANX7150_I2S_CTRL_REG 0x52\r
-#define ANX7150_I2S_CTRL_VUCP 0x80 // u8 position\r
-#define SPDIF_IN_SEL 0x10 //0-spdif, 1-multi with sd0\r
-#define ANX7150_I2S_CTRL_SHIFT_CTRL 0x08 // u8 position\r
-#define ANX7150_I2S_CTRL_DIR_CTRL 0x04 // u8 position\r
-#define ANX7150_I2S_CTRL_WS_POL 0x02 // u8 position\r
-#define ANX7150_I2S_CTRL_JUST_CTRL 0x01 // u8 position\r
-\r
-#define ANX7150_I2SCH_CTRL_REG 0x53\r
-#define ANX7150_I2SCH_FIFO3_SEL 0xC0 // u8 position\r
-#define ANX7150_I2SCH_FIFO2_SEL 0x30 // u8 position\r
-#define ANX7150_I2SCH_FIFO1_SEL 0x0C // u8 position\r
-#define ANX7150_I2SCH_FIFO0_SEL 0x03 // u8 position\r
-\r
-#define ANX7150_I2SCH_SWCTRL_REG 0x54\r
-\r
-#define ANX7150_I2SCH_SWCTRL_SW3 0x80 // u8 position\r
-#define ANX7150_I2SCH_SWCTRL_SW2 0x40 // u8 position\r
-#define ANX7150_I2SCH_SWCTRL_SW1 0x20 // u8 position\r
-#define ANX7150_I2SCH_SWCTRL_SW0 0x10 // u8 position\r
-#define ANX7150_I2SCH_SWCTRL_INWD_LEN 0xE0 // u8 position\r
-#define ANX7150_I2SCH_SWCTRL_INWD_MAX 0x01 // u8 position\r
-\r
-#define ANX7150_SPDIFCH_STATUS_REG 0x55\r
-#define ANX7150_SPDIFCH_STATUS_FS_FREG 0xF0 // u8 position\r
-#define ANX7150_SPDIFCH_STATUS_WD_LEN 0x0E // u8 position\r
-#define ANX7150_SPDIFCH_STATUS_WD_MX 0x01 // u8 position\r
-\r
-#define ANX7150_I2SCH_STATUS1_REG 0x56\r
-#define ANX7150_I2SCH_STATUS1_MODE 0xC0 // u8 position\r
-#define ANX7150_I2SCH_STATUS1_PCM_MODE 0x38 // u8 position\r
-#define ANX7150_I2SCH_STATUS1_SW_CPRGT 0x04 // u8 position\r
-#define ANX7150_I2SCH_STATUS1_NON_PCM 0x02 // u8 position\r
-#define ANX7150_I2SCH_STATUS1_PROF_APP 0x01 // u8 position\r
-\r
-#define ANX7150_I2SCH_STATUS2_REG 0x57\r
-\r
-#define ANX7150_I2SCH_STATUS3_REG 0x58\r
-#define ANX7150_I2SCH_STATUS3_CH_NUM 0xF0 // u8 position\r
-#define ANX7150_I2SCH_STATUS3_SRC_NUM 0x0F // u8 position\r
-\r
-\r
-\r
-#define ANX7150_I2SCH_STATUS4_REG 0x59\r
-\r
-#define ANX7150_I2SCH_STATUS5_REG 0x5A\r
-\r
-#define ANX7150_I2SCH_STATUS5_WORD_MAX 0x01 // u8 position\r
-\r
-#define ANX7150_HDMI_AUDSTATUS_REG 0x5B\r
-\r
-#define ANX7150_HDMI_AUDSTATUS_SPDIF_DET 0x01 // u8 position\r
-\r
-#define ANX7150_HDMI_AUDBIST_CTRL_REG 0x5C\r
-\r
-#define ANX7150_HDMI_AUDBIST_EN3 0x08 // u8 position\r
-#define ANX7150_HDMI_AUDBIST_EN2 0x04 // u8 position\r
-#define ANX7150_HDMI_AUDBIST_EN1 0x02 // u8 position\r
-#define ANX7150_HDMI_AUDBIST_EN0 0x01 // u8 position\r
-\r
-#define ANX7150_AUD_INCLK_CNT_REG 0x5D\r
-#define ANX7150_AUD_DEBUG_STATUS_REG 0x5E\r
-\r
-#define ANX7150_ONEu8_AUD_CTRL_REG 0x60\r
-\r
-#define ANX7150_ONEu8_AUD_CTRL_SEN7 0x80 // u8 position\r
-#define ANX7150_ONEu8_AUD_CTRL_SEN6 0x40 // u8 position\r
-#define ANX7150_ONEu8_AUD_CTRL_SEN5 0x20 // u8 position\r
-#define ANX7150_ONEu8_AUD_CTRL_SEN4 0x10 // u8 position\r
-#define ANX7150_ONEu8_AUD_CTRL_SEN3 0x08 // u8 position\r
-#define ANX7150_ONEu8_AUD_CTRL_SEN2 0x04 // u8 position\r
-#define ANX7150_ONEu8_AUD_CTRL_SEN1 0x02 // u8 position\r
-#define ANX7150_ONEu8_AUD_CTRL_SEN0 0x01 // u8 position\r
-\r
-#define ANX7150_ONEu8_AUD0_CTRL_REG 0x61\r
-#define ANX7150_ONEu8_AUD1_CTRL_REG 0x62\r
-#define ANX7150_ONEu8_AUD2_CTRL_REG 0x63\r
-#define ANX7150_ONEu8_AUD3_CTRL_REG 0x64\r
-\r
-#define ANX7150_ONEu8_AUDCLK_CTRL_REG 0x65\r
-\r
-#define ANX7150_ONEu8_AUDCLK_DET 0x08 // u8 position\r
-\r
-#define ANX7150_SPDIF_ERR_THRSHLD_REG 0x66\r
-#define ANX7150_SPDIF_ERR_CNT_REG 0x67\r
-\r
-#define ANX7150_HDMI_LINK_CTRL_REG 0x70\r
-\r
-#define ANX7150_HDMI_LINK_DATA_MUTEEN1 0x80 // u8 position\r
-#define ANX7150_HDMI_LINK_DATA_MUTEEN0 0x40 // u8 position\r
-#define ANX7150_HDMI_LINK_CLK_MUTEEN2 0x20 // u8 position\r
-#define ANX7150_HDMI_LINK_CLK_MUTEEN1 0x10 // u8 position\r
-#define ANX7150_HDMI_LINK_CLK_MUTEEN0 0x08 // u8 position\r
-#define ANX7150_HDMI_LINK_DEC_DE 0x04 // u8 position\r
-#define ANX7150_HDMI_LINK_PRMB_INC 0x02 // u8 position\r
-#define ANX7150_HDMI_LINK_AUTO_PROG 0x01 // u8 position\r
-\r
-#define ANX7150_VID_CAPCTRL2_REG 0x71\r
-\r
-#define ANX7150_VID_CAPCTRL2_CHK_UPDATEEN 0x10 // u8 position\r
-\r
-#define ANX7150_LINK_MUTEEE_REG 0x72\r
-\r
-#define ANX7150_LINK_MUTEEE_AVMUTE_EN2 0x20 // u8 position\r
-#define ANX7150_LINK_MUTEEE_AVMUTE_EN1 0x10 // u8 position\r
-#define ANX7150_LINK_MUTEEE_AVMUTE_EN0 0x08 // u8 position\r
-#define ANX7150_LINK_MUTEEE_AUDMUTE_EN2 0x04 // u8 position\r
-#define ANX7150_LINK_MUTEEE_AUDMUTE_EN1 0x02 // u8 position\r
-#define ANX7150_LINK_MUTEEE_AUDMUTE_EN0 0x01 // u8 position\r
-\r
-#define ANX7150_SERDES_TEST0_REG 0x73\r
-#define ANX7150_SERDES_TEST1_REG 0x74\r
-#define ANX7150_SERDES_TEST2_REG 0x75\r
-\r
-#define ANX7150_PLL_TX_AMP 0x76\r
-\r
-\r
-#define ANX7150_DDC_SLV_ADDR_REG 0x80\r
-#define ANX7150_DDC_SLV_SEGADDR_REG 0x81\r
-#define ANX7150_DDC_SLV_OFFADDR_REG 0x82\r
-#define ANX7150_DDC_ACC_CMD_REG 0x83\r
-#define ANX7150_DDC_ACCNUM0_REG 0x84\r
-#define ANX7150_DDC_ACCNUM1_REG 0x85\r
-\r
-#define ANX7150_DDC_CHSTATUS_REG 0x86\r
-\r
-#define ANX7150_DDC_CHSTATUS_DDCERR 0x80 // u8 position\r
-#define ANX7150_DDC_CHSTATUS_DDC_OCCUPY 0x40 // u8 position\r
-#define ANX7150_DDC_CHSTATUS_FIFO_FULL 0x20 // u8 position\r
-#define ANX7150_DDC_CHSTATUS_FIFO_EMPT 0x10 // u8 position\r
-#define ANX7150_DDC_CHSTATUS_NOACK 0x08 // u8 position\r
-#define ANX7150_DDC_CHSTATUS_FIFO_RD 0x04 // u8 position\r
-#define ANX7150_DDC_CHSTATUS_FIFO_WR 0x02 // u8 position\r
-#define ANX7150_DDC_CHSTATUS_INPRO 0x01 // u8 position\r
-\r
-#define ANX7150_DDC_FIFO_ACC_REG 0x87\r
-#define ANX7150_DDC_FIFOCNT_REG 0x88\r
-\r
-#define ANX7150_SYS_PD_REG 0x90\r
-#define ANX7150_SYS_PD_PLL 0x80 // u8 position\r
-#define ANX7150_SYS_PD_TMDS 0x40 // u8 position\r
-#define ANX7150_SYS_PD_TMDS_CLK 0x20 // u8 position\r
-#define ANX7150_SYS_PD_MISC 0x10 // u8 position\r
-#define ANX7150_SYS_PD_LINK 0x08 // u8 position\r
-#define ANX7150_SYS_PD_IDCK 0x04 // u8 position\r
-#define ANX7150_SYS_PD_AUD 0x02 // u8 position\r
-#define ANX7150_SYS_PD_MACRO_ALL 0x01 // u8 position\r
-\r
-#define ANX7150_LINKFSM_DEBUG0_REG 0x91\r
-#define ANX7150_LINKFSM_DEBUG1_REG 0x92\r
-\r
-#define ANX7150_PLL_CTRL0_REG 0x93\r
-#define ANX7150_PLL_CTRL0_CPREG_BLEED 0x02 // u8 position\r
-#define ANX7150_PLL_CTRL0_TEST_EN 0x01 // u8 position\r
-\r
-#define ANX7150_PLL_CTRL1_REG 0x94\r
-#define ANX7150_PLL_CTRL1_TESTEN 0x80 // u8 position\r
-\r
-#define ANX7150_OSC_CTRL_REG 0x95\r
-#define ANX7150_OSC_CTRL_TESTEN 0x80 // u8 position\r
-#define ANX7150_OSC_CTRL_SEL_BG 0x40 // u8 position\r
-\r
-#define ANX7150_TMDS_CH0_CONFIG_REG 0x96\r
-#define ANX7150_TMDS_CH0_TESTEN 0x20 // u8 position\r
-#define ANX7150_TMDS_CH0_AMP 0x1C // u8 position\r
-#define ANX7150_TMDS_CHO_EMP 0x03 // u8 position\r
-\r
-#define ANX7150_TMDS_CH1_CONFIG_REG 0x97\r
-#define ANX7150_TMDS_CH1_TESTEN 0x20 // u8 position\r
-#define ANX7150_TMDS_CH1_AMP 0x1C // u8 position\r
-#define ANX7150_TMDS_CH1_EMP 0x03 // u8 position\r
-\r
-#define ANX7150_TMDS_CH2_CONFIG_REG 0x98\r
-#define ANX7150_TMDS_CH2_TESTEN 0x20 // u8 position\r
-#define ANX7150_TMDS_CH2_AMP 0x1C // u8 position\r
-#define ANX7150_TMDS_CH2_EMP 0x03 // u8 position\r
-\r
-#define ANX7150_TMDS_CLKCH_CONFIG_REG 0x99\r
-#define ANX7150_TMDS_CLKCH_MUTE 0x80 // u8 position\r
-#define ANX7150_TMDS_CLKCH_TESTEN 0x08 // u8 position\r
-#define ANX7150_TMDS_CLKCH_AMP 0x07 // u8 position\r
-\r
-#define ANX7150_CHIP_CTRL_REG 0x9A\r
-#define ANX7150_CHIP_CTRL_PRBS_GENEN 0x80 // u8 position\r
-#define ANX7150_CHIP_CTRL_LINK_DBGSEL 0x70 // u8 position\r
-#define ANX7150_CHIP_CTRL_VIDCHK_EN 0x08 // u8 position\r
-#define ANX7150_CHIP_CTRL_MISC_TIMER 0x04 // u8 position\r
-#define ANX7150_CHIP_CTRL_PLL_RNG 0x02 // u8 position\r
-#define ANX7150_CHIP_CTRL_PLL_MAN 0x01 // u8 position\r
-\r
-#define ANX7150_CHIP_STATUS_REG 0x9B\r
-#define ANX7150_CHIP_STATUS_GPIO 0x80 // u8 position\r
-#define ANX7150_CHIP_STATUS_SDA 0x40 // u8 position\r
-#define ANX7150_CHIP_STATUS_SCL 0x20 // u8 position\r
-#define ANX7150_CHIP_STATUS_PLL_HSPO 0x04 // u8 position\r
-#define ANX7150_CHIP_STATUS_PLL_LOCK 0x02 // u8 position\r
-#define ANX7150_CHIP_STATUS_MISC_LOCK 0x01 // u8 position\r
-\r
-#define ANX7150_DBG_PINGPIO_CTRL_REG 0x9C\r
-#define ANX7150_DBG_PINGPIO_VDLOW_SHAREDEN 0x04 // u8 position\r
-#define ANX7150_DBG_PINGPIO_GPIO_ADDREN 0x02 // u8 position\r
-#define ANX7150_DBG_PINGPIO_GPIO_OUT 0x01 // u8 position\r
-\r
-#define ANX7150_CHIP_DEBUG0_CTRL_REG 0x9D\r
-#define ANX7150_CHIP_DEBUG0_PRBS_ERR 0xE0 // u8 position\r
-#define ANX7150_CHIP_DEBUG0_CAPST 0x1F // u8 position\r
-\r
-#define ANX7150_CHIP_DEBUG1_CTRL_REG 0x9E\r
-#define ANX7150_CHIP_DEBUG1_SDA_SW 0x80 // u8 position\r
-#define ANX7150_CHIP_DEBUG1_SCL_SW 0x40 // u8 position\r
-#define ANX7150_CHIP_DEBUG1_SERDES_TESTEN 0x20 // u8 position\r
-#define ANX7150_CHIP_DEBUG1_CLK_BYPASS 0x10 // u8 position\r
-#define ANX7150_CHIP_DEBUG1_FORCE_PLLLOCK 0x08 // u8 position\r
-#define ANX7150_CHIP_DEBUG1_PLLLOCK_BYPASS 0x04 // u8 position\r
-#define ANX7150_CHIP_DEBUG1_FORCE_HP 0x02 // u8 position\r
-#define ANX7150_CHIP_DEBUG1_HP_DEGLITCH 0x01 // u8 position\r
-\r
-#define ANX7150_CHIP_DEBUG2_CTRL_REG 0x9F\r
-#define ANX7150_CHIP_DEBUG2_EXEMB_SYNCEN 0x04 // u8 position\r
-#define ANX7150_CHIP_DEBUG2_VIDBIST 0x02 // u8 position\r
-\r
-#define ANX7150_VID_INCLK_REG 0x5F\r
-\r
-#define ANX7150_HDCP_STATUS_REG 0xA0\r
-#define ANX7150_HDCP_STATUS_ADV_CIPHER 0x80 // u8 position\r
-#define ANX7150_HDCP_STATUS_R0_READY 0x10 // u8 position\r
-#define ANX7150_HDCP_STATUS_AKSV_ACT 0x08 // u8 position\r
-#define ANX7150_HDCP_STATUS_ENCRYPT 0x04 // u8 position\r
-#define ANX7150_HDCP_STATUS_AUTH_PASS 0x02 // u8 position\r
-#define ANX7150_HDCP_STATUS_KEY_DONE 0x01 // u8 position\r
-\r
-#define ANX7150_HDCP_CTRL0_REG 0xA1\r
-#define ANX7150_HDCP_CTRL0_STORE_AN 0x80 // u8 position\r
-#define ANX7150_HDCP_CTRL0_RX_REP 0x40 // u8 position\r
-#define ANX7150_HDCP_CTRL0_RE_AUTH 0x20 // u8 position\r
-#define ANX7150_HDCP_CTRL0_SW_AUTHOK 0x10 // u8 position\r
-#define ANX7150_HDCP_CTRL0_HW_AUTHEN 0x08 // u8 position\r
-#define ANX7150_HDCP_CTRL0_ENC_EN 0x04 // u8 position\r
-#define ANX7150_HDCP_CTRL0_BKSV_SRM 0x02 // u8 position\r
-#define ANX7150_HDCP_CTRL0_KSV_VLD 0x01 // u8 position\r
-\r
-#define ANX7150_HDCP_CTRL1_REG 0xA2\r
-#define ANX7150_LINK_CHK_12_EN 0x40\r
-#define ANX7150_HDCP_CTRL1_DDC_NOSTOP 0x20 // u8 position\r
-#define ANX7150_HDCP_CTRL1_DDC_NOACK 0x10 // u8 position\r
-#define ANX7150_HDCP_CTRL1_EDDC_NOACK 0x08 // u8 position\r
-#define ANX7150_HDCP_CTRL1_BLUE_SCREEN_EN 0x04 // u8 position\r
-#define ANX7150_HDCP_CTRL1_RCV11_EN 0x02 // u8 position\r
-#define ANX7150_HDCP_CTRL1_HDCP11_EN 0x01 // u8 position\r
-\r
-#define ANX7150_HDCP_Link_Check_FRAME_NUM_REG 0xA3\r
-#define ANX7150_HDCP_AKSV1_REG 0xA5\r
-#define ANX7150_HDCP_AKSV2_REG 0xA6\r
-#define ANX7150_HDCP_AKSV3_REG 0xA7\r
-#define ANX7150_HDCP_AKSV4_REG 0xA8\r
-#define ANX7150_HDCP_AKSV5_REG 0xA9\r
-\r
-#define ANX7150_HDCP_AN1_REG 0xAA\r
-#define ANX7150_HDCP_AN2_REG 0xAB\r
-#define ANX7150_HDCP_AN3_REG 0xAC\r
-#define ANX7150_HDCP_AN4_REG 0xAD\r
-#define ANX7150_HDCP_AN5_REG 0xAE\r
-#define ANX7150_HDCP_AN6_REG 0xAF\r
-#define ANX7150_HDCP_AN7_REG 0xB0\r
-#define ANX7150_HDCP_AN8_REG 0xB1\r
-\r
-#define ANX7150_HDCP_BKSV1_REG 0xB2\r
-#define ANX7150_HDCP_BKSV2_REG 0xB3\r
-#define ANX7150_HDCP_BKSV3_REG 0xB4\r
-#define ANX7150_HDCP_BKSV4_REG 0xB5\r
-#define ANX7150_HDCP_BKSV5_REG 0xB6\r
-\r
-#define ANX7150_HDCP_RI1_REG 0xB7\r
-#define ANX7150_HDCP_RI2_REG 0xB8\r
-\r
-#define ANX7150_HDCP_PJ_REG 0xB9\r
-#define ANX7150_HDCP_RX_CAPS_REG 0xBA\r
-#define ANX7150_HDCP_BSTATUS0_REG 0xBB\r
-#define ANX7150_HDCP_BSTATUS1_REG 0xBC\r
-\r
-#define ANX7150_HDCP_AMO0_REG 0xD0\r
-#define ANX7150_HDCP_AMO1_REG 0xD1\r
-#define ANX7150_HDCP_AMO2_REG 0xD2\r
-#define ANX7150_HDCP_AMO3_REG 0xD3\r
-#define ANX7150_HDCP_AMO4_REG 0xD4\r
-#define ANX7150_HDCP_AMO5_REG 0xD5\r
-#define ANX7150_HDCP_AMO6_REG 0xD6\r
-#define ANX7150_HDCP_AMO7_REG 0xD7\r
-\r
-#define ANX7150_HDCP_DBG_CTRL_REG 0xBD\r
-\r
-#define ANX7150_HDCP_DBG_ENC_INC 0x08 // u8 position\r
-#define ANX7150_HDCP_DBG_DDC_SPEED 0x06 // u8 position\r
-#define ANX7150_HDCP_DBG_SKIP_RPT 0x01 // u8 position\r
-\r
-#define ANX7150_HDCP_KEY_STATUS_REG 0xBE\r
-#define ANX7150_HDCP_KEY_BIST_EN 0x04 // u8 position\r
-#define ANX7150_HDCP_KEY_BIST_ERR 0x02 // u8 position\r
-#define ANX7150_HDCP_KEY_CMD_DONE 0x01 // u8 position\r
-\r
-#define ANX7150_KEY_CMD_REGISTER 0xBF //added\r
-\r
-#define ANX7150_HDCP_AUTHDBG_STATUS_REG 0xC7\r
-#define ANX7150_HDCP_ENCRYPTDBG_STATUS_REG 0xC8\r
-#define ANX7150_HDCP_FRAME_NUM_REG 0xC9\r
-\r
-#define ANX7150_DDC_MSTR_INTER_REG 0xCA\r
-#define ANX7150_DDC_MSTR_LINK_REG 0xCB\r
-\r
-#define ANX7150_HDCP_BLUESCREEN0_REG 0xCC\r
-#define ANX7150_HDCP_BLUESCREEN1_REG 0xCD\r
-#define ANX7150_HDCP_BLUESCREEN2_REG 0xCE\r
-// DEV_ADDR = 0x7A or 0x7E\r
-#define ANX7150_INFO_PKTCTRL1_REG 0xC0\r
-#define ANX7150_INFO_PKTCTRL1_SPD_RPT 0x80 // u8 position\r
-#define ANX7150_INFO_PKTCTRL1_SPD_EN 0x40 // u8 position\r
-#define ANX7150_INFO_PKTCTRL1_AVI_RPT 0x20 // u8 position\r
-#define ANX7150_INFO_PKTCTRL1_AVI_EN 0x10 // u8 position\r
-#define ANX7150_INFO_PKTCTRL1_GCP_RPT 0x08 // u8 position\r
-#define ANX7150_INFO_PKTCTRL1_GCP_EN 0x04 // u8 position\r
-#define ANX7150_INFO_PKTCTRL1_ACR_NEW 0x02 // u8 position\r
-#define ANX7150_INFO_PKTCTRL1_ACR_EN 0x01 // u8 position\r
-\r
-#define ANX7150_INFO_PKTCTRL2_REG 0xC1\r
-#define ANX7150_INFO_PKTCTRL2_UD1_RPT 0x80 // u8 position\r
-#define ANX7150_INFO_PKTCTRL2_UD1_EN 0x40 // u8 position\r
-#define ANX7150_INFO_PKTCTRL2_UD0_RPT 0x20 // u8 position\r
-#define ANX7150_INFO_PKTCTRL2_UD0_EN 0x10 // u8 position\r
-#define ANX7150_INFO_PKTCTRL2_MPEG_RPT 0x08 // u8 position\r
-#define ANX7150_INFO_PKTCTRL2_MPEG_EN 0x04 // u8 position\r
-#define ANX7150_INFO_PKTCTRL2_AIF_RPT 0x02 // u8 position\r
-#define ANX7150_INFO_PKTCTRL2_AIF_EN 0x01 // u8 position\r
-\r
-#define ANX7150_ACR_N1_SW_REG 0xC2\r
-#define ANX7150_ACR_N2_SW_REG 0xC3\r
-#define ANX7150_ACR_N3_SW_REG 0xC4\r
-\r
-#define ANX7150_ACR_CTS1_SW_REG 0xC5\r
-#define ANX7150_ACR_CTS2_SW_REG 0xC6\r
-#define ANX7150_ACR_CTS3_SW_REG 0xC7\r
-\r
-#define ANX7150_ACR_CTS1_HW_REG 0xC8\r
-#define ANX7150_ACR_CTS2_HW_REG 0xC9\r
-#define ANX7150_ACR_CTS3_HW_REG 0xCA\r
-\r
-#define ANX7150_ACR_CTS_CTRL_REG 0xCB\r
-\r
-#define ANX7150_GNRL_CTRL_PKT_REG 0xCC\r
-#define ANX7150_GNRL_CTRL_CLR_AVMUTE 0x02 // u8 position\r
-#define ANX7150_GNRL_CTRL_SET_AVMUTE 0x01 // u8 position\r
-\r
-#define ANX7150_AUD_PKT_FLATCTRL_REG 0xCD\r
-#define ANX7150_AUD_PKT_AUTOFLAT_EN 0x80 // u8 position\r
-#define ANX7150_AUD_PKT_FLAT 0x07 // u8 position\r
-\r
-\r
-//select video hardware interface\r
-#define ANX7150_VID_HW_INTERFACE 0x03//0x00:RGB and YcbCr 4:4:4 Formats with Separate Syncs (24-bpp mode)\r
- //0x01:YCbCr 4:2:2 Formats with Separate Syncs(16-bbp)\r
- //0x02:YCbCr 4:2:2 Formats with Embedded Syncs(No HS/VS/DE)\r
- //0x03:YC Mux 4:2:2 Formats with Separate Sync Mode1(u815:8 and u8 3:0 are used)\r
- //0x04:YC Mux 4:2:2 Formats with Separate Sync Mode2(u811:0 are used)\r
- //0x05:YC Mux 4:2:2 Formats with Embedded Sync Mode1(u815:8 and u8 3:0 are used)\r
- //0x06:YC Mux 4:2:2 Formats with Embedded Sync Mode2(u811:0 are used)\r
- //0x07:RGB and YcbCr 4:4:4 DDR Formats with Separate Syncs\r
- //0x08:RGB and YcbCr 4:4:4 DDR Formats with Embedded Syncs\r
- //0x09:RGB and YcbCr 4:4:4 Formats with Separate Syncs but no DE\r
- //0x0a:YCbCr 4:2:2 Formats with Separate Syncs but no DE\r
-//select input color space\r
-#define ANX7150_INPUT_COLORSPACE 0x01//0x00: input color space is RGB\r
- //0x01: input color space is YCbCr422\r
- //0x02: input color space is YCbCr444\r
-//select input pixel clock edge for DDR mode\r
-#define ANX7150_IDCK_EDGE_DDR 0x00 //0x00:use rising edge to latch even numbered pixel data//jack wen\r
- //0x01:use falling edge to latch even numbered pixel data\r
-\r
-//select audio hardware interface\r
-#define ANX7150_AUD_HW_INTERFACE 0x01//0x01:audio input comes from I2S\r
- //0x02:audio input comes from SPDIF\r
- //0x04:audio input comes from one u8 audio\r
-//select MCLK and Fs relationship if audio HW interface is I2S\r
-#define ANX7150_MCLK_Fs_RELATION 0x01//0x00:MCLK = 128 * Fs\r
- //0x01:MCLK = 256 * Fs\r
- //0x02:MCLK = 384 * Fs\r
- //0x03:MCLK = 512 * Fs //wen updated error\r
-\r
-#define ANX7150_AUD_CLK_EDGE 0x00 //0x00:use MCLK and SCK rising edge to latch audio data\r
- //0x08, revised by wen. //0x80:use MCLK and SCK falling edge to latch audio data\r
-//select I2S channel numbers if audio HW interface is I2S\r
-#define ANX7150_I2S_CH0_ENABLE 0x01 //0x01:enable channel 0 input; 0x00: disable\r
-#define ANX7150_I2S_CH1_ENABLE 0x00 //0x01:enable channel 0 input; 0x00: disable\r
-#define ANX7150_I2S_CH2_ENABLE 0x00 //0x01:enable channel 0 input; 0x00: disable\r
-#define ANX7150_I2S_CH3_ENABLE 0x00 //0x01:enable channel 0 input; 0x00: disable\r
-//select I2S word length if audio HW interface is I2S\r
-#define ANX7150_I2S_WORD_LENGTH 0x0b\r
- //0x02 = 16u8s; 0x04 = 18 u8s; 0x08 = 19 u8s; 0x0a = 20 u8s(maximal word length is 20u8s); 0x0c = 17 u8s;\r
- // 0x03 = 20u8s(maximal word length is 24u8s); 0x05 = 22 u8s; 0x09 = 23 u8s; 0x0b = 24 u8s; 0x0d = 21 u8s;\r
-\r
-//select I2S format if audio HW interface is I2S\r
-#define ANX7150_I2S_SHIFT_CTRL 0x00//0x00: fist u8 shift(philips spec)\r
- //0x01:no shift\r
-#define ANX7150_I2S_DIR_CTRL 0x00//0x00:SD data MSB first\r
- //0x01:LSB first\r
-#define ANX7150_I2S_WS_POL 0x00//0x00:left polarity when word select is low\r
- //0x01:left polarity when word select is high\r
-#define ANX7150_I2S_JUST_CTRL 0x00//0x00:data is left justified\r
- //0x01:data is right justified\r
-\r
-#define EDID_Parse_Enable 1 // cwz 0 for test, 1 normal\r
-//InfoFrame and Control Packet Registers\r
-// 0x7A or 0X7E\r
-/*\r
-#define AVI_HB0 0x00\r
-#define AVI_HB1 0x01\r
-#define AVI_HB2 0x02\r
-#define AVI_PB0 0x03\r
-#define AVI_PB1 0x04\r
-#define AVI_PB2 0x05\r
-#define AVI_PB3 0x06\r
-#define AVI_PB4 0x07\r
-#define AVI_PB5 0x08\r
-#define AVI_PB6 0x09\r
-#define AVI_PB7 0x0A\r
-#define AVI_PB8 0x0B\r
-#define AVI_PB9 0x0C\r
-#define AVI_PB10 0x0D\r
-#define AVI_PB11 0x0E\r
-#define AVI_PB12 0x0F\r
-#define AVI_PB13 0x10\r
-#define AVI_PB14 0x11\r
-#define AVI_PB15 0x12\r
-\r
-#define AUD_HBO 0x20\r
-#define AUD_HB1 0x21\r
-#define AUD_HB2 0x22\r
-#define AUD_PB0 0x23\r
-#define AUD_PB1 0x24\r
-#define AUD_PB2 0x25\r
-#define AUD_PB3 0x26\r
-#define AUD_PB4 0x27\r
-#define AUD_PB5 0x28\r
-#define AUD_PB6 0x29\r
-#define AUD_PB7 0x2A\r
-#define AUD_PB8 0x2B\r
-#define AUD_PB9 0x2C\r
-#define AUD_PB10 0x2D\r
-\r
-#define SPD_HBO 0x40\r
-#define SPD_HB1 0x41\r
-#define SPD_HB2 0x42\r
-#define SPD_PB0 0x43\r
-#define SPD_PB1 0x44\r
-#define SPD_PB2 0x45\r
-#define SPD_PB3 0x46\r
-#define SPD_PB4 0x47\r
-#define SPD_PB5 0x48\r
-#define SPD_PB6 0x49\r
-#define SPD_PB7 0x4A\r
-#define SPD_PB8 0x4B\r
-#define SPD_PB9 0x4C\r
-#define SPD_PB10 0x4D\r
-#define SPD_PB11 0x4E\r
-#define SPD_PB12 0x4F\r
-#define SPD_PB13 0x50\r
-#define SPD_PB14 0x51\r
-#define SPD_PB15 0x52\r
-#define SPD_PB16 0x53\r
-#define SPD_PB17 0x54\r
-#define SPD_PB18 0x55\r
-#define SPD_PB19 0x56\r
-#define SPD_PB20 0x57\r
-#define SPD_PB21 0x58\r
-#define SPD_PB22 0x59\r
-#define SPD_PB23 0x5A\r
-#define SPD_PB24 0x5B\r
-#define SPD_PB25 0x5C\r
-#define SPD_PB26 0x5D\r
-#define SPD_PB27 0x5E\r
-\r
-#define MPEG_HBO 0x60\r
-#define MPEG_HB1 0x61\r
-#define MPEG_HB2 0x62\r
-#define MPEG_PB0 0x63\r
-#define MPEG_PB1 0x64\r
-#define MPEG_PB2 0x65\r
-#define MPEG_PB3 0x66\r
-#define MPEG_PB4 0x67\r
-#define MPEG_PB5 0x68\r
-#define MPEG_PB6 0x69\r
-#define MPEG_PB7 0x6A\r
-#define MPEG_PB8 0x6B\r
-#define MPEG_PB9 0x6C\r
-#define MPEG_PB10 0x6D\r
-#define MPEG_PB11 0x6E\r
-#define MPEG_PB12 0x6F\r
-#define MPEG_PB13 0x70\r
-#define MPEG_PB14 0x71\r
-#define MPEG_PB15 0x72\r
-#define MPEG_PB16 0x73\r
-#define MPEG_PB17 0x74\r
-#define MPEG_PB18 0x75\r
-#define MPEG_PB19 0x76\r
-#define MPEG_PB20 0x77\r
-#define MPEG_PB21 0x78\r
-#define MPEG_PB22 0x79\r
-#define MPEG_PB23 0x7A\r
-#define MPEG_PB24 0x7B\r
-#define MPEG_PB25 0x7C\r
-#define MPEG_PB26 0x7D\r
-#define MPEG_PB27 0x7E\r
-\r
-#define USRDF0_HBO 0x80\r
-#define USRDF0_HB1 0x81\r
-#define USRDF0_HB2 0x82\r
-#define USRDF0_PB0 0x83\r
-#define USRDF0_PB1 0x84\r
-#define USRDF0_PB2 0x85\r
-#define USRDF0_PB3 0x86\r
-#define USRDF0_PB4 0x87\r
-#define USRDF0_PB5 0x88\r
-#define USRDF0_PB6 0x89\r
-#define USRDF0_PB7 0x8A\r
-#define USRDF0_PB8 0x8B\r
-#define USRDF0_PB9 0x8C\r
-#define USRDF0_PB10 0x8D\r
-#define USRDF0_PB11 0x8E\r
-#define USRDF0_PB12 0x8F\r
-#define USRDF0_PB13 0x90\r
-#define USRDF0_PB14 0x91\r
-#define USRDF0_PB15 0x92\r
-#define USRDF0_PB16 0x93\r
-#define USRDF0_PB17 0x94\r
-#define USRDF0_PB18 0x95\r
-#define USRDF0_PB19 0x96\r
-#define USRDF0_PB20 0x97\r
-#define USRDF0_PB21 0x98\r
-#define USRDF0_PB22 0x99\r
-#define USRDF0_PB23 0x9A\r
-#define USRDF0_PB24 0x9B\r
-#define USRDF0_PB25 0x9C\r
-#define USRDF0_PB26 0x9D\r
-#define USRDF0_PB27 0x9E\r
-\r
-#define USRDF1_HBO 0xA0\r
-#define USRDF1_HB1 0xA1\r
-#define USRDF1_HB2 0xA2\r
-#define USRDF1_PB0 0xA3\r
-#define USRDF1_PB1 0xA4\r
-#define USRDF1_PB2 0xA5\r
-#define USRDF1_PB3 0xA6\r
-#define USRDF1_PB4 0xA7\r
-#define USRDF1_PB5 0xA8\r
-#define USRDF1_PB6 0xA9\r
-#define USRDF1_PB7 0xAA\r
-#define USRDF1_PB8 0xAB\r
-#define USRDF1_PB9 0xAC\r
-#define USRDF1_PB10 0xAD\r
-#define USRDF1_PB11 0xAE\r
-#define USRDF1_PB12 0xAF\r
-#define USRDF1_PB13 0xB0\r
-#define USRDF1_PB14 0xB1\r
-#define USRDF1_PB15 0xB2\r
-#define USRDF1_PB16 0xB3\r
-#define USRDF1_PB17 0xB4\r
-#define USRDF1_PB18 0xB5\r
-#define USRDF1_PB19 0xB6\r
-#define USRDF1_PB20 0xB7\r
-#define USRDF1_PB21 0xB8\r
-#define USRDF1_PB22 0xB9\r
-#define USRDF1_PB23 0xBA\r
-#define USRDF1_PB24 0xBB\r
-#define USRDF1_PB25 0xBC\r
-#define USRDF1_PB26 0xBD\r
-#define USRDF1_PB27 0xBE\r
-*/\r
- int anx7150_get_hpd(struct i2c_client *client);\r
-\r
-void ANX7150_API_HDCP_ONorOFF(u8 HDCP_ONorOFF);\r
-int anx7150_detect_device(struct anx7150_pdata *anx);\r
-u8 ANX7150_Get_System_State(void);\r
-int ANX7150_Interrupt_Process(struct anx7150_pdata *anx, int cur_state);\r
-int anx7150_unplug(struct i2c_client *client);\r
-int anx7150_plug(struct i2c_client *client);\r
-int ANX7150_API_Initial(struct i2c_client *client);\r
-void ANX7150_Shutdown(struct i2c_client *client);\r
-int ANX7150_Parse_EDID(struct i2c_client *client, struct anx7150_dev_s *dev);\r
-int ANX7150_GET_SENSE_STATE(struct i2c_client *client);\r
-int ANX7150_Get_Optimal_resolution(int resolution_set);\r
-void HDMI_Set_Video_Format(u8 video_format);\r
-void HDMI_Set_Audio_Fs( u8 audio_fs);\r
-void ANX7150_API_System_Config(void);\r
-u8 ANX7150_Config_Audio(struct i2c_client *client);\r
-u8 ANX7150_Config_Packet(struct i2c_client *client);\r
-void ANX7150_HDCP_Process(struct i2c_client *client,int enable);\r
-int ANX7150_PLAYBACK_Process(void);\r
-void ANX7150_Set_System_State(struct i2c_client *client, u8 new_state);\r
-int ANX7150_Config_Video(struct i2c_client *client);\r
-int ANX7150_GET_RECIVER_TYPE(void);\r
-void HDMI_Set_Video_Format(u8 video_format);\r
-void HDMI_Set_Audio_Fs( u8 audio_fs);\r
-int ANX7150_PLAYBACK_Process(void);\r
-int ANX7150_Blue_Screen(struct anx7150_pdata *anx);\r
-int anx7150_set_avmute(struct i2c_client *client);\r
-int anx7150_initial(struct i2c_client *client);\r
-\r
-#endif\r
+++ /dev/null
-#include <linux/delay.h>\r
-#include <linux/mfd/rk610_core.h>\r
-#include "rk610_hdmi.h"\r
-#include "rk610_hdmi_hw.h"\r
-static struct rk610_hdmi_hw_inf g_hw_inf;\r
-static EDID_INF g_edid;\r
-static byte edid_buf[EDID_BLOCK_SIZE];\r
-static struct edid_result Rk610_edid_result;\r
-byte DoEdidRead (struct i2c_client *client);\r
-static int RK610_hdmi_soft_reset(struct i2c_client *client);\r
-static int Rk610_hdmi_Display_switch(struct i2c_client *client);\r
-static int Rk610_hdmi_sys_power_up(struct i2c_client *client);\r
-static int Rk610_hdmi_sys_power_down(struct i2c_client *client);\r
-\r
-static int Rk610_hdmi_i2c_read_p0_reg(struct i2c_client *client, char reg, char *val)\r
-{\r
- return i2c_master_reg8_recv(client, reg, val, 1, 100*1000) > 0? 0: -EINVAL;\r
-}\r
-static int Rk610_hdmi_i2c_write_p0_reg(struct i2c_client *client, char reg, char *val)\r
-{\r
- return i2c_master_reg8_send(client, reg, val, 1, 100*1000) > 0? 0: -EINVAL;\r
-}\r
-static int RK610_hdmi_audio_mute(struct i2c_client *client,bool enable)\r
-{\r
- char c;\r
- int ret=0;\r
- c = ((~enable)&1)<<1;\r
- ret =Rk610_hdmi_i2c_write_p0_reg(client, 0x05, &c);\r
-}\r
-static int Rk610_hdmi_pwr_mode(struct i2c_client *client, int mode)\r
-{\r
- char c;\r
- int ret=0;\r
- RK610_DBG(&client->dev,"%s \n",__FUNCTION__);\r
- switch(mode){\r
- case NORMAL:\r
- Rk610_hdmi_sys_power_down(client);\r
- c=0x82;\r
- ret =Rk610_hdmi_i2c_write_p0_reg(client, 0xe3, &c);\r
- c=0x00;\r
- ret =Rk610_hdmi_i2c_write_p0_reg(client, 0xe5, &c);\r
- c=0x00;\r
- ret =Rk610_hdmi_i2c_write_p0_reg(client, 0xe4, &c);\r
- c=0x00;\r
- ret =Rk610_hdmi_i2c_write_p0_reg(client, 0xe7, &c);\r
- c=0x8e;\r
- ret =Rk610_hdmi_i2c_write_p0_reg(client, 0xe1, &c);\r
- c=0x00;\r
- ret =Rk610_hdmi_i2c_write_p0_reg(client, 0xce, &c);\r
- c=0x01;\r
- ret =Rk610_hdmi_i2c_write_p0_reg(client, 0xce, &c);\r
- RK610_hdmi_audio_mute(client,1);\r
- Rk610_hdmi_sys_power_up(client);\r
- g_hw_inf.analog_sync = 1;\r
- break;\r
- case LOWER_PWR:\r
- RK610_hdmi_audio_mute(client,0);\r
- Rk610_hdmi_sys_power_down(client);\r
- c=0x02;\r
- ret =Rk610_hdmi_i2c_write_p0_reg(client, 0xe3, &c);\r
- c=0x1c;\r
- ret =Rk610_hdmi_i2c_write_p0_reg(client, 0xe5, &c);\r
- c=0x8c;\r
- ret =Rk610_hdmi_i2c_write_p0_reg(client, 0xe1, &c);\r
- c=0x04;\r
- ret =Rk610_hdmi_i2c_write_p0_reg(client, 0xe7, &c);\r
- c=0x03;\r
- ret =Rk610_hdmi_i2c_write_p0_reg(client, 0xe4, &c);\r
- break;\r
- default:\r
- RK610_ERR(&client->dev,"unkown rk610 hdmi pwr mode %d\n",mode);\r
- }\r
- return ret;\r
-}\r
-\r
-#ifdef CONFIG_HAS_EARLYSUSPEND\r
-int Rk610_hdmi_suspend(struct i2c_client *client)\r
-{\r
- int ret = 0;\r
- RK610_DBG(&client->dev,"%s \n",__FUNCTION__);\r
- g_hw_inf.suspend_flag = 1;\r
- g_hw_inf.hpd = 0;\r
- Rk610_hdmi_unplug(client);\r
- return ret;\r
-}\r
-int Rk610_hdmi_resume(struct i2c_client *client)\r
-{\r
- int ret = 0;\r
- char c = 0;\r
- RK610_DBG(&client->dev, "%s \n",__FUNCTION__);\r
- Rk610_hdmi_i2c_read_p0_reg(client, 0xc8, &c);\r
- if(c & RK610_HPD_PLUG ){\r
- Rk610_hdmi_plug(client);\r
- g_hw_inf.hpd=1;\r
- }\r
- else{\r
- Rk610_hdmi_unplug(client);\r
- g_hw_inf.hpd=0;\r
- }\r
- g_hw_inf.suspend_flag = 0;\r
- return ret;\r
-}\r
-#endif\r
-static int Rk610_hdmi_sys_power_up(struct i2c_client *client)\r
-{\r
- char c = 0;\r
- int ret = 0;\r
- RK610_DBG(&client->dev,"%s \n",__FUNCTION__);\r
- c= RK610_SYS_CLK<<2 |RK610_SYS_PWR_ON<<1 |RK610_INT_POL;\r
- ret =Rk610_hdmi_i2c_write_p0_reg(client, 0x00, &c);\r
- return ret;\r
-}\r
-static int Rk610_hdmi_sys_power_down(struct i2c_client *client)\r
-{\r
- char c = 0;\r
- int ret = 0;\r
- RK610_DBG(&client->dev,"%s \n",__FUNCTION__);\r
- c= RK610_SYS_CLK<<2 |RK610_SYS_PWR_OFF<<1 |RK610_INT_POL;\r
- ret =Rk610_hdmi_i2c_write_p0_reg(client, 0x00, &c);\r
- return ret;\r
-}\r
-//X=11.2896M/(4*100k), X = {0x4c,0x4b}\r
-static int RK610_DDC_BUS_CONFIG(struct i2c_client *client)\r
-{\r
- char c = 0;\r
- int ret = 0;\r
- c= RK610_DDC_CONFIG&0xff;\r
- ret =Rk610_hdmi_i2c_write_p0_reg(client, 0x4b, &c);\r
- c= (RK610_DDC_CONFIG>>8)&0xff;\r
- ret =Rk610_hdmi_i2c_write_p0_reg(client, 0x4c, &c);\r
- return ret;\r
-}\r
-static int RK610_read_edid_block(struct i2c_client *client,u8 block, u8 * buf)\r
-{\r
- char c = 0;\r
- int ret = 0,i;\r
- u8 Segment = 0;\r
- u8 Offset = 0;\r
- if(block%2)\r
- Offset = EDID_BLOCK_SIZE;\r
- if(block/2)\r
- Segment = 1;\r
- RK610_DBG(&client->dev,"EDID DATA (Segment = %d Block = %d Offset = %d):\n", (int) Segment, (int) block, (int) Offset);\r
- //set edid fifo first addr\r
- c = 0x00;\r
- ret = Rk610_hdmi_i2c_write_p0_reg(client, 0x4f, &c);\r
- //set edid word address 00/80\r
- c = Offset;\r
- ret =Rk610_hdmi_i2c_write_p0_reg(client, 0x4e, &c);\r
- //set edid segment pointer\r
- c = Segment;\r
- ret =Rk610_hdmi_i2c_write_p0_reg(client, 0x4d, &c);\r
- \r
- //enable edid interrupt\r
- c=0xc6;\r
- ret =Rk610_hdmi_i2c_write_p0_reg(client, 0xc0, &c);\r
- //wait edid interrupt\r
- msleep(10);\r
- RK610_DBG(&client->dev,"Interrupt generated\n");\r
- c=0x00;\r
- ret =Rk610_hdmi_i2c_read_p0_reg(client, 0xc1, &c);\r
- RK610_DBG(&client->dev,"Interrupt reg=%x \n",c);\r
- //clear EDID interrupt reg\r
- c=0x04;\r
- ret =Rk610_hdmi_i2c_write_p0_reg(client, 0xc1, &c);\r
- for(i=0; i <EDID_BLOCK_SIZE;i++){\r
- c = 0; \r
- Rk610_hdmi_i2c_read_p0_reg(client, 0x50, &c);\r
- buf[i] = c;\r
- }\r
- return ret;\r
-}\r
-#if 0\r
-//------------------------------------------------------------------------------\r
-// Function Name: Parse861ShortDescriptors()\r
-// Function Description: Parse CEA-861 extension short descriptors of the EDID block\r
-// passed as a parameter and save them in global structure g_edid.\r
-//\r
-// Accepts: A pointer to the EDID 861 Extension block being parsed.\r
-// Returns: EDID_PARSED_OK if EDID parsed correctly. Error code if failed.\r
-// Globals: EDID data\r
-// NOTE: Fields that are not supported by the 9022/4 (such as deep color) were not parsed.\r
-//------------------------------------------------------------------------------\r
-byte Parse861ShortDescriptors (byte *Data)\r
-{\r
- byte LongDescriptorOffset;\r
- byte DataBlockLength;\r
- byte DataIndex;\r
- byte ExtendedTagCode;\r
- byte VSDB_BaseOffset = 0;\r
-\r
- byte V_DescriptorIndex = 0; // static to support more than one extension\r
- byte A_DescriptorIndex = 0; // static to support more than one extension\r
-\r
- byte TagCode;\r
-\r
- byte i;\r
- byte j;\r
-\r
- if (Data[EDID_TAG_ADDR] != EDID_EXTENSION_TAG)\r
- {\r
- RK610_HDMI_ERR("EDID -> Extension Tag Error\n");\r
- return EDID_EXT_TAG_ERROR;\r
- }\r
-\r
- if (Data[EDID_REV_ADDR] != EDID_REV_THREE)\r
- {\r
- RK610_HDMI_ERR("EDID -> Revision Error\n"));\r
- return EDID_REV_ADDR_ERROR;\r
- }\r
-\r
- LongDescriptorOffset = Data[LONG_DESCR_PTR_IDX]; // block offset where long descriptors start\r
-\r
- g_edid.UnderScan = ((Data[MISC_SUPPORT_IDX]) >> 7) & LSBIT; // byte #3 of CEA extension version 3\r
- g_edid.BasicAudio = ((Data[MISC_SUPPORT_IDX]) >> 6) & LSBIT;\r
- g_edid.YCbCr_4_4_4 = ((Data[MISC_SUPPORT_IDX]) >> 5) & LSBIT;\r
- g_edid.YCbCr_4_2_2 = ((Data[MISC_SUPPORT_IDX]) >> 4) & LSBIT;\r
-\r
- DataIndex = EDID_DATA_START; // 4\r
-\r
- while (DataIndex < LongDescriptorOffset)\r
- {\r
- TagCode = (Data[DataIndex] >> 5) & THREE_LSBITS;\r
- DataBlockLength = Data[DataIndex++] & FIVE_LSBITS;\r
- if ((DataIndex + DataBlockLength) > LongDescriptorOffset)\r
- {\r
- RK610_HDMI_ERR("EDID -> V Descriptor Overflow\n");\r
- return EDID_V_DESCR_OVERFLOW;\r
- }\r
-\r
- i = 0; // num of short video descriptors in current data block\r
-\r
- switch (TagCode)\r
- {\r
- case VIDEO_D_BLOCK:\r
- while ((i < DataBlockLength) && (i < MAX_V_DESCRIPTORS)) // each SVD is 1 byte long\r
- {\r
- g_edid.VideoDescriptor[V_DescriptorIndex++] = Data[DataIndex++];\r
- i++;\r
- }\r
- DataIndex += DataBlockLength - i; // if there are more STDs than MAX_V_DESCRIPTORS, skip the last ones. Update DataIndex\r
-\r
- RK610_RK610_DBG(&client->dev,"EDID -> Short Descriptor Video Block\n");\r
- break;\r
-\r
- case AUDIO_D_BLOCK:\r
- while (i < DataBlockLength/3) // each SAD is 3 bytes long\r
- {\r
- j = 0;\r
- while (j < AUDIO_DESCR_SIZE) // 3\r
- {\r
- g_edid.AudioDescriptor[A_DescriptorIndex][j++] = Data[DataIndex++];\r
- }\r
- A_DescriptorIndex++;\r
- i++;\r
- }\r
- RK610_HDMI_DBG("EDID -> Short Descriptor Audio Block\n");\r
- break;\r
-\r
- case SPKR_ALLOC_D_BLOCK:\r
- g_edid.SpkrAlloc[i++] = Data[DataIndex++]; // although 3 bytes are assigned to Speaker Allocation, only\r
- DataIndex += 2; // the first one carries information, so the next two are ignored by this code.\r
- RK610_HDMI_DBG("EDID -> Short Descriptor Speaker Allocation Block\n");\r
- break;\r
-\r
- case USE_EXTENDED_TAG:\r
- ExtendedTagCode = Data[DataIndex++];\r
-\r
- switch (ExtendedTagCode)\r
- {\r
- case VIDEO_CAPABILITY_D_BLOCK:\r
- RK610_HDMI_DBG("EDID -> Short Descriptor Video Capability Block\n");\r
-\r
- // TO BE ADDED HERE: Save "video capability" parameters in g_edid data structure\r
- // Need to modify that structure definition\r
- // In the meantime: just increment DataIndex by 1\r
- DataIndex += 1; // replace with reading and saving the proper data per CEA-861 sec. 7.5.6 while incrementing DataIndex\r
- break;\r
-\r
- case COLORIMETRY_D_BLOCK:\r
- g_edid.ColorimetrySupportFlags = Data[DataIndex++] & BITS_1_0;\r
- g_edid.MetadataProfile = Data[DataIndex++] & BITS_2_1_0;\r
-\r
- RK610_HDMI_DBG("EDID -> Short Descriptor Colorimetry Block\n");\r
- break;\r
- }\r
- break;\r
-\r
- case VENDOR_SPEC_D_BLOCK:\r
- VSDB_BaseOffset = DataIndex - 1;\r
-\r
- if ((Data[DataIndex++] == 0x03) && // check if sink is HDMI compatible\r
- (Data[DataIndex++] == 0x0C) &&\r
- (Data[DataIndex++] == 0x00))\r
-\r
- g_edid.RK610_HDMI_Sink = TRUE;\r
- else\r
- g_edid.RK610_HDMI_Sink = FALSE;\r
-\r
- g_edid.CEC_A_B = Data[DataIndex++]; // CEC Physical address\r
- g_edid.CEC_C_D = Data[DataIndex++];\r
-\r
-#ifdef DEV_SUPPORT_CEC\r
- // Take the Address that was passed in the EDID and use this API\r
- // to set the physical address for CEC.\r
- {\r
- word phyAddr;\r
- phyAddr = (word)g_edid.CEC_C_D; // Low-order nibbles\r
- phyAddr |= ((word)g_edid.CEC_A_B << 8); // Hi-order nibbles\r
- // Is the new PA different from the current PA?\r
- if (phyAddr != SI_CecGetDevicePA ())\r
- {\r
- // Yes! So change the PA\r
- SI_CecSetDevicePA (phyAddr);\r
- }\r
- }\r
-#endif\r
-\r
- if ((DataIndex + 7) > VSDB_BaseOffset + DataBlockLength) // Offset of 3D_Present bit in VSDB\r
- g_edid._3D_Supported = FALSE;\r
- else if (Data[DataIndex + 7] >> 7)\r
- g_edid._3D_Supported = TRUE;\r
- else\r
- g_edid._3D_Supported = FALSE;\r
-\r
- DataIndex += DataBlockLength - RK610_HDMI_SIGNATURE_LEN - CEC_PHYS_ADDR_LEN; // Point to start of next block\r
- RK610_HDMI_DBG("EDID -> Short Descriptor Vendor Block\n");\r
- break;\r
-\r
- default:\r
- RK610_HDMI_DBG("EDID -> Unknown Tag Code\n");\r
- return EDID_UNKNOWN_TAG_CODE;\r
-\r
- } // End, Switch statement\r
- } // End, while (DataIndex < LongDescriptorOffset) statement\r
-\r
- return EDID_SHORT_DESCRIPTORS_OK;\r
-}\r
-\r
-//------------------------------------------------------------------------------\r
-// Function Name: Parse861LongDescriptors()\r
-// Function Description: Parse CEA-861 extension long descriptors of the EDID block\r
-// passed as a parameter and printf() them to the screen.\r
-//\r
-// Accepts: A pointer to the EDID block being parsed\r
-// Returns: An error code if no long descriptors found; EDID_PARSED_OK if descriptors found.\r
-// Globals: none\r
-//------------------------------------------------------------------------------\r
-byte Parse861LongDescriptors (byte *Data)\r
-{\r
- byte LongDescriptorsOffset;\r
- byte DescriptorNum = 1;\r
-\r
- LongDescriptorsOffset = Data[LONG_DESCR_PTR_IDX]; // EDID block offset 2 holds the offset\r
-\r
- if (!LongDescriptorsOffset) // per CEA-861-D, table 27\r
- {\r
- TPI_DEBUG_PRINT(("EDID -> No Detailed Descriptors\n"));\r
- return EDID_NO_DETAILED_DESCRIPTORS;\r
- }\r
-\r
- // of the 1st 18-byte descriptor\r
- while (LongDescriptorsOffset + LONG_DESCR_LEN < EDID_BLOCK_SIZE)\r
- {\r
- TPI_EDID_PRINT(("Parse Results - CEA-861 Long Descriptor #%d:\n", (int) DescriptorNum));\r
- TPI_EDID_PRINT(("===============================================================\n"));\r
-\r
-#if (CONF__TPI_EDID_PRINT == ENABLE)\r
- if (!ParseDetailedTiming(Data, LongDescriptorsOffset, EDID_BLOCK_2_3))\r
- break;\r
-#endif\r
- LongDescriptorsOffset += LONG_DESCR_LEN;\r
- DescriptorNum++;\r
- }\r
-\r
- return EDID_LONG_DESCRIPTORS_OK;\r
-}\r
-\r
-//------------------------------------------------------------------------------\r
-// Function Name: Parse861Extensions()\r
-// Function Description: Parse CEA-861 extensions from EDID ROM (EDID blocks beyond\r
-// block #0). Save short descriptors in global structure\r
-// g_edid. printf() long descriptors to the screen.\r
-//\r
-// Accepts: The number of extensions in the EDID being parsed\r
-// Returns: EDID_PARSED_OK if EDID parsed correctly. Error code if failed.\r
-// Globals: EDID data\r
-// NOTE: Fields that are not supported by the 9022/4 (such as deep color) were not parsed.\r
-//------------------------------------------------------------------------------\r
-byte Parse861Extensions (struct i2c_client *client,byte NumOfExtensions)\r
-{\r
- byte i,j,k;\r
- \r
- byte ErrCode;\r
- \r
-// byte V_DescriptorIndex = 0;\r
-// byte A_DescriptorIndex = 0;\r
- \r
- byte Block = 0;\r
- \r
- g_edid.HDMI_Sink = FALSE;\r
-\r
- do\r
- {\r
- Block++;\r
- HDMI_DBG("\n");\r
- \r
- for (j=0, i=0; j<128; j++)\r
- {\r
- k = edid_buf[j];\r
- HDMI_DBG("%2.2X ", (int) k);\r
- i++;\r
- \r
- if (i == 0x10)\r
- {\r
- HDMI_DBG("\n");\r
- i = 0;\r
- }\r
- }\r
- HDMI_DBG("\n");\r
- RK610_read_edid_block(client,Block, edid_buf);\r
- if ((NumOfExtensions > 1) && (Block == 1))\r
- {\r
- continue;\r
- }\r
- \r
- ErrCode = Parse861ShortDescriptors(edid_buf);\r
- if (ErrCode != EDID_SHORT_DESCRIPTORS_OK)\r
- {\r
- return ErrCode;\r
- }\r
- \r
- ErrCode = Parse861LongDescriptors(edid_buf);\r
- if (ErrCode != EDID_LONG_DESCRIPTORS_OK)\r
- {\r
- return ErrCode;\r
- }\r
- \r
- } while (Block < NumOfExtensions);\r
-\r
- return EDID_OK;\r
-}\r
-\r
-//------------------------------------------------------------------------------\r
-// Function Name: ParseEDID()\r
-// Function Description: Extract sink properties from its EDID file and save them in\r
-// global structure g_edid.\r
-//\r
-// Accepts: none\r
-// Returns: TRUE or FLASE\r
-// Globals: EDID data\r
-// NOTE: Fields that are not supported by the 9022/4 (such as deep color) were not parsed.\r
-//------------------------------------------------------------------------------\r
-static byte ParseEDID (byte *pEdid, byte *numExt)\r
-{\r
- if (!CheckEDID_Header(pEdid))\r
- {\r
- // first 8 bytes of EDID must be {0, FF, FF, FF, FF, FF, FF, 0}\r
- HDMI_ERR("EDID -> Incorrect Header\n");\r
- return EDID_INCORRECT_HEADER;\r
- }\r
-\r
- if (!DoEDID_Checksum(pEdid))\r
- {\r
- // non-zero EDID checksum\r
- HDMI_ERR("EDID -> Checksum Error\n");\r
- return EDID_CHECKSUM_ERROR;\r
- }\r
-\r
- *numExt = pEdid[NUM_OF_EXTEN_ADDR]; // read # of extensions from offset 0x7E of block 0\r
- HDMI_DBG("EDID -> 861 Extensions = %d\n", (int) *numExt);\r
-\r
- if (!(*numExt))\r
- {\r
- // No extensions to worry about\r
- HDMI_DBG("EDID -> EDID_NO_861_EXTENSIONS\n");\r
- return EDID_NO_861_EXTENSIONS;\r
- }\r
- return EDID_OK;\r
-}\r
-#endif\r
-\r
-//------------------------------------------------------------------------------\r
-// Function Name: CheckEDID_Header()\r
-// Function Description: Checks if EDID header is correct per VESA E-EDID standard\r
-//\r
-// Accepts: Pointer to 1st EDID block\r
-// Returns: TRUE or FLASE\r
-// Globals: EDID data\r
-//------------------------------------------------------------------------------\r
-byte CheckEDID_Header (byte *Block)\r
-{\r
- byte i = 0;\r
-\r
- if (Block[i]) // byte 0 must be 0\r
- return FALSE;\r
-\r
- for (i = 1; i < 1 + EDID_HDR_NO_OF_FF; i++)\r
- {\r
- if(Block[i] != 0xFF) // bytes [1..6] must be 0xFF\r
- return FALSE;\r
- }\r
-\r
- if (Block[i]) // byte 7 must be 0\r
- return FALSE;\r
-\r
- return TRUE;\r
-}\r
-\r
-//------------------------------------------------------------------------------\r
-// Function Name: DoEDID_Checksum()\r
-// Function Description: Calculte checksum of the 128 byte block pointed to by the\r
-// pointer passed as parameter\r
-//\r
-// Accepts: Pointer to a 128 byte block whose checksum needs to be calculated\r
-// Returns: TRUE or FLASE\r
-// Globals: EDID data\r
-//------------------------------------------------------------------------------\r
-byte DoEDID_Checksum (byte *Block)\r
-{\r
- byte i;\r
- byte CheckSum = 0;\r
-\r
- for (i = 0; i < EDID_BLOCK_SIZE; i++)\r
- CheckSum += Block[i];\r
-\r
- if (CheckSum)\r
- return FALSE;\r
-\r
- return TRUE;\r
-}\r
-//------------------------------------------------------------------------------\r
-// Function Name: Parse861ShortDescriptors()\r
-// Function Description: Parse CEA-861 extension short descriptors of the EDID block\r
-// passed as a parameter and save them in global structure g_edid.\r
-//\r
-// Accepts: A pointer to the EDID 861 Extension block being parsed.\r
-// Returns: EDID_PARSED_OK if EDID parsed correctly. Error code if failed.\r
-// Globals: EDID data\r
-// NOTE: Fields that are not supported by the 9022/4 (such as deep color) were not parsed.\r
-//------------------------------------------------------------------------------\r
-byte Parse861ShortDescriptors (struct i2c_client *client,byte *Data)\r
-{\r
- byte LongDescriptorOffset;\r
- byte DataBlockLength;\r
- byte DataIndex;\r
- byte ExtendedTagCode;\r
- byte VSDB_BaseOffset = 0;\r
-\r
- byte V_DescriptorIndex = 0; // static to support more than one extension\r
- byte A_DescriptorIndex = 0; // static to support more than one extension\r
-\r
- byte TagCode;\r
-\r
- byte i;\r
- byte j;\r
-\r
- if (Data[EDID_TAG_ADDR] != EDID_EXTENSION_TAG)\r
- {\r
- RK610_ERR(&client->dev,"EDID -> Extension Tag Error\n");\r
- return EDID_EXT_TAG_ERROR;\r
- }\r
-\r
- if (Data[EDID_REV_ADDR] != EDID_REV_THREE)\r
- {\r
- RK610_ERR(&client->dev,"EDID -> Revision Error\n");\r
- return EDID_REV_ADDR_ERROR;\r
- }\r
-\r
- LongDescriptorOffset = Data[LONG_DESCR_PTR_IDX]; // block offset where long descriptors start\r
-\r
- g_edid.UnderScan = ((Data[MISC_SUPPORT_IDX]) >> 7) & LSBIT; // byte #3 of CEA extension version 3\r
- g_edid.BasicAudio = ((Data[MISC_SUPPORT_IDX]) >> 6) & LSBIT;\r
- g_edid.YCbCr_4_4_4 = ((Data[MISC_SUPPORT_IDX]) >> 5) & LSBIT;\r
- g_edid.YCbCr_4_2_2 = ((Data[MISC_SUPPORT_IDX]) >> 4) & LSBIT;\r
-\r
- DataIndex = EDID_DATA_START; // 4\r
-\r
- while (DataIndex < LongDescriptorOffset)\r
- {\r
- TagCode = (Data[DataIndex] >> 5) & THREE_LSBITS;\r
- DataBlockLength = Data[DataIndex++] & FIVE_LSBITS;\r
- if ((DataIndex + DataBlockLength) > LongDescriptorOffset)\r
- {\r
- RK610_ERR(&client->dev,"EDID -> V Descriptor Overflow\n");\r
- return EDID_V_DESCR_OVERFLOW;\r
- }\r
-\r
- i = 0; // num of short video descriptors in current data block\r
-\r
- switch (TagCode)\r
- {\r
- case VIDEO_D_BLOCK:\r
- while ((i < DataBlockLength) && (i < MAX_V_DESCRIPTORS)) // each SVD is 1 byte long\r
- {\r
- g_edid.VideoDescriptor[V_DescriptorIndex++] = Data[DataIndex++];\r
- i++;\r
- }\r
- DataIndex += DataBlockLength - i; // if there are more STDs than MAX_V_DESCRIPTORS, skip the last ones. Update DataIndex\r
-\r
- RK610_DBG(&client->dev,"EDID -> Short Descriptor Video Block\n");\r
- break;\r
-\r
- case AUDIO_D_BLOCK:\r
- while (i < DataBlockLength/3) // each SAD is 3 bytes long\r
- {\r
- j = 0;\r
- while (j < AUDIO_DESCR_SIZE) // 3\r
- {\r
- g_edid.AudioDescriptor[A_DescriptorIndex][j++] = Data[DataIndex++];\r
- }\r
- A_DescriptorIndex++;\r
- i++;\r
- }\r
- RK610_DBG(&client->dev,"EDID -> Short Descriptor Audio Block\n");\r
- break;\r
-\r
- case SPKR_ALLOC_D_BLOCK:\r
- g_edid.SpkrAlloc[i++] = Data[DataIndex++]; // although 3 bytes are assigned to Speaker Allocation, only\r
- DataIndex += 2; // the first one carries information, so the next two are ignored by this code.\r
- RK610_DBG(&client->dev,"EDID -> Short Descriptor Speaker Allocation Block\n");\r
- break;\r
-\r
- case USE_EXTENDED_TAG:\r
- ExtendedTagCode = Data[DataIndex++];\r
-\r
- switch (ExtendedTagCode)\r
- {\r
- case VIDEO_CAPABILITY_D_BLOCK:\r
- RK610_DBG(&client->dev,"EDID -> Short Descriptor Video Capability Block\n");\r
-\r
- // TO BE ADDED HERE: Save "video capability" parameters in g_edid data structure\r
- // Need to modify that structure definition\r
- // In the meantime: just increment DataIndex by 1\r
- DataIndex += 1; // replace with reading and saving the proper data per CEA-861 sec. 7.5.6 while incrementing DataIndex\r
- break;\r
-\r
- case COLORIMETRY_D_BLOCK:\r
- g_edid.ColorimetrySupportFlags = Data[DataIndex++] & BITS_1_0;\r
- g_edid.MetadataProfile = Data[DataIndex++] & BITS_2_1_0;\r
-\r
- RK610_DBG(&client->dev,"EDID -> Short Descriptor Colorimetry Block\n");\r
- break;\r
- }\r
- break;\r
-\r
- case VENDOR_SPEC_D_BLOCK:\r
- VSDB_BaseOffset = DataIndex - 1;\r
-\r
- if ((Data[DataIndex++] == 0x03) && // check if sink is HDMI compatible\r
- (Data[DataIndex++] == 0x0C) &&\r
- (Data[DataIndex++] == 0x00))\r
-\r
- g_edid.HDMI_Sink = TRUE;\r
- else\r
- g_edid.HDMI_Sink = FALSE;\r
-\r
- g_edid.CEC_A_B = Data[DataIndex++]; // CEC Physical address\r
- g_edid.CEC_C_D = Data[DataIndex++];\r
-\r
-#ifdef DEV_SUPPORT_CEC\r
- // Take the Address that was passed in the EDID and use this API\r
- // to set the physical address for CEC.\r
- {\r
- word phyAddr;\r
- phyAddr = (word)g_edid.CEC_C_D; // Low-order nibbles\r
- phyAddr |= ((word)g_edid.CEC_A_B << 8); // Hi-order nibbles\r
- // Is the new PA different from the current PA?\r
- if (phyAddr != SI_CecGetDevicePA ())\r
- {\r
- // Yes! So change the PA\r
- SI_CecSetDevicePA (phyAddr);\r
- }\r
- }\r
-#endif\r
-\r
- if ((DataIndex + 7) > VSDB_BaseOffset + DataBlockLength) // Offset of 3D_Present bit in VSDB\r
- g_edid._3D_Supported = FALSE;\r
- else if (Data[DataIndex + 7] >> 7)\r
- g_edid._3D_Supported = TRUE;\r
- else\r
- g_edid._3D_Supported = FALSE;\r
-\r
- DataIndex += DataBlockLength - HDMI_SIGNATURE_LEN - CEC_PHYS_ADDR_LEN; // Point to start of next block\r
- RK610_DBG(&client->dev,"EDID -> Short Descriptor Vendor Block\n");\r
- break;\r
-\r
- default:\r
- RK610_ERR(&client->dev,"EDID -> Unknown Tag Code\n");\r
- return EDID_UNKNOWN_TAG_CODE;\r
-\r
- } // End, Switch statement\r
- } // End, while (DataIndex < LongDescriptorOffset) statement\r
-\r
- return EDID_SHORT_DESCRIPTORS_OK;\r
-}\r
-//------------------------------------------------------------------------------\r
-// Function Name: ParseEDID()\r
-// Function Description: Extract sink properties from its EDID file and save them in\r
-// global structure g_edid.\r
-//\r
-// Accepts: none\r
-// Returns: TRUE or FLASE\r
-// Globals: EDID data\r
-// NOTE: Fields that are not supported by the 9022/4 (such as deep color) were not parsed.\r
-//------------------------------------------------------------------------------\r
-static byte ParseEDID (struct i2c_client *client,byte *pEdid, byte *numExt)\r
-{\r
- if (!CheckEDID_Header(pEdid))\r
- {\r
- // first 8 bytes of EDID must be {0, FF, FF, FF, FF, FF, FF, 0}\r
- RK610_ERR(&client->dev,"EDID -> Incorrect Header\n");\r
- return EDID_INCORRECT_HEADER;\r
- }\r
-\r
- if (!DoEDID_Checksum(pEdid))\r
- {\r
- // non-zero EDID checksum\r
- RK610_ERR(&client->dev,"EDID -> Checksum Error\n");\r
- return EDID_CHECKSUM_ERROR;\r
- }\r
-\r
- *numExt = pEdid[NUM_OF_EXTEN_ADDR]; // read # of extensions from offset 0x7E of block 0\r
- RK610_DBG(&client->dev,"EDID -> 861 Extensions = %d\n", (int) *numExt);\r
-\r
- if (!(*numExt))\r
- {\r
- // No extensions to worry about\r
- RK610_DBG(&client->dev,"EDID -> EDID_NO_861_EXTENSIONS\n");\r
- return EDID_NO_861_EXTENSIONS;\r
- }\r
- return EDID_OK;\r
-}\r
-\r
-int Rk610_Parse_resolution(void)\r
-{\r
- int i,vic;\r
- memset(&Rk610_edid_result,0,sizeof(struct edid_result));\r
- for(i=0;i < MAX_V_DESCRIPTORS;i++){\r
- vic = g_edid.VideoDescriptor[i]&0x7f;\r
- if(vic == HDMI_VIC_1080p_50Hz)\r
- Rk610_edid_result.supported_1080p_50Hz = 1;\r
- else if(vic == HDMI_VIC_1080p_60Hz)\r
- Rk610_edid_result.supported_1080p_60Hz = 1; \r
- else if(vic == HDMI_VIC_720p_50Hz)\r
- Rk610_edid_result.supported_720p_50Hz = 1; \r
- else if(vic == HDMI_VIC_720p_60Hz)\r
- Rk610_edid_result.supported_720p_60Hz = 1; \r
- else if(vic == HDMI_VIC_576p_50Hz)\r
- Rk610_edid_result.supported_576p_50Hz = 1; \r
- else if(vic == HDMI_VIC_480p_60Hz)\r
- Rk610_edid_result.supported_720x480p_60Hz = 1; \r
- }\r
- #ifdef RK610_DEBUG\r
- printk("rk610_hdmi:1080p_50Hz %s\n",Rk610_edid_result.supported_1080p_50Hz?"support":"not support");\r
- printk("rk610_hdmi:1080p_60Hz %s\n",Rk610_edid_result.supported_1080p_60Hz?"support":"not support");\r
- printk("rk610_hdmi:720p_50Hz %s\n",Rk610_edid_result.supported_720p_50Hz?"support":"not support");\r
- printk("rk610_hdmi:720p_60Hz %s\n",Rk610_edid_result.supported_720p_60Hz?"support":"not support");\r
- printk("rk610_hdmi:576p_50Hz %s\n",Rk610_edid_result.supported_576p_50Hz?"support":"not support");\r
- printk("rk610_hdmi:720x480p_60Hz %s\n",Rk610_edid_result.supported_720x480p_60Hz?"support":"not support");\r
- #endif\r
- return 0;\r
-}\r
-\r
-int Rk610_Get_Optimal_resolution(int resolution_set)\r
-{\r
- int resolution_real;\r
- int find_resolution = 0;\r
- \r
- Rk610_Parse_resolution();\r
- switch(resolution_set){\r
- case HDMI_1280x720p_50Hz:\r
- if(Rk610_edid_result.supported_720p_50Hz){\r
- resolution_real = HDMI_1280x720p_50Hz;\r
- find_resolution = 1;\r
- }\r
- break;\r
- case HDMI_1280x720p_60Hz:\r
- if(Rk610_edid_result.supported_720p_60Hz){\r
- resolution_real = HDMI_1280x720p_60Hz;\r
- find_resolution = 1;\r
- }\r
- break;\r
- case HDMI_720x576p_50Hz_4x3:\r
- if(Rk610_edid_result.supported_576p_50Hz){\r
- resolution_real = HDMI_720x576p_50Hz_4x3;\r
- find_resolution = 1;\r
- }\r
- break;\r
- case HDMI_720x576p_50Hz_16x9:\r
- if(Rk610_edid_result.supported_576p_50Hz){\r
- resolution_real = HDMI_720x576p_50Hz_16x9;\r
- find_resolution = 1;\r
- }\r
- break;\r
- case HDMI_720x480p_60Hz_4x3:\r
- if(Rk610_edid_result.supported_720x480p_60Hz){\r
- resolution_real = HDMI_720x480p_60Hz_4x3;\r
- find_resolution = 1;\r
- }\r
- break;\r
- case HDMI_720x480p_60Hz_16x9:\r
- if(Rk610_edid_result.supported_720x480p_60Hz){\r
- resolution_real = HDMI_720x480p_60Hz_16x9;\r
- find_resolution = 1;\r
- }\r
- break;\r
- case HDMI_1920x1080p_50Hz:\r
- if(Rk610_edid_result.supported_1080p_50Hz){\r
- resolution_real = HDMI_1920x1080p_50Hz;\r
- find_resolution = 1;\r
- }\r
- break;\r
- case HDMI_1920x1080p_60Hz:\r
- if(Rk610_edid_result.supported_1080p_60Hz){\r
- resolution_real = HDMI_1920x1080p_60Hz;\r
- find_resolution = 1;\r
- }\r
- break;\r
- default:\r
- break;\r
- }\r
-\r
- if(find_resolution == 0){\r
-\r
- if(Rk610_edid_result.supported_720p_50Hz)\r
- resolution_real = HDMI_1280x720p_50Hz;\r
- else if(Rk610_edid_result.supported_720p_60Hz)\r
- resolution_real = HDMI_1280x720p_60Hz;\r
- else if(Rk610_edid_result.supported_1080p_50Hz)\r
- resolution_real = HDMI_1920x1080p_50Hz;\r
- else if(Rk610_edid_result.supported_1080p_60Hz)\r
- resolution_real = HDMI_1920x1080p_60Hz;\r
- else if(Rk610_edid_result.supported_576p_50Hz)\r
- resolution_real = HDMI_720x576p_50Hz_4x3;\r
- else if(Rk610_edid_result.supported_720x480p_60Hz)\r
- resolution_real = HDMI_720x480p_60Hz_4x3;\r
- else\r
- resolution_real = HDMI_1280x720p_60Hz;\r
- }\r
-\r
- return resolution_real;\r
-}\r
-\r
-byte DoEdidRead (struct i2c_client *client)\r
-{\r
- u8 NumOfExtensions=0;\r
- u8 Result;\r
- u8 i,j;\r
- // If we already have valid EDID data, ship this whole thing\r
- if (g_edid.edidDataValid == FALSE)\r
- {\r
- Rk610_hdmi_sys_power_up(client);\r
- // Request access to DDC bus from the receiver\r
- RK610_DDC_BUS_CONFIG(client);\r
- memset(edid_buf,0,EDID_BLOCK_SIZE);\r
- RK610_read_edid_block(client,EDID_BLOCK0, edid_buf); // read first 128 bytes of EDID ROM\r
- RK610_DBG(&client->dev,"/************first block*******/\n");\r
- #ifdef RK610_DEBUG\r
- for (j=0; j<EDID_BLOCK_SIZE; j++)\r
- {\r
- if(j%16==0)\r
- printk("\n%x :",j);\r
- printk("%2.2x ", edid_buf[j]);\r
- }\r
- #endif\r
- Result = ParseEDID(client,edid_buf, &NumOfExtensions);\r
- if(Result!=EDID_OK){\r
- if(Result==EDID_NO_861_EXTENSIONS){\r
- g_edid.HDMI_Sink = FALSE;\r
- }\r
- else {\r
- g_edid.HDMI_Sink = FALSE;\r
- return FALSE;\r
- }\r
- }\r
- else{\r
- NumOfExtensions = edid_buf[NUM_OF_EXTEN_ADDR];\r
- for(i=1;i<=NumOfExtensions;i++){\r
- RK610_DBG(&client->dev,"\n/************block %d*******/\n",i);\r
- memset(edid_buf,0,EDID_BLOCK_SIZE);\r
- RK610_read_edid_block(client,i, edid_buf); \r
- Parse861ShortDescriptors(client,edid_buf);\r
- #ifdef RK610_DEBUG\r
- for (j=0; j<EDID_BLOCK_SIZE; j++){\r
- if(j%16==0)\r
- printk("\n%x :",j);\r
- printk("%2.2X ", edid_buf[j]);\r
- }\r
- #endif\r
- }\r
-\r
- g_edid.HDMI_Sink = TRUE;\r
- }\r
-\r
-#if 0\r
- Result = ParseEDID(edid_buf, &NumOfExtensions);\r
- if (Result != EDID_OK)\r
- {\r
- if (Result == EDID_NO_861_EXTENSIONS)\r
- {\r
- RK610_DBG(&client->dev,"EDID -> No 861 Extensions\n");\r
- g_edid.HDMI_Sink = FALSE;\r
- g_edid.YCbCr_4_4_4 = FALSE;\r
- g_edid.YCbCr_4_2_2 = FALSE;\r
- g_edid.CEC_A_B = 0x00;\r
- g_edid.CEC_C_D = 0x00;\r
- }\r
- else\r
- {\r
- RK610_DBG(&client->dev,"EDID -> Parse FAILED\n");\r
- g_edid.HDMI_Sink = TRUE;\r
- g_edid.YCbCr_4_4_4 = FALSE;\r
- g_edid.YCbCr_4_2_2 = FALSE;\r
- g_edid.CEC_A_B = 0x00;\r
- g_edid.CEC_C_D = 0x00;\r
- }\r
- }\r
- else\r
- {\r
- RK610_DBG(&client->dev,"EDID -> Parse OK\n");\r
- Result = Parse861Extensions(NumOfExtensions); // Parse 861 Extensions (short and long descriptors);\r
- if (Result != EDID_OK)\r
- {\r
- RK610_DBG(&client->dev,"EDID -> Extension Parse FAILED\n");\r
- g_edid.HDMI_Sink = FALSE;\r
- g_edid.YCbCr_4_4_4 = FALSE;\r
- g_edid.YCbCr_4_2_2 = FALSE;\r
- g_edid.CEC_A_B = 0x00;\r
- g_edid.CEC_C_D = 0x00;\r
- }\r
- else\r
- {\r
- RK610_DBG(&client->dev,"EDID -> Extension Parse OK\n");\r
- g_edid.HDMI_Sink = TRUE;\r
- }\r
- }\r
-#endif\r
- RK610_DBG(&client->dev,"EDID -> NumOfExtensions = %d\n", NumOfExtensions);\r
- RK610_DBG(&client->dev,"EDID -> g_edid.HDMI_Sink = %d\n", (int)g_edid.HDMI_Sink);\r
- //RK610_DBG(&client->dev,"EDID -> g_edid.YCbCr_4_4_4 = %d\n", (int)g_edid.YCbCr_4_4_4);\r
- //RK610_DBG(&client->dev,"EDID -> g_edid.YCbCr_4_2_2 = %d\n", (int)g_edid.YCbCr_4_2_2);\r
- //RK610_DBG(&client->dev,"EDID -> g_edid.CEC_A_B = 0x%x\n", (int)g_edid.CEC_A_B);\r
- //RK610_DBG(&client->dev,"EDID -> g_edid.CEC_C_D = 0x%x\n", (int)g_edid.CEC_C_D);\r
-\r
- g_edid.edidDataValid = TRUE;\r
- }\r
- return TRUE;\r
-}\r
-\r
-static int Rk610_hdmi_Display_switch(struct i2c_client *client)\r
-{\r
- char c;\r
- int ret=0;\r
- int mode;\r
- mode = (g_edid.HDMI_Sink == TRUE)? DISPLAY_HDMI:DISPLAY_DVI;\r
- ret = Rk610_hdmi_i2c_read_p0_reg(client, 0x52, &c);\r
- if(mode == DISPLAY_HDMI)\r
- c |= DISPLAY_MODE; \r
- else \r
- c &= ~DISPLAY_MODE;\r
- ret = Rk610_hdmi_i2c_write_p0_reg(client, 0x52, &c);\r
- RK610_DBG(&client->dev,">>>%s mode=%d,c=%x",__func__,mode,c);\r
- return ret;\r
-}\r
-\r
-static int Rk610_hdmi_Config_audio_informat(struct i2c_client *client)\r
-{\r
- char c;\r
- int ret=0;\r
- RK610_DBG(&client->dev,"%s \n",__FUNCTION__);\r
- //Select configure for Audio Info\r
- c=0x08;\r
- ret = Rk610_hdmi_i2c_write_p0_reg(client, 0x9f, &c);\r
- //Configure the Audio info to HDMI RX.\r
- c=0x84; //HB0\r
- ret = Rk610_hdmi_i2c_write_p0_reg(client, 0xa0, &c);\r
- c=0x01; //HB1\r
- ret = Rk610_hdmi_i2c_write_p0_reg(client, 0xa1, &c);\r
- c=0x0a; //HB2\r
- ret = Rk610_hdmi_i2c_write_p0_reg(client, 0xa2, &c);\r
- //c=0x00; //PB0\r
- //ret = Rk610_hdmi_i2c_write_p0_reg(client, 0xa3, &c);\r
- c=0x11; //PB1\r
- ret = Rk610_hdmi_i2c_write_p0_reg(client, 0xa4, &c);\r
- c=0x09; //PB2\r
- ret = Rk610_hdmi_i2c_write_p0_reg(client, 0xa5, &c);\r
- c=0x00; //PB3\r
- ret = Rk610_hdmi_i2c_write_p0_reg(client, 0xa6, &c);\r
- c=0x00; //PB4\r
- ret = Rk610_hdmi_i2c_write_p0_reg(client, 0xa7, &c);\r
- c=0x01; //PB5\r
- ret = Rk610_hdmi_i2c_write_p0_reg(client, 0xa8, &c);\r
- return ret;\r
-}\r
-\r
-static int Rk610_hdmi_Config_Avi_informat(struct i2c_client *client ,u8 vic)\r
-{\r
- char c;\r
- int ret=0;\r
- RK610_DBG(&client->dev,"%s \n",__FUNCTION__);\r
- //Select configure for AVI Info\r
- c = 0x06; \r
- ret = Rk610_hdmi_i2c_write_p0_reg(client, 0x9f, &c);\r
-\r
- //Configure the AVI info to HDMI RX\r
- c = 0x82; //HB0\r
- ret = Rk610_hdmi_i2c_write_p0_reg(client, 0xa0, &c);\r
- c = 0x02; //HB1\r
- ret = Rk610_hdmi_i2c_write_p0_reg(client, 0xa1, &c);\r
- c = 0x0d; //HB2\r
- ret = Rk610_hdmi_i2c_write_p0_reg(client, 0xa2, &c);\r
- //c=0x00; //PB0\r
- //ret = Rk610_hdmi_i2c_write_p0_reg(client, 0xa3, &c);\r
- c = 0x00; //PB1\r
- ret = Rk610_hdmi_i2c_write_p0_reg(client, 0xa4, &c);\r
- c = 0x08; //PB2\r
- ret = Rk610_hdmi_i2c_write_p0_reg(client, 0xa5, &c);\r
- c = 0x70; //PB3\r
- ret = Rk610_hdmi_i2c_write_p0_reg(client, 0xa6, &c);\r
- c = vic; //PB4\r
- ret = Rk610_hdmi_i2c_write_p0_reg(client, 0xa7, &c);\r
- c = 0x40; //PB5\r
- ret = Rk610_hdmi_i2c_write_p0_reg(client, 0xa8, &c);\r
- return ret;\r
-}\r
-static int Rk610_hdmi_Config_Video(struct i2c_client *client, u8 video_format)\r
-{\r
- char vic;\r
- int ret = 0;\r
- RK610_DBG(&client->dev,"%s \n",__FUNCTION__);\r
- switch(video_format){\r
- case HDMI_720x480p_60Hz_4x3:\r
- case HDMI_720x480p_60Hz_16x9:\r
- vic = HDMI_VIC_480p_60Hz;\r
- break;\r
- case HDMI_720x576p_50Hz_4x3:\r
- case HDMI_720x576p_50Hz_16x9:\r
- vic = HDMI_VIC_576p_50Hz;\r
- break;\r
- case HDMI_1280x720p_50Hz:\r
- vic = HDMI_VIC_720p_50Hz;\r
- break;\r
- case HDMI_1280x720p_60Hz:\r
- vic = HDMI_VIC_720p_60Hz;\r
- break;\r
- case HDMI_1920x1080p_50Hz:\r
- vic = HDMI_VIC_1080p_50Hz;\r
- break;\r
- case HDMI_1920x1080p_60Hz:\r
- vic = HDMI_VIC_1080p_60Hz;\r
- break;\r
- default:\r
- vic = 0x04;\r
- break;\r
- }\r
- ret = Rk610_hdmi_Config_Avi_informat(client,vic);\r
- return ret;\r
-}\r
-static int Rk610_hdmi_Config_Audio(struct i2c_client *client ,u8 audio_fs)\r
-{\r
- char c=0;\r
- int ret = 0;\r
- RK610_DBG(&client->dev,"%s \n",__FUNCTION__);\r
- c=0x01;\r
- ret = Rk610_hdmi_i2c_write_p0_reg(client, 0x35, &c);\r
- c=0x3c;\r
- ret = Rk610_hdmi_i2c_write_p0_reg(client, 0x38, &c);\r
- c=0x00;\r
- ret = Rk610_hdmi_i2c_write_p0_reg(client, 0x39, &c);\r
- c=0x18;\r
- ret = Rk610_hdmi_i2c_write_p0_reg(client, 0x40, &c);\r
- switch(audio_fs){\r
- case HDMI_I2S_Fs_44100:\r
- c=0x80;\r
- ret = Rk610_hdmi_i2c_write_p0_reg(client, 0x41, &c);\r
- break;\r
- case HDMI_I2S_Fs_48000:\r
- c=0x92;\r
- ret = Rk610_hdmi_i2c_write_p0_reg(client, 0x41, &c);\r
- break;\r
- default:\r
- c=0x80;\r
- ret = Rk610_hdmi_i2c_write_p0_reg(client, 0x41, &c);\r
- break;\r
- }\r
- Rk610_hdmi_Config_audio_informat(client);\r
- return ret;\r
-}\r
-\r
-int Rk610_hdmi_Set_Video(u8 video_format)\r
-{\r
- if(g_hw_inf.video_format !=video_format){\r
- g_hw_inf.video_format = video_format;\r
- g_hw_inf.config_param |= VIDEO_CHANGE;\r
- }\r
- return 0;\r
-}\r
-int Rk610_hdmi_Set_Audio(u8 audio_fs)\r
-{\r
- if(g_hw_inf.audio_fs !=audio_fs){\r
- g_hw_inf.audio_fs = audio_fs;\r
- g_hw_inf.config_param |= AUDIO_CHANGE;\r
- }\r
- return 0;\r
-}\r
-static int RK610_hdmi_Driver_mode(struct i2c_client *client)\r
-{\r
- char c;\r
- int ret=0;\r
- c=0x8e;\r
- ret =Rk610_hdmi_i2c_write_p0_reg(client, 0xe1, &c);\r
- c=0x04;\r
- ret =Rk610_hdmi_i2c_write_p0_reg(client, 0xe2, &c);\r
- return 0;\r
-}\r
-static int RK610_hdmi_PLL_mode(struct i2c_client *client)\r
-{\r
- char c;\r
- int ret=0;\r
- c=0x10;\r
- ret = Rk610_hdmi_i2c_write_p0_reg(client, 0xe8, &c);\r
- c=0x2c;\r
- ret = Rk610_hdmi_i2c_write_p0_reg(client, 0xe6, &c);\r
- c=0x00;\r
- ret = Rk610_hdmi_i2c_write_p0_reg(client, 0xe5, &c);\r
- return 0;\r
-}\r
-void Rk610_hdmi_plug(struct i2c_client *client)\r
-{\r
- RK610_DBG(&client->dev,">>> hdmi plug \n");\r
- DoEdidRead(client);\r
- Rk610_hdmi_Display_switch(client);\r
- Rk610_hdmi_pwr_mode(client,NORMAL);\r
-}\r
-void Rk610_hdmi_unplug(struct i2c_client *client)\r
-{\r
- RK610_DBG(&client->dev,">>> hdmi unplug \n");\r
- g_edid.edidDataValid = FALSE;\r
- Rk610_hdmi_pwr_mode(client,LOWER_PWR); \r
-}\r
-void Rk610_hdmi_event_work(struct i2c_client *client, bool *hpd)\r
-{\r
- char c=0;\r
- int ret=0;\r
- if(g_hw_inf.suspend_flag == 1){\r
- *hpd = 0;\r
- return ;\r
- }\r
-\r
- c=0x00;\r
- ret =Rk610_hdmi_i2c_read_p0_reg(client, 0xc1, &c);\r
- if(c & RK610_HPD_EVENT){\r
- RK610_DBG(&client->dev,">>>HPD EVENT\n");\r
- /**********clear hpd event******/\r
- c = RK610_HPD_EVENT;\r
- ret =Rk610_hdmi_i2c_write_p0_reg(client, 0xc1, &c);\r
- ret =Rk610_hdmi_i2c_read_p0_reg(client, 0xc8, &c);\r
- if(c & RK610_HPD_PLUG ){\r
- // Rk610_hdmi_plug(client);\r
- g_hw_inf.hpd=1;\r
- }\r
- else{\r
- // Rk610_hdmi_unplug(client);\r
- g_hw_inf.hpd=0;\r
- }\r
-\r
- }\r
- if(c & RK610_EDID_EVENT){\r
- /**********clear hpd event******/\r
- c = RK610_EDID_EVENT;\r
- ret =Rk610_hdmi_i2c_write_p0_reg(client, 0xc1, &c);\r
- RK610_DBG(&client->dev,">>>EDID EVENT\n");\r
- /*************clear edid event*********/\r
- }\r
- *hpd = g_hw_inf.hpd;\r
-}\r
-int Rk610_hdmi_Config_Done(struct i2c_client *client)\r
-{\r
- char c;\r
- int ret=0;\r
- RK610_DBG(&client->dev,"%s \n",__FUNCTION__);\r
-\r
- ret =Rk610_hdmi_sys_power_down(client);\r
-\r
- if(g_hw_inf.config_param != 0){\r
- c=0x08;\r
- ret =Rk610_hdmi_i2c_write_p0_reg(client, 0x04, &c);\r
- c=0x01;\r
- ret =Rk610_hdmi_i2c_write_p0_reg(client, 0x01, &c);\r
- if(g_hw_inf.config_param & VIDEO_CHANGE){\r
- Rk610_hdmi_Config_Video(client,g_hw_inf.video_format);\r
- g_hw_inf.config_param &= (~VIDEO_CHANGE); \r
- }\r
- if(g_hw_inf.config_param & AUDIO_CHANGE){\r
- Rk610_hdmi_Config_Audio(client,g_hw_inf.audio_fs);\r
- g_hw_inf.config_param &= (~AUDIO_CHANGE); \r
- }\r
- }\r
- ret =Rk610_hdmi_sys_power_up(client);\r
- ret =Rk610_hdmi_sys_power_down(client);\r
- ret =Rk610_hdmi_sys_power_up(client);\r
- if(g_hw_inf.analog_sync){\r
- c=0x00;\r
- ret =Rk610_hdmi_i2c_write_p0_reg(client, 0xce, &c);\r
- c=0x01;\r
- ret =Rk610_hdmi_i2c_write_p0_reg(client, 0xce, &c);\r
- g_hw_inf.analog_sync = 0;\r
- }\r
-\r
- return ret;\r
-}\r
-#if 0\r
-int Rk610_hdmi_hpd(struct i2c_client *client)\r
-{\r
- char c;\r
- RK610_DBG(&client->dev,"%s \n",__FUNCTION__);\r
- if(Rk610_hdmi_i2c_read_p0_reg(client, 0xc8, &c)<0){\r
- RK610_ERR(">>>%s I2c trans err",__FUNCTION__);\r
- return -1;\r
- }\r
- if()\r
- return (c & RK610_HPD_PLUG)?1:0;\r
-}\r
-#endif\r
-static int RK610_hdmi_soft_reset(struct i2c_client *client)\r
-{\r
- char c;\r
- int ret;\r
- //soft reset\r
- c=0x00;\r
- ret =Rk610_hdmi_i2c_read_p0_reg(client, 0xce, &c);\r
- msleep(10);\r
- c=0x01;\r
- ret =Rk610_hdmi_i2c_read_p0_reg(client, 0xce, &c); \r
- msleep(100);\r
- return ret;\r
-}\r
-static void Rk610_hdmi_Variable_Initial(void)\r
-{\r
- memset(&g_hw_inf,0,sizeof(struct rk610_hdmi_hw_inf));\r
- g_edid.edidDataValid = FALSE;\r
- g_hw_inf.edid_inf = &g_edid; \r
- g_hw_inf.audio_fs = HDMI_I2S_DEFAULT_Fs;\r
- g_hw_inf.video_format = HDMI_DEFAULT_RESOLUTION;\r
- g_hw_inf.config_param = AUDIO_CHANGE | VIDEO_CHANGE;\r
- g_hw_inf.hpd = 0;\r
- g_hw_inf.suspend_flag = 0;\r
- g_hw_inf.analog_sync = 0;\r
-}\r
-int Rk610_hdmi_init(struct i2c_client *client)\r
-{\r
- char c;\r
- RK610_DBG(&client->dev,"%s \n",__FUNCTION__);\r
- Rk610_hdmi_Variable_Initial();\r
- RK610_hdmi_soft_reset(client);\r
- RK610_hdmi_Driver_mode(client);\r
- RK610_hdmi_PLL_mode(client);\r
- Rk610_hdmi_Set_Video(g_hw_inf.video_format);\r
- Rk610_hdmi_Set_Audio(g_hw_inf.audio_fs);\r
- Rk610_hdmi_Config_Done(client);\r
- Rk610_hdmi_i2c_read_p0_reg(client, 0xc8, &c);\r
- if(c & RK610_HPD_PLUG ){\r
- Rk610_hdmi_plug(client);\r
- g_hw_inf.hpd=1;\r
- }else{\r
- Rk610_hdmi_unplug(client);\r
- g_hw_inf.hpd=0;\r
- }\r
- return 0;\r
-}\r
projects / firefly-linux-kernel-4.4.55.git / commitdiff