drm/radeon: Print gart initialization details on all chipsets
authorTormod Volden <debian.tormod@gmail.com>
Wed, 31 Aug 2011 21:54:07 +0000 (21:54 +0000)
committerDave Airlie <airlied@redhat.com>
Tue, 6 Sep 2011 10:55:08 +0000 (11:55 +0100)
This was previously done for r300 only. Use %016llX instead of %08X for
printing the table address.

Also fix typos in gart warning messages.

Signed-off-by: Tormod Volden <debian.tormod@gmail.com>
Reviewed-by: Michel Dänzer <michel@daenzer.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
drivers/gpu/drm/radeon/evergreen.c
drivers/gpu/drm/radeon/ni.c
drivers/gpu/drm/radeon/r100.c
drivers/gpu/drm/radeon/r300.c
drivers/gpu/drm/radeon/r600.c
drivers/gpu/drm/radeon/radeon_gart.c
drivers/gpu/drm/radeon/rs400.c
drivers/gpu/drm/radeon/rs600.c
drivers/gpu/drm/radeon/rv770.c

index d8d71a399f527ac1c729e25221fc95f503251091..0b517e16fd3ad4cbf5330cab008a3a788d2f5032 100644 (file)
@@ -910,6 +910,9 @@ int evergreen_pcie_gart_enable(struct radeon_device *rdev)
        WREG32(VM_CONTEXT1_CNTL, 0);
 
        evergreen_pcie_gart_tlb_flush(rdev);
+       DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
+                (unsigned)(rdev->mc.gtt_size >> 20),
+                (unsigned long long)rdev->gart.table_addr);
        rdev->gart.ready = true;
        return 0;
 }
index a2e00fa9c6185989f02e9847d81dc156335adda8..3b8b849643d03f317b3206a50758f39d4f29034a 100644 (file)
@@ -996,6 +996,9 @@ int cayman_pcie_gart_enable(struct radeon_device *rdev)
        WREG32(VM_CONTEXT1_CNTL, 0);
 
        cayman_pcie_gart_tlb_flush(rdev);
+       DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
+                (unsigned)(rdev->mc.gtt_size >> 20),
+                (unsigned long long)rdev->gart.table_addr);
        rdev->gart.ready = true;
        return 0;
 }
index f2204cb1ccdfa96e0daa22ed9963a59555664f19..574f2c7c6dd96c9ff0a9399bcb9add3bb7c08a48 100644 (file)
@@ -513,6 +513,9 @@ int r100_pci_gart_enable(struct radeon_device *rdev)
        tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
        WREG32(RADEON_AIC_CNTL, tmp);
        r100_pci_gart_tlb_flush(rdev);
+       DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
+                (unsigned)(rdev->mc.gtt_size >> 20),
+                (unsigned long long)rdev->gart.table_addr);
        rdev->gart.ready = true;
        return 0;
 }
index 55a7f190027ee425a00a9f902c7526d3ee6adb43..33f2b68c680b349a5d9e097776d329fc047a37ef 100644 (file)
@@ -144,8 +144,9 @@ int rv370_pcie_gart_enable(struct radeon_device *rdev)
        tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
        WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
        rv370_pcie_gart_tlb_flush(rdev);
-       DRM_INFO("PCIE GART of %uM enabled (table at 0x%08X).\n",
-                (unsigned)(rdev->mc.gtt_size >> 20), table_addr);
+       DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
+                (unsigned)(rdev->mc.gtt_size >> 20),
+                (unsigned long long)table_addr);
        rdev->gart.ready = true;
        return 0;
 }
index aa5571b73aa02e947ec590ad6febb624778fc3da..334aee6eab7ce03b4ed7cf9e151f4977755dce28 100644 (file)
@@ -993,6 +993,9 @@ int r600_pcie_gart_enable(struct radeon_device *rdev)
                WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 
        r600_pcie_gart_tlb_flush(rdev);
+       DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
+                (unsigned)(rdev->mc.gtt_size >> 20),
+                (unsigned long long)rdev->gart.table_addr);
        rdev->gart.ready = true;
        return 0;
 }
index a533f52fd163b51c3c89c6f501792e167b9a727a..fdc3a9a54bf8e13cd6e4d9d475630cbec546b3b3 100644 (file)
@@ -142,7 +142,7 @@ void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
        u64 page_base;
 
        if (!rdev->gart.ready) {
-               WARN(1, "trying to unbind memory to unitialized GART !\n");
+               WARN(1, "trying to unbind memory from uninitialized GART !\n");
                return;
        }
        t = offset / RADEON_GPU_PAGE_SIZE;
@@ -174,7 +174,7 @@ int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
        int i, j;
 
        if (!rdev->gart.ready) {
-               WARN(1, "trying to bind memory to unitialized GART !\n");
+               WARN(1, "trying to bind memory to uninitialized GART !\n");
                return -EINVAL;
        }
        t = offset / RADEON_GPU_PAGE_SIZE;
index aa6a66eeb4ec8323ddeb77063e40c7c35b7e29eb..89a6e1ecea8deb595e8639a459f7aa477e5c287e 100644 (file)
@@ -182,6 +182,9 @@ int rs400_gart_enable(struct radeon_device *rdev)
        /* Enable gart */
        WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN | size_reg));
        rs400_gart_tlb_flush(rdev);
+       DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
+                (unsigned)(rdev->mc.gtt_size >> 20),
+                (unsigned long long)rdev->gart.table_addr);
        rdev->gart.ready = true;
        return 0;
 }
index 4b5d0e6974a8f0b5b9abefd54e15404c9bb3f92a..9320dd6404f67cdbe9ac3ba20aa6e4e582745904 100644 (file)
@@ -484,6 +484,9 @@ static int rs600_gart_enable(struct radeon_device *rdev)
        tmp = RREG32_MC(R_000009_MC_CNTL1);
        WREG32_MC(R_000009_MC_CNTL1, (tmp | S_000009_ENABLE_PAGE_TABLES(1)));
        rs600_gart_tlb_flush(rdev);
+       DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
+                (unsigned)(rdev->mc.gtt_size >> 20),
+                (unsigned long long)rdev->gart.table_addr);
        rdev->gart.ready = true;
        return 0;
 }
index 4720d000d440cd680723ccca2028b45ae2f4274d..80928f9ff80f7bd2a6b7545c70d79773d57aaef8 100644 (file)
@@ -161,6 +161,9 @@ int rv770_pcie_gart_enable(struct radeon_device *rdev)
                WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 
        r600_pcie_gart_tlb_flush(rdev);
+       DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
+                (unsigned)(rdev->mc.gtt_size >> 20),
+                (unsigned long long)rdev->gart.table_addr);
        rdev->gart.ready = true;
        return 0;
 }