Test cases named with dates is a legacy rule not used now. Rename several test cases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209877 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/test/CodeGen/AArch64/2014-05-29-shrink-v1i64.ll b/test/CodeGen/AArch64/2014-05-29-shrink-v1i64.ll
deleted file mode 100644 (file)
index f31a570..0000000
--- a/test/CodeGen/AArch64/2014-05-29-shrink-v1i64.ll
+++ /dev/null
@@ -1,14 +0,0 @@
-; RUN: llc -march=arm64 < %s
-
-; The DAGCombiner tries to do following shrink:
-;     Convert x+y to (VT)((SmallVT)x+(SmallVT)y)
-; But currently it can't handle vector type and will trigger an assertion failure
-; when it tries to generate an add mixed using vector type and scaler type.
-; This test checks that such assertion failur should not happen.
-define <1 x i64> @dotest(<1 x i64> %in0) {
-entry:
-  %0 = add <1 x i64> %in0, %in0
-  %vshl_n = shl <1 x i64> %0, <i64 32>
-  %vsra_n = ashr <1 x i64> %vshl_n, <i64 32>
-  ret <1 x i64> %vsra_n
-}

diff --git a/test/CodeGen/AArch64/arm64-2014-04-16-AnInfiniteLoopInDAGCombine.ll b/test/CodeGen/AArch64/arm64-2014-04-16-AnInfiniteLoopInDAGCombine.ll
deleted file mode 100644 (file)
index a73b707..0000000
--- a/test/CodeGen/AArch64/arm64-2014-04-16-AnInfiniteLoopInDAGCombine.ll
+++ /dev/null
@@ -1,23 +0,0 @@
-; RUN: llc < %s -march=arm64
-
-; This test case tests an infinite loop bug in DAG combiner.
-; It just tries to do the following replacing endlessly:
-; (1)  Replacing.3 0x2c509f0: v4i32 = any_extend 0x2c4cd08 [ORD=4]
-;      With: 0x2c4d128: v4i32 = sign_extend 0x2c4cd08 [ORD=4]
-;
-; (2)  Replacing.2 0x2c4d128: v4i32 = sign_extend 0x2c4cd08 [ORD=4]
-;      With: 0x2c509f0: v4i32 = any_extend 0x2c4cd08 [ORD=4]
-; As we think the (2) optimization from SIGN_EXTEND to ANY_EXTEND is
-; an optimization to replace unused bits with undefined bits, we remove
-; the (1) optimization (It doesn't make sense to replace undefined bits
-; with signed bits).
-
-define <4 x i32> @infiniteLoop(<4 x i32> %in0, <4 x i16> %in1) {
-entry:
-  %cmp.i = icmp sge <4 x i16> %in1, <i16 32767, i16 32767, i16 -1, i16 -32768>
-  %sext.i = sext <4 x i1> %cmp.i to <4 x i32>
-  %mul.i = mul <4 x i32> %in0, %sext.i
-  %sext = shl <4 x i32> %mul.i, <i32 16, i32 16, i32 16, i32 16>
-  %vmovl.i.i = ashr <4 x i32> %sext, <i32 16, i32 16, i32 16, i32 16>
-  ret <4 x i32> %vmovl.i.i
-}
\ No newline at end of file

diff --git a/test/CodeGen/AArch64/arm64-2014-04-28-sqshl-uqshl-i64Contant.ll b/test/CodeGen/AArch64/arm64-2014-04-28-sqshl-uqshl-i64Contant.ll
deleted file mode 100644 (file)
index 3949b85..0000000
--- a/test/CodeGen/AArch64/arm64-2014-04-28-sqshl-uqshl-i64Contant.ll
+++ /dev/null
@@ -1,19 +0,0 @@
-; RUN: llc < %s -verify-machineinstrs -march=arm64 | FileCheck %s
-
-; Check if sqshl/uqshl with constant shift amout can be selected. 
-define i64 @test_vqshld_s64_i(i64 %a) {
-; CHECK-LABEL: test_vqshld_s64_i:
-; CHECK: sqshl {{d[0-9]+}}, {{d[0-9]+}}, #36
-  %1 = tail call i64 @llvm.aarch64.neon.sqshl.i64(i64 %a, i64 36)
-  ret i64 %1
-}
-
-define i64 @test_vqshld_u64_i(i64 %a) {
-; CHECK-LABEL: test_vqshld_u64_i:
-; CHECK: uqshl {{d[0-9]+}}, {{d[0-9]+}}, #36
-  %1 = tail call i64 @llvm.aarch64.neon.uqshl.i64(i64 %a, i64 36)
-  ret i64 %1
-}
-
-declare i64 @llvm.aarch64.neon.uqshl.i64(i64, i64)
-declare i64 @llvm.aarch64.neon.sqshl.i64(i64, i64)

diff --git a/test/CodeGen/AArch64/arm64-2014-04-29-EXT-undef-mask.ll b/test/CodeGen/AArch64/arm64-2014-04-29-EXT-undef-mask.ll
deleted file mode 100644 (file)
index 1b2d543..0000000
--- a/test/CodeGen/AArch64/arm64-2014-04-29-EXT-undef-mask.ll
+++ /dev/null
@@ -1,23 +0,0 @@
-; RUN: llc < %s -O0 -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
-
-; The following 2 test cases test shufflevector with beginning UNDEF mask.
-define <8 x i16> @test_vext_undef_traverse(<8 x i16> %in) {
-;CHECK-LABEL: test_vext_undef_traverse:
-;CHECK: {{ext.16b.*v0, #4}}
-  %vext = shufflevector <8 x i16> <i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 0, i16 0>, <8 x i16> %in, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 6, i32 7, i32 8, i32 9>
-  ret <8 x i16> %vext
-}
-
-define <8 x i16> @test_vext_undef_traverse2(<8 x i16> %in) {
-;CHECK-LABEL: test_vext_undef_traverse2:
-;CHECK: {{ext.16b.*v0, #6}}
-  %vext = shufflevector <8 x i16> %in, <8 x i16> <i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef>, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 0, i32 1, i32 2>
-  ret <8 x i16> %vext
-}
-
-define <8 x i8> @test_vext_undef_traverse3(<8 x i8> %in) {
-;CHECK-LABEL: test_vext_undef_traverse3:
-;CHECK: {{ext.8b.*v0, #6}}
-  %vext = shufflevector <8 x i8> %in, <8 x i8> <i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 2, i32 3, i32 4, i32 5>
-  ret <8 x i8> %vext
-}

diff --git a/test/CodeGen/AArch64/arm64-AnInfiniteLoopInDAGCombine.ll b/test/CodeGen/AArch64/arm64-AnInfiniteLoopInDAGCombine.ll
new file mode 100644 (file)
index 0000000..a73b707
--- /dev/null
+++ b/test/CodeGen/AArch64/arm64-AnInfiniteLoopInDAGCombine.ll
@@ -0,0 +1,23 @@
+; RUN: llc < %s -march=arm64
+
+; This test case tests an infinite loop bug in DAG combiner.
+; It just tries to do the following replacing endlessly:
+; (1)  Replacing.3 0x2c509f0: v4i32 = any_extend 0x2c4cd08 [ORD=4]
+;      With: 0x2c4d128: v4i32 = sign_extend 0x2c4cd08 [ORD=4]
+;
+; (2)  Replacing.2 0x2c4d128: v4i32 = sign_extend 0x2c4cd08 [ORD=4]
+;      With: 0x2c509f0: v4i32 = any_extend 0x2c4cd08 [ORD=4]
+; As we think the (2) optimization from SIGN_EXTEND to ANY_EXTEND is
+; an optimization to replace unused bits with undefined bits, we remove
+; the (1) optimization (It doesn't make sense to replace undefined bits
+; with signed bits).
+
+define <4 x i32> @infiniteLoop(<4 x i32> %in0, <4 x i16> %in1) {
+entry:
+  %cmp.i = icmp sge <4 x i16> %in1, <i16 32767, i16 32767, i16 -1, i16 -32768>
+  %sext.i = sext <4 x i1> %cmp.i to <4 x i32>
+  %mul.i = mul <4 x i32> %in0, %sext.i
+  %sext = shl <4 x i32> %mul.i, <i32 16, i32 16, i32 16, i32 16>
+  %vmovl.i.i = ashr <4 x i32> %sext, <i32 16, i32 16, i32 16, i32 16>
+  ret <4 x i32> %vmovl.i.i
+}
\ No newline at end of file

diff --git a/test/CodeGen/AArch64/arm64-EXT-undef-mask.ll b/test/CodeGen/AArch64/arm64-EXT-undef-mask.ll
new file mode 100644 (file)
index 0000000..1b2d543
--- /dev/null
+++ b/test/CodeGen/AArch64/arm64-EXT-undef-mask.ll
@@ -0,0 +1,23 @@
+; RUN: llc < %s -O0 -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
+
+; The following 2 test cases test shufflevector with beginning UNDEF mask.
+define <8 x i16> @test_vext_undef_traverse(<8 x i16> %in) {
+;CHECK-LABEL: test_vext_undef_traverse:
+;CHECK: {{ext.16b.*v0, #4}}
+  %vext = shufflevector <8 x i16> <i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 0, i16 0>, <8 x i16> %in, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 6, i32 7, i32 8, i32 9>
+  ret <8 x i16> %vext
+}
+
+define <8 x i16> @test_vext_undef_traverse2(<8 x i16> %in) {
+;CHECK-LABEL: test_vext_undef_traverse2:
+;CHECK: {{ext.16b.*v0, #6}}
+  %vext = shufflevector <8 x i16> %in, <8 x i16> <i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef>, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 0, i32 1, i32 2>
+  ret <8 x i16> %vext
+}
+
+define <8 x i8> @test_vext_undef_traverse3(<8 x i8> %in) {
+;CHECK-LABEL: test_vext_undef_traverse3:
+;CHECK: {{ext.8b.*v0, #6}}
+  %vext = shufflevector <8 x i8> %in, <8 x i8> <i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 2, i32 3, i32 4, i32 5>
+  ret <8 x i8> %vext
+}

diff --git a/test/CodeGen/AArch64/arm64-shrink-v1i64.ll b/test/CodeGen/AArch64/arm64-shrink-v1i64.ll
new file mode 100644 (file)
index 0000000..f31a570
--- /dev/null
+++ b/test/CodeGen/AArch64/arm64-shrink-v1i64.ll
@@ -0,0 +1,14 @@
+; RUN: llc -march=arm64 < %s
+
+; The DAGCombiner tries to do following shrink:
+;     Convert x+y to (VT)((SmallVT)x+(SmallVT)y)
+; But currently it can't handle vector type and will trigger an assertion failure
+; when it tries to generate an add mixed using vector type and scaler type.
+; This test checks that such assertion failur should not happen.
+define <1 x i64> @dotest(<1 x i64> %in0) {
+entry:
+  %0 = add <1 x i64> %in0, %in0
+  %vshl_n = shl <1 x i64> %0, <i64 32>
+  %vsra_n = ashr <1 x i64> %vshl_n, <i64 32>
+  ret <1 x i64> %vsra_n
+}

diff --git a/test/CodeGen/AArch64/arm64-sqshl-uqshl-i64Contant.ll b/test/CodeGen/AArch64/arm64-sqshl-uqshl-i64Contant.ll
new file mode 100644 (file)
index 0000000..3949b85
--- /dev/null
+++ b/test/CodeGen/AArch64/arm64-sqshl-uqshl-i64Contant.ll
@@ -0,0 +1,19 @@
+; RUN: llc < %s -verify-machineinstrs -march=arm64 | FileCheck %s
+
+; Check if sqshl/uqshl with constant shift amout can be selected. 
+define i64 @test_vqshld_s64_i(i64 %a) {
+; CHECK-LABEL: test_vqshld_s64_i:
+; CHECK: sqshl {{d[0-9]+}}, {{d[0-9]+}}, #36
+  %1 = tail call i64 @llvm.aarch64.neon.sqshl.i64(i64 %a, i64 36)
+  ret i64 %1
+}
+
+define i64 @test_vqshld_u64_i(i64 %a) {
+; CHECK-LABEL: test_vqshld_u64_i:
+; CHECK: uqshl {{d[0-9]+}}, {{d[0-9]+}}, #36
+  %1 = tail call i64 @llvm.aarch64.neon.uqshl.i64(i64 %a, i64 36)
+  ret i64 %1
+}
+
+declare i64 @llvm.aarch64.neon.uqshl.i64(i64, i64)
+declare i64 @llvm.aarch64.neon.sqshl.i64(i64, i64)