X86: Don't transform shifts into ands when the sign bit is tested.

Should unbreak MultiSource/Benchmarks/mediabench/g721/g721encode/encode.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207145 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 8800bff87f8676ae44cfcf3751ce6af1bc1409cf..e59560ed88bfde67d39db797a245e624ae6a6a4a 100644 (file)
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -9802,7 +9802,8 @@ SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
     // If we have a constant logical shift that's only used in a comparison
     // against zero turn it into an equivalent AND. This allows turning it into
     // a TEST instruction later.
-    if (isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
+    if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) &&
+        isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
       EVT VT = Op.getValueType();
       unsigned BitWidth = VT.getSizeInBits();
       unsigned ShAmt = Op->getConstantOperandVal(1);

diff --git a/test/CodeGen/X86/cmp.ll b/test/CodeGen/X86/cmp.ll
index c52197f9be42e5ec6630459b1d9747f113f9ac03..cdcdc963ed100c6a8918a37f634a2f7182b18ef9 100644 (file)
--- a/test/CodeGen/X86/cmp.ll
+++ b/test/CodeGen/X86/cmp.ll
@@ -187,3 +187,14 @@ define i32 @test13(i32 %mask, i32 %base, i32 %intra) {
 ; CHECK: testb $8, %dil
 ; CHECK: cmovnel
 }
+
+define i32 @test14(i32 %mask, i32 %base, i32 %intra) #0 {
+  %s = lshr i32 %mask, 7
+  %tobool = icmp sgt i32 %s, -1
+  %cond = select i1 %tobool, i32 %intra, i32 %base
+  ret i32 %cond
+
+; CHECK-LABEL: test14:
+; CHECK:       shrl    $7, %edi
+; CHECK-NEXT:  cmovnsl %edx, %esi
+}