arm64: dts: rockchip: rk3399: Correct DPHY PLL clock

clk_24m --> Gate --> clk_mipidphy_ref --> Gate --> clk_dphy_pll

Change-Id: Icb5283c0854a475a5f2fc436e7d4448393b5ac95
Signed-off-by: WeiYong Bi <bivvy.bi@rock-chips.com>

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 80175f35cb974d84629c204284f592fe84579cf4..6d11ce20bfdc7582afcd8b6bb14789009b938921 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -1914,7 +1914,7 @@
                compatible = "rockchip,rk3399-mipi-dsi";
                reg = <0x0 0xff960000 0x0 0x8000>;
                interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
-               clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
+               clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>,
                         <&cru SCLK_DPHY_TX0_CFG>;
                clock-names = "ref", "pclk", "phy_cfg";
                resets = <&cru SRST_P_MIPI_DSI0>;