Cleanup TableGen subtarget emitter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165178 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/utils/TableGen/CodeGenSchedule.cpp b/utils/TableGen/CodeGenSchedule.cpp
index e54202e3f2702c5becf092886ca77e2f6f3a9832..15af7a8ae2d953c93ed8f248195ce17e3a9c141c 100644 (file)
--- a/utils/TableGen/CodeGenSchedule.cpp
+++ b/utils/TableGen/CodeGenSchedule.cpp
@@ -72,9 +72,6 @@ CodeGenSchedModels::CodeGenSchedModels(RecordKeeper &RK,
   // Infer new SchedClasses from SchedVariant.
   inferSchedClasses();
 
-  DEBUG(for (unsigned i = 0; i < SchedClasses.size(); ++i)
-          SchedClasses[i].dump(this));
-
   // Populate each CodeGenProcModel's WriteResDefs, ReadAdvanceDefs, and
   // ProcResourceDefs.
   collectProcResources();
@@ -475,7 +472,7 @@ void CodeGenSchedModels::collectSchedClasses() {
            RWI != RWE; ++RWI) {
         const CodeGenProcModel &ProcModel =
           getProcModel((*RWI)->getValueAsDef("SchedModel"));
-        dbgs() << "InstrRW on " << ProcModel.ModelName << " for " << InstName;
+        dbgs() << "InstRW on " << ProcModel.ModelName << " for " << InstName;
         IdxVec Writes;
         IdxVec Reads;
         findRWs((*RWI)->getValueAsListOfDefs("OperandReadWrites"),

diff --git a/utils/TableGen/SubtargetEmitter.cpp b/utils/TableGen/SubtargetEmitter.cpp
index 4127b379b15db4724c939f7fb1141dcd6391a9c8..f115af101625013fc55a2431ac666b92c80c76f2 100644 (file)
--- a/utils/TableGen/SubtargetEmitter.cpp
+++ b/utils/TableGen/SubtargetEmitter.cpp
@@ -11,6 +11,8 @@
 //
 //===----------------------------------------------------------------------===//
 
+#define DEBUG_TYPE "subtarget-emitter"
+
 #include "CodeGenTarget.h"
 #include "CodeGenSchedule.h"
 #include "llvm/ADT/StringExtras.h"
@@ -769,6 +771,8 @@ void SubtargetEmitter::GenSchedClassTables(const CodeGenProcModel &ProcModel,
   std::vector<MCSchedClassDesc> &SCTab = SchedTables.ProcSchedClasses.back();
   for (CodeGenSchedModels::SchedClassIter SCI = SchedModels.schedClassBegin(),
          SCE = SchedModels.schedClassEnd(); SCI != SCE; ++SCI) {
+    DEBUG(SCI->dump(&SchedModels));
+
     SCTab.resize(SCTab.size() + 1);
     MCSchedClassDesc &SCDesc = SCTab.back();
     // SCDesc.Name is guarded by NDEBUG
@@ -817,8 +821,8 @@ void SubtargetEmitter::GenSchedClassTables(const CodeGenProcModel &ProcModel,
       }
     }
     else if (!SCI->InstRWs.empty()) {
-      assert(SCI->Writes.empty() && SCI->Reads.empty() &&
-             "InstRW class should not have its own ReadWrites");
+      // This class may have a default ReadWrite list which can be overriden by
+      // InstRW definitions.
       Record *RWDef = 0;
       for (RecIter RWI = SCI->InstRWs.begin(), RWE = SCI->InstRWs.end();
            RWI != RWE; ++RWI) {