drm/nouveau/disp/dp: fix some tx_pu mishandling
authorBen Skeggs <bskeggs@redhat.com>
Fri, 21 Aug 2015 02:50:07 +0000 (12:50 +1000)
committerBen Skeggs <bskeggs@redhat.com>
Fri, 28 Aug 2015 02:40:05 +0000 (12:40 +1000)
We only need to mask 0x0f on GM2xx, and want to keep the higher bits on
earlier cards.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf110.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm204.c
drivers/gpu/drm/nouveau/nvkm/subdev/bios/dp.c

index 8918da7ffdf25fd6f23cc287bf464e61a00ed1a7..2982ebf1affd1417f5f2e18d5e7f770a7a753f93 100644 (file)
@@ -125,7 +125,7 @@ g94_sor_dp_drv_ctl(struct nvkm_output_dp *outp, int ln, int vs, int pe, int pc)
                data[2] = (data[2] & ~0x0000ff00) | (ocfg.tx_pu << 8);
        nv_wr32(priv, 0x61c118 + loff, data[0] | (ocfg.dc << shift));
        nv_wr32(priv, 0x61c120 + loff, data[1] | (ocfg.pe << shift));
-       nv_wr32(priv, 0x61c130 + loff, data[2] | (ocfg.tx_pu << 8));
+       nv_wr32(priv, 0x61c130 + loff, data[2]);
        return 0;
 }
 
index 52fbe4880e13a2c81a7457fa799d2c19a52407f8..2107e314a1171423275c8fbbc547d25ec8b39b83 100644 (file)
@@ -102,7 +102,7 @@ gf110_sor_dp_drv_ctl(struct nvkm_output_dp *outp,
                data[2] = (data[2] & ~0x0000ff00) | (ocfg.tx_pu << 8);
        nv_wr32(priv, 0x61c118 + loff, data[0] | (ocfg.dc << shift));
        nv_wr32(priv, 0x61c120 + loff, data[1] | (ocfg.pe << shift));
-       nv_wr32(priv, 0x61c130 + loff, data[2] | (ocfg.tx_pu << 8));
+       nv_wr32(priv, 0x61c130 + loff, data[2]);
        data[3] = nv_rd32(priv, 0x61c13c + loff) & ~(0x000000ff << shift);
        nv_wr32(priv, 0x61c13c + loff, data[3] | (ocfg.pc << shift));
        return 0;
index 1e40dfe11319082a2e504ddbdaccd4daeff4eeab..a2706e24f5c1d58ca7557ccb46cbe9a824b0c592 100644 (file)
@@ -109,15 +109,16 @@ gm204_sor_dp_drv_ctl(struct nvkm_output_dp *outp,
                                  &ver, &hdr, &cnt, &len, &ocfg);
        if (!addr)
                return -EINVAL;
+       ocfg.tx_pu &= 0x0f;
 
        data[0] = nv_rd32(priv, 0x61c118 + loff) & ~(0x000000ff << shift);
        data[1] = nv_rd32(priv, 0x61c120 + loff) & ~(0x000000ff << shift);
        data[2] = nv_rd32(priv, 0x61c130 + loff);
-       if ((data[2] & 0x0000ff00) < (ocfg.tx_pu << 8) || ln == 0)
-               data[2] = (data[2] & ~0x0000ff00) | (ocfg.tx_pu << 8);
+       if ((data[2] & 0x00000f00) < (ocfg.tx_pu << 8) || ln == 0)
+               data[2] = (data[2] & ~0x00000f00) | (ocfg.tx_pu << 8);
        nv_wr32(priv, 0x61c118 + loff, data[0] | (ocfg.dc << shift));
        nv_wr32(priv, 0x61c120 + loff, data[1] | (ocfg.pe << shift));
-       nv_wr32(priv, 0x61c130 + loff, data[2] | (ocfg.tx_pu << 8));
+       nv_wr32(priv, 0x61c130 + loff, data[2]);
        data[3] = nv_rd32(priv, 0x61c13c + loff) & ~(0x000000ff << shift);
        nv_wr32(priv, 0x61c13c + loff, data[3] | (ocfg.pc << shift));
        return 0;
index 20975d38542ccd156ea3e03d7ac8eb4520540491..dee047bbfd30dcf6c4673ed96944ab1c589e9924 100644 (file)
@@ -178,7 +178,7 @@ nvbios_dpcfg_parse(struct nvkm_bios *bios, u16 outp, u8 idx,
                        info->pc    = nv_ro08(bios, data + 0x00);
                        info->dc    = nv_ro08(bios, data + 0x01);
                        info->pe    = nv_ro08(bios, data + 0x02);
-                       info->tx_pu = nv_ro08(bios, data + 0x03) & 0x0f;
+                       info->tx_pu = nv_ro08(bios, data + 0x03);
                        break;
                default:
                        data = 0x0000;