CHROMIUM: ARM: dts: rockchip: assigned parents for vop dclks

The VOP DCLK is used to generate panel clocks.

For veyron, we have decided to permanently assign vop0 for
use with HDMI and vop1 for use with eDP.

Furthermore, to allow us to generate a wide range of precise pixel clocks,
we will be dedicating the NPLL exclusively for use as the parent clock
for VOP0/HDMI.

To implement the exclusive assignment of NPLL in the kernel, we remove
the NPLL entry from all clock muxes that would otherwise be able to select
it (such as vop1).  For vop0, we remove all choices *except* NPLL.

Before booting the kernel, the bios will configure vop0 and vop1 as it
sees fit - potentially assigning NPLL to vop1 and some other PLL to vop0.

Thus, at boot it is possible that from the kernel's perspective, these
clocks are orphans.  To fix this, we explicitly assign their clock parents
to ensure that they are properly parented no matter what state they are
when the kernel boots.

Change-Id: Iafe301abcbf211246fda66519cea5fc946af97ee
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Tested-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>

diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index ae6eb55f00616012fb22ff4367b6f13db304bf8e..a2ce0b55421dfb24e2088fbb790d14b0c9c22c54 100644 (file)
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -741,16 +741,19 @@
                rockchip,grf = <&grf>;
                #clock-cells = <1>;
                #reset-cells = <1>;
-               assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
-                                 <&cru PLL_NPLL>, <&cru ACLK_CPU>,
-                                 <&cru HCLK_CPU>, <&cru PCLK_CPU>,
-                                 <&cru ACLK_PERI>, <&cru HCLK_PERI>,
-                                 <&cru PCLK_PERI>;
-               assigned-clock-rates = <594000000>, <400000000>,
+               assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>,
+                                 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
+                                  <&cru PLL_NPLL>, <&cru ACLK_CPU>,
+                                  <&cru HCLK_CPU>, <&cru PCLK_CPU>,
+                                  <&cru ACLK_PERI>, <&cru HCLK_PERI>,
+                                  <&cru PCLK_PERI>;
+               assigned-clock-rates = <0>, <0>,
+                                      <594000000>, <400000000>,
                                       <500000000>, <300000000>,
                                       <150000000>, <75000000>,
                                       <300000000>, <150000000>,
                                       <75000000>;
+               assigned-clock-parents = <&cru PLL_NPLL>, <&cru PLL_GPLL>;
        };
 
        grf: syscon@ff770000 {