OMAP: DSS2: Change remaining DISPC functions for new omap_channel argument

The following dispc functions are also changed to incorporate channel as an argument:
	-dispc_lclk_rate()
	-dispc_pclk_rate()
	-dispc_set_pol_freq()
	-dispc_set_clock_div()
	-dispc_get_clock_div()

Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
Signed-off-by: Mukund Mittal <mmittal@ti.com>
Signed-off-by: Samreen <samreen@ti.com>
Signed-off-by: Archit Taneja <archit@ti.com>
[tomi.valkeinen@nokia.com: fixed trivial compile error]
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>

diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
index 7ca53c1004195a2c26f7d56e2f6f108b2cad1cff..5dfdf0ba409d4737fbee4d73b3abe353adae86eb 100644 (file)
--- a/drivers/video/omap2/dss/dispc.c
+++ b/drivers/video/omap2/dss/dispc.c
@@ -1444,12 +1444,13 @@ static void calc_dma_rotation_offset(u8 rotation, bool mirror,
        }
 }
 
-static unsigned long calc_fclk_five_taps(u16 width, u16 height,
-               u16 out_width, u16 out_height, enum omap_color_mode color_mode)
+static unsigned long calc_fclk_five_taps(enum omap_channel channel, u16 width,
+               u16 height, u16 out_width, u16 out_height,
+               enum omap_color_mode color_mode)
 {
        u32 fclk = 0;
        /* FIXME venc pclk? */
-       u64 tmp, pclk = dispc_pclk_rate();
+       u64 tmp, pclk = dispc_pclk_rate(channel);
 
        if (height > out_height) {
                /* FIXME get real display PPL */
@@ -1481,8 +1482,8 @@ static unsigned long calc_fclk_five_taps(u16 width, u16 height,
        return fclk;
 }
 
-static unsigned long calc_fclk(u16 width, u16 height,
-               u16 out_width, u16 out_height)
+static unsigned long calc_fclk(enum omap_channel channel, u16 width,
+               u16 height, u16 out_width, u16 out_height)
 {
        unsigned int hf, vf;
 
@@ -1506,7 +1507,7 @@ static unsigned long calc_fclk(u16 width, u16 height,
                vf = 1;
 
        /* FIXME venc pclk? */
-       return dispc_pclk_rate() * vf * hf;
+       return dispc_pclk_rate(channel) * vf * hf;
 }
 
 void dispc_set_channel_out(enum omap_plane plane, enum omap_channel channel_out)
@@ -1582,7 +1583,7 @@ static int _dispc_setup_plane(enum omap_plane plane,
                five_taps = height > out_height * 2;
 
                if (!five_taps) {
-                       fclk = calc_fclk(width, height,
+                       fclk = calc_fclk(OMAP_DSS_CHANNEL_LCD, width, height,
                                        out_width, out_height);
 
                        /* Try 5-tap filter if 3-tap fclk is too high */
@@ -1597,8 +1598,9 @@ static int _dispc_setup_plane(enum omap_plane plane,
                }
 
                if (five_taps)
-                       fclk = calc_fclk_five_taps(width, height,
-                                       out_width, out_height, color_mode);
+                       fclk = calc_fclk_five_taps(OMAP_DSS_CHANNEL_LCD, width,
+                                       height, out_width, out_height,
+                                       color_mode);
 
                DSSDBG("required fclk rate = %lu Hz\n", fclk);
                DSSDBG("current fclk rate = %lu Hz\n", dispc_fclk_rate());
@@ -2155,13 +2157,14 @@ void dispc_set_lcd_timings(enum omap_channel channel,
        DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
 }
 
-static void dispc_set_lcd_divisor(u16 lck_div, u16 pck_div)
+static void dispc_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
+               u16 pck_div)
 {
        BUG_ON(lck_div < 1);
        BUG_ON(pck_div < 2);
 
        enable_clocks(1);
-       dispc_write_reg(DISPC_DIVISOR(OMAP_DSS_CHANNEL_LCD),
+       dispc_write_reg(DISPC_DIVISOR(channel),
                        FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
        enable_clocks(0);
 }
@@ -2189,13 +2192,13 @@ unsigned long dispc_fclk_rate(void)
        return r;
 }
 
-unsigned long dispc_lclk_rate(void)
+unsigned long dispc_lclk_rate(enum omap_channel channel)
 {
        int lcd;
        unsigned long r;
        u32 l;
 
-       l = dispc_read_reg(DISPC_DIVISOR(OMAP_DSS_CHANNEL_LCD));
+       l = dispc_read_reg(DISPC_DIVISOR(channel));
 
        lcd = FLD_GET(l, 23, 16);
 
@@ -2204,13 +2207,13 @@ unsigned long dispc_lclk_rate(void)
        return r / lcd;
 }
 
-unsigned long dispc_pclk_rate(void)
+unsigned long dispc_pclk_rate(enum omap_channel channel)
 {
        int lcd, pcd;
        unsigned long r;
        u32 l;
 
-       l = dispc_read_reg(DISPC_DIVISOR(OMAP_DSS_CHANNEL_LCD));
+       l = dispc_read_reg(DISPC_DIVISOR(channel));
 
        lcd = FLD_GET(l, 23, 16);
        pcd = FLD_GET(l, 7, 0);
@@ -2235,8 +2238,10 @@ void dispc_dump_clocks(struct seq_file *s)
                        "dss1_alwon_fclk" : "dsi1_pll_fclk");
 
        seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
-       seq_printf(s, "lck\t\t%-16lulck div\t%u\n", dispc_lclk_rate(), lcd);
-       seq_printf(s, "pck\t\t%-16lupck div\t%u\n", dispc_pclk_rate(), pcd);
+       seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
+                       dispc_lclk_rate(OMAP_DSS_CHANNEL_LCD), lcd);
+       seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
+                       dispc_pclk_rate(OMAP_DSS_CHANNEL_LCD), pcd);
 
        enable_clocks(0);
 }
@@ -2428,8 +2433,8 @@ void dispc_dump_regs(struct seq_file *s)
 #undef DUMPREG
 }
 
-static void _dispc_set_pol_freq(bool onoff, bool rf, bool ieo, bool ipc,
-                               bool ihs, bool ivs, u8 acbi, u8 acb)
+static void _dispc_set_pol_freq(enum omap_channel channel, bool onoff, bool rf,
+               bool ieo, bool ipc, bool ihs, bool ivs, u8 acbi, u8 acb)
 {
        u32 l = 0;
 
@@ -2446,13 +2451,14 @@ static void _dispc_set_pol_freq(bool onoff, bool rf, bool ieo, bool ipc,
        l |= FLD_VAL(acb, 7, 0);
 
        enable_clocks(1);
-       dispc_write_reg(DISPC_POL_FREQ(OMAP_DSS_CHANNEL_LCD), l);
+       dispc_write_reg(DISPC_POL_FREQ(channel), l);
        enable_clocks(0);
 }
 
-void dispc_set_pol_freq(enum omap_panel_config config, u8 acbi, u8 acb)
+void dispc_set_pol_freq(enum omap_channel channel,
+               enum omap_panel_config config, u8 acbi, u8 acb)
 {
-       _dispc_set_pol_freq((config & OMAP_DSS_LCD_ONOFF) != 0,
+       _dispc_set_pol_freq(channel, (config & OMAP_DSS_LCD_ONOFF) != 0,
                        (config & OMAP_DSS_LCD_RF) != 0,
                        (config & OMAP_DSS_LCD_IEO) != 0,
                        (config & OMAP_DSS_LCD_IPC) != 0,
@@ -2521,24 +2527,26 @@ int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
        return 0;
 }
 
-int dispc_set_clock_div(struct dispc_clock_info *cinfo)
+int dispc_set_clock_div(enum omap_channel channel,
+               struct dispc_clock_info *cinfo)
 {
        DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
        DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
 
-       dispc_set_lcd_divisor(cinfo->lck_div, cinfo->pck_div);
+       dispc_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
 
        return 0;
 }
 
-int dispc_get_clock_div(struct dispc_clock_info *cinfo)
+int dispc_get_clock_div(enum omap_channel channel,
+               struct dispc_clock_info *cinfo)
 {
        unsigned long fck;
 
        fck = dispc_fclk_rate();
 
-       cinfo->lck_div = REG_GET(DISPC_DIVISOR(OMAP_DSS_CHANNEL_LCD), 23, 16);
-       cinfo->pck_div = REG_GET(DISPC_DIVISOR(OMAP_DSS_CHANNEL_LCD), 7, 0);
+       cinfo->lck_div = REG_GET(DISPC_DIVISOR(channel), 23, 16);
+       cinfo->pck_div = REG_GET(DISPC_DIVISOR(channel), 7, 0);
 
        cinfo->lck = fck / cinfo->lck_div;
        cinfo->pck = cinfo->lck / cinfo->pck_div;

diff --git a/drivers/video/omap2/dss/dpi.c b/drivers/video/omap2/dss/dpi.c
index 08b497f924bbcebf2b7fd178ff2bfb23215edf89..8c61e87629b39fd5bd3fb90a72b8026863a54925 100644 (file)
--- a/drivers/video/omap2/dss/dpi.c
+++ b/drivers/video/omap2/dss/dpi.c
@@ -40,8 +40,9 @@ static struct {
 } dpi;
 
 #ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
-static int dpi_set_dsi_clk(bool is_tft, unsigned long pck_req,
-               unsigned long *fck, int *lck_div, int *pck_div)
+static int dpi_set_dsi_clk(struct omap_dss_device *dssdev, bool is_tft,
+               unsigned long pck_req, unsigned long *fck, int *lck_div,
+               int *pck_div)
 {
        struct dsi_clock_info dsi_cinfo;
        struct dispc_clock_info dispc_cinfo;
@@ -58,7 +59,7 @@ static int dpi_set_dsi_clk(bool is_tft, unsigned long pck_req,
 
        dss_select_dispc_clk_source(DSS_SRC_DSI1_PLL_FCLK);
 
-       r = dispc_set_clock_div(&dispc_cinfo);
+       r = dispc_set_clock_div(dssdev->manager->id, &dispc_cinfo);
        if (r)
                return r;
 
@@ -69,8 +70,9 @@ static int dpi_set_dsi_clk(bool is_tft, unsigned long pck_req,
        return 0;
 }
 #else
-static int dpi_set_dispc_clk(bool is_tft, unsigned long pck_req,
-               unsigned long *fck, int *lck_div, int *pck_div)
+static int dpi_set_dispc_clk(struct omap_dss_device *dssdev, bool is_tft,
+               unsigned long pck_req, unsigned long *fck, int *lck_div,
+               int *pck_div)
 {
        struct dss_clock_info dss_cinfo;
        struct dispc_clock_info dispc_cinfo;
@@ -84,7 +86,7 @@ static int dpi_set_dispc_clk(bool is_tft, unsigned long pck_req,
        if (r)
                return r;
 
-       r = dispc_set_clock_div(&dispc_cinfo);
+       r = dispc_set_clock_div(dssdev->manager->id, &dispc_cinfo);
        if (r)
                return r;
 
@@ -107,17 +109,17 @@ static int dpi_set_mode(struct omap_dss_device *dssdev)
 
        dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
 
-       dispc_set_pol_freq(dssdev->panel.config, dssdev->panel.acbi,
-                       dssdev->panel.acb);
+       dispc_set_pol_freq(dssdev->manager->id, dssdev->panel.config,
+                       dssdev->panel.acbi, dssdev->panel.acb);
 
        is_tft = (dssdev->panel.config & OMAP_DSS_LCD_TFT) != 0;
 
 #ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
-       r = dpi_set_dsi_clk(is_tft, t->pixel_clock * 1000,
-                       &fck, &lck_div, &pck_div);
+       r = dpi_set_dsi_clk(dssdev, is_tft, t->pixel_clock * 1000, &fck,
+                       &lck_div, &pck_div);
 #else
-       r = dpi_set_dispc_clk(is_tft, t->pixel_clock * 1000,
-                       &fck, &lck_div, &pck_div);
+       r = dpi_set_dispc_clk(dssdev, is_tft, t->pixel_clock * 1000, &fck,
+                       &lck_div, &pck_div);
 #endif
        if (r)
                goto err0;

diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c
index acd36cad8445f68a5f610e2794b3956021bd760d..ddf3a05608228ac58c83f0c3246a43631a202e08 100644 (file)
--- a/drivers/video/omap2/dss/dsi.c
+++ b/drivers/video/omap2/dss/dsi.c
@@ -792,7 +792,8 @@ static int dsi_pll_power(enum dsi_pll_power_state state)
 }
 
 /* calculate clock rates using dividers in cinfo */
-static int dsi_calc_clock_rates(struct dsi_clock_info *cinfo)
+static int dsi_calc_clock_rates(struct omap_dss_device *dssdev,
+               struct dsi_clock_info *cinfo)
 {
        if (cinfo->regn == 0 || cinfo->regn > REGN_MAX)
                return -EINVAL;
@@ -812,7 +813,7 @@ static int dsi_calc_clock_rates(struct dsi_clock_info *cinfo)
                 * with DSS2_FCK source also */
                cinfo->highfreq = 0;
        } else {
-               cinfo->clkin = dispc_pclk_rate();
+               cinfo->clkin = dispc_pclk_rate(dssdev->manager->id);
 
                if (cinfo->clkin < 32000000)
                        cinfo->highfreq = 0;
@@ -1206,8 +1207,8 @@ void dsi_dump_clocks(struct seq_file *s)
 
        seq_printf(s,   "VP_CLK\t\t%lu\n"
                        "VP_PCLK\t\t%lu\n",
-                       dispc_lclk_rate(),
-                       dispc_pclk_rate());
+                       dispc_lclk_rate(OMAP_DSS_CHANNEL_LCD),
+                       dispc_pclk_rate(OMAP_DSS_CHANNEL_LCD));
 
        enable_clocks(0);
 }
@@ -2989,7 +2990,7 @@ static int dsi_configure_dsi_clocks(struct omap_dss_device *dssdev)
        cinfo.regm  = dssdev->phy.dsi.div.regm;
        cinfo.regm3 = dssdev->phy.dsi.div.regm3;
        cinfo.regm4 = dssdev->phy.dsi.div.regm4;
-       r = dsi_calc_clock_rates(&cinfo);
+       r = dsi_calc_clock_rates(dssdev, &cinfo);
        if (r) {
                DSSERR("Failed to calc dsi clocks\n");
                return r;
@@ -3021,7 +3022,7 @@ static int dsi_configure_dispc_clocks(struct omap_dss_device *dssdev)
                return r;
        }
 
-       r = dispc_set_clock_div(&dispc_cinfo);
+       r = dispc_set_clock_div(dssdev->manager->id, &dispc_cinfo);
        if (r) {
                DSSERR("Failed to set dispc clocks\n");
                return r;

diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h
index 275e29067372b49fc9f4bd4ee45971f8b9e9c5a9..3fcb8ab781af7073990263572c8195d23d60557e 100644 (file)
--- a/drivers/video/omap2/dss/dss.h
+++ b/drivers/video/omap2/dss/dss.h
@@ -393,15 +393,18 @@ bool dispc_lcd_timings_ok(struct omap_video_timings *timings);
 void dispc_set_lcd_timings(enum omap_channel channel,
                struct omap_video_timings *timings);
 unsigned long dispc_fclk_rate(void);
-unsigned long dispc_lclk_rate(void);
-unsigned long dispc_pclk_rate(void);
-void dispc_set_pol_freq(enum omap_panel_config config, u8 acbi, u8 acb);
+unsigned long dispc_lclk_rate(enum omap_channel channel);
+unsigned long dispc_pclk_rate(enum omap_channel channel);
+void dispc_set_pol_freq(enum omap_channel channel,
+               enum omap_panel_config config, u8 acbi, u8 acb);
 void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
                struct dispc_clock_info *cinfo);
 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
                struct dispc_clock_info *cinfo);
-int dispc_set_clock_div(struct dispc_clock_info *cinfo);
-int dispc_get_clock_div(struct dispc_clock_info *cinfo);
+int dispc_set_clock_div(enum omap_channel channel,
+               struct dispc_clock_info *cinfo);
+int dispc_get_clock_div(enum omap_channel channel,
+               struct dispc_clock_info *cinfo);
 
 
 /* VENC */

diff --git a/drivers/video/omap2/dss/sdi.c b/drivers/video/omap2/dss/sdi.c
index 19443b18f3da1e46fe98095eb9ae7e8ed66601d0..b64adf7dfc88b20963829245e0061c6ad1df4960 100644 (file)
--- a/drivers/video/omap2/dss/sdi.c
+++ b/drivers/video/omap2/dss/sdi.c
@@ -77,15 +77,15 @@ int omapdss_sdi_display_enable(struct omap_dss_device *dssdev)
        /* 15.5.9.1.2 */
        dssdev->panel.config |= OMAP_DSS_LCD_RF | OMAP_DSS_LCD_ONOFF;
 
-       dispc_set_pol_freq(dssdev->panel.config, dssdev->panel.acbi,
-                       dssdev->panel.acb);
+       dispc_set_pol_freq(dssdev->manager->id, dssdev->panel.config,
+                       dssdev->panel.acbi, dssdev->panel.acb);
 
        if (!sdi.skip_init) {
                r = dss_calc_clock_div(1, t->pixel_clock * 1000,
                                &dss_cinfo, &dispc_cinfo);
        } else {
                r = dss_get_clock_div(&dss_cinfo);
-               r = dispc_get_clock_div(&dispc_cinfo);
+               r = dispc_get_clock_div(dssdev->manager->id, &dispc_cinfo);
        }
 
        if (r)
@@ -112,7 +112,7 @@ int omapdss_sdi_display_enable(struct omap_dss_device *dssdev)
        if (r)
                goto err2;
 
-       r = dispc_set_clock_div(&dispc_cinfo);
+       r = dispc_set_clock_div(dssdev->manager->id, &dispc_cinfo);
        if (r)
                goto err2;