update ddr in kernel

diff --git a/arch/arm/mach-rk29/ddr.c b/arch/arm/mach-rk29/ddr.c
index ca298d4f2cf99777b16035ba772ee9720224485c..42896358579a3f48400beac9ab962a974c5facb9 100644 (file)
--- a/arch/arm/mach-rk29/ddr.c
+++ b/arch/arm/mach-rk29/ddr.c
@@ -33,16 +33,9 @@
 \r
 #include <asm/io.h>\r
 \r
-//#include <linux/module.h>\r
-//#include <linux/device.h>\r
-//#include <linux/err.h>\r
+// save_sp ±ØÐ붨ÒåΪ¾²Ì¬È«¾Ö±äÁ¿\r
 \r
-\r
-\r
-unsigned long save_sp;\r
-#define DDR_SAVE_SP            do { save_sp = ddr_save_sp((SRAM_DATA_END&(~7))); } while (0)\r
-#define DDR_RESTORE_SP         do { ddr_save_sp(save_sp); } while (0)\r
-//unsigned long ddr_save_sp( unsigned long new_sp );\r
+static unsigned long save_sp;\r
 \r
 \r
 //CCR;                    //Controller Configuration Register                            \r
@@ -391,20 +384,6 @@ static __sramdata u32 tFAW;
 static __sramdata u32 tXS;\r
 static __sramdata u32 tXP;\r
 \r
-#if 0\r
-asm(   \r
-"      .section \".sram.text\",\"ax\"\n"       \r
-"      .align\n"\r
-"      .type   ddr_save_sp, #function\n"\r
-"               .global ddr_save_sp\n"\r
-"ddr_save_sp:\n"\r
-"      mov r1,sp\n"    \r
-"      mov sp,r0\n"    \r
-"      mov r0,r1\n"    \r
-"      mov pc,lr\n"\r
-"      .previous"\r
-);\r
-#endif\r
 \r
 /****************************************************************************\r
 ÄÚ²¿sram µÄus ÑÓʱº¯Êý\r
@@ -521,7 +500,6 @@ void __sramfunc EnterDDRSelfRefresh(void)
 /****************************************************************/\r
 void __sramfunc ExitDDRSelfRefresh(void)\r
 {\r
-    volatile u32 n;\r
 \r
     pDDR_Reg->DCR = (pDDR_Reg->DCR & (~((0x1<<13) | (0xF<<27) | (0x1<<31)))) | ((0x1<<13) | (0x7<<27) | (0x1<<31)); //exit\r
     delayus(10); //wait for exit self refresh dll lock\r
@@ -530,7 +508,6 @@ void __sramfunc ExitDDRSelfRefresh(void)
     pSCU_Reg->CRU_SOFTRST_CON[0] &= ~(0x1F<<19);\r
     delayus(100); \r
     //pDDR_Reg->CCR |= DTT;\r
-    n = pDDR_Reg->CCR;\r
     delayus(100);\r
     pDDR_Reg->CCR |= HOSTEN;  //enable host port\r
 }\r
@@ -1031,11 +1008,11 @@ void DDR_ChangeFreq(u32 DDRoldMHz, u32 DDRnewMHz)
 \r
     DDRPreUpdateRef(DDRnewMHz);\r
     DDRPreUpdateTiming(DDRnewMHz);     \r
-    DDR_SAVE_SP;\r
+    DDR_SAVE_SP(save_sp);\r
     flush_cache_all();      // 20100615,HSL@RK.\r
     __cpuc_flush_user_all();\r
     ChangeDDRFreqInSram(DDRoldMHz, DDRnewMHz);\r
-    DDR_RESTORE_SP;\r
+    DDR_RESTORE_SP(save_sp);\r
 }\r
 \r
 ////////////////////////////////////////////////////////////////////////////////////\r
@@ -1125,42 +1102,22 @@ n=temp[1024*3];
 barrier();\r
 \r
 \r
-#if 0\r
-       n = * (volatile u32 *)SRAM_CODE_OFFSET;\r
-       n = * (volatile u32 *)(SRAM_CODE_OFFSET + 4096);\r
-       n = * (volatile u32 *)(SRAM_CODE_OFFSET + 8192);\r
-       n = * (volatile u32 *)(SRAM_CODE_OFFSET + 12288);\r
-#endif\r
 \r
 #endif\r
        n= pDDR_Reg->CCR;\r
        n= pSCU_Reg->CRU_SOFTRST_CON[0];\r
-      //       flush_cache_all();      // 20100615,HSL@RK.\r
-       //__cpuc_flush_kern_all();\r
-       //__cpuc_flush_user_all();\r
-       //barrier();\r
-       dsb();//dmb();\r
+       dsb();\r
          \r
-     //  printk("do_selfrefreshtest tlb \n");\r
        DDR_EnterSelfRefresh();\r
-       //delayus(100000000);\r
-       //delayus(1000*1000*100);\r
        DDR_ExitSelfRefresh();\r
-       dsb(); //dmb();\r
-#if 1\r
-       delayus(1);\r
-       delayus(1);\r
-       delayus(1);\r
-       delayus(1);\r
-\r
-#endif\r
+       dsb(); \r
 }\r
 \r
 static void selfrefreshtest(void)\r
 {\r
-       DDR_SAVE_SP;\r
+       DDR_SAVE_SP(save_sp);\r
        do_selfrefreshtest();\r
-       DDR_RESTORE_SP;\r
+       DDR_RESTORE_SP(save_sp);\r
 }\r
 \r
 static void changefreqtest(u32 DDRnewMHz)\r
@@ -1173,12 +1130,12 @@ static void changefreqtest(u32 DDRnewMHz)
     MHz =  Hz /1000000; // PLLGetDDRFreq()/1000;\r
     DDRPreUpdateRef(DDRnewMHz);\r
     DDRPreUpdateTiming(DDRnewMHz);     \r
-    DDR_SAVE_SP;\r
+    DDR_SAVE_SP(save_sp);\r
     flush_cache_all();      // 20100615,HSL@RK.\r
     __cpuc_flush_user_all();\r
     ChangeDDRFreqInSram(MHz, DDRnewMHz);\r
     DDRDLLSetMode(DLL_BYPASS,DDRnewMHz);\r
-    DDR_RESTORE_SP;\r
+    DDR_RESTORE_SP(save_sp);\r
 }\r
 \r
 #ifdef CONFIG_HAS_EARLYSUSPEND\r
@@ -1280,39 +1237,13 @@ void __sramfunc ddr_resume(void)
 static int __init ddr_update_freq(void)\r
 {\r
 \r
-  // DDR_Init();\r
+  DDR_Init();\r
    \r
 #if 0 //#ifdef CONFIG_HAS_EARLYSUSPEND\r
        register_early_suspend(&early_suspend_info);\r
 #endif\r
 \r
 \r
-#if 0\r
-   unsigned long flags , i;\r
-   printk("DDR enter self-refresh!\n");\r
-   \r
-   local_irq_save(flags);\r
- \r
-   DDR_Init();\r
-   //DDR_ChangeFreq(333); \r
-  \r
-   for (i=0;i<1000000;i++)\r
-   {\r
-       printk("%d ", i);\r
-       if(!(i%50))\r
-               printk("\n");\r
-\r
-       selfrefreshtest();\r
-       //changefreqtest(200);  \r
-       //delayus(10000000);\r
-       //changefreqtest(333);\r
-   }\r
-   \r
-   local_irq_restore(flags);\r
-   \r
-   printk("DDR exit self-refresh!\n");\r
-   \r
-#endif\r
    \r
 \r
    return 0;\r