From: Joerg Sonnenberger <joerg@bec.de>
Date: Tue, 22 Feb 2011 20:40:09 +0000 (+0000)
Subject: Use the same (%dx) hack for in[bwl] as for out[bwl].
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=00743c2218ff3f0f4edce972e2d88893a19e6ef8;p=oota-llvm.git

Use the same (%dx) hack for in[bwl] as for out[bwl].


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126244 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/X86/AsmParser/X86AsmParser.cpp b/lib/Target/X86/AsmParser/X86AsmParser.cpp
index 1cac07a0e10..8fe549ba312 100644
--- a/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ b/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -775,6 +775,19 @@ ParseInstruction(StringRef Name, SMLoc NameLoc,
       delete &Op;
     }
   }
+  // Same hack for "in[bwl]? (%dx), %al" -> "inb %dx, %al".
+  if ((Name == "inb" || Name == "inw" || Name == "inl" || Name == "in") &&
+      Operands.size() == 3) {
+    X86Operand &Op = *(X86Operand*)Operands.begin()[1];
+    if (Op.isMem() && Op.Mem.SegReg == 0 &&
+        isa<MCConstantExpr>(Op.Mem.Disp) &&
+        cast<MCConstantExpr>(Op.Mem.Disp)->getValue() == 0 &&
+        Op.Mem.BaseReg == MatchRegisterName("dx") && Op.Mem.IndexReg == 0) {
+      SMLoc Loc = Op.getEndLoc();
+      Operands.begin()[1] = X86Operand::CreateReg(Op.Mem.BaseReg, Loc, Loc);
+      delete &Op;
+    }
+  }
   
   // FIXME: Hack to handle recognize s{hr,ar,hl} $1, <op>.  Canonicalize to
   // "shift <op>".
diff --git a/test/MC/X86/x86-64.s b/test/MC/X86/x86-64.s
index 456c21a1c7d..ee9757fa317 100644
--- a/test/MC/X86/x86-64.s
+++ b/test/MC/X86/x86-64.s
@@ -241,13 +241,32 @@ inl	%dx
 
 // PR8114
 // CHECK: outb	%al, %dx
+// CHECK: outb	%al, %dx
+// CHECK: outw	%ax, %dx
 // CHECK: outw	%ax, %dx
 // CHECK: outl	%eax, %dx
+// CHECK: outl	%eax, %dx
+
+out	%al, (%dx)
+outb	%al, (%dx)
+out	%ax, (%dx)
+outw	%ax, (%dx)
+out	%eax, (%dx)
+outl	%eax, (%dx)
 
-out %al, (%dx)
-out %ax, (%dx)
-outl %eax, (%dx)
+// CHECK: inb	%dx, %al
+// CHECK: inb	%dx, %al
+// CHECK: inw	%dx, %ax
+// CHECK: inw	%dx, %ax
+// CHECK: inl	%dx, %eax
+// CHECK: inl	%dx, %eax
 
+in	(%dx), %al
+inb	(%dx), %al
+in	(%dx), %ax
+inw	(%dx), %ax
+in	(%dx), %eax
+inl	(%dx), %eax
 
 // rdar://8431422