From: Dan Gohman Date: Tue, 11 Mar 2008 01:59:03 +0000 (+0000) Subject: Generalize ExpandIntToFP to handle the case where the operand is legal X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=034f60ed24c53c1e37f7695965f782faec2dff2b;p=oota-llvm.git Generalize ExpandIntToFP to handle the case where the operand is legal and it's the result that requires expansion. This code is a little confusing because the TargetLoweringInfo tables for [US]INT_TO_FP use the operand type (the integer type) rather than the result type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48206 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index 087737336be..2e82b362e65 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -5366,20 +5366,25 @@ SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node, SDOperand SelectionDAGLegalize:: ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) { MVT::ValueType SourceVT = Source.getValueType(); - assert(getTypeAction(SourceVT) == Expand && - "This is not an expansion!"); + bool ExpandSource = getTypeAction(SourceVT) == Expand; if (!isSigned) { // The integer value loaded will be incorrectly if the 'sign bit' of the // incoming integer is set. To handle this, we dynamically test to see if // it is set, and, if so, add a fudge factor. - SDOperand Lo, Hi; - ExpandOp(Source, Lo, Hi); + SDOperand Hi; + if (ExpandSource) { + SDOperand Lo; + ExpandOp(Source, Lo, Hi); + Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, Lo, Hi); + } else { + // The comparison for the sign bit will use the entire operand. + Hi = Source; + } // If this is unsigned, and not supported, first perform the conversion to // signed, then adjust the result if the sign bit is set. - SDOperand SignedConv = ExpandIntToFP(true, DestTy, - DAG.getNode(ISD::BUILD_PAIR, SourceVT, Lo, Hi)); + SDOperand SignedConv = ExpandIntToFP(true, DestTy, Source); SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi, DAG.getConstant(0, Hi.getValueType()), @@ -5437,17 +5442,23 @@ ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) { // Expand the source, then glue it back together for the call. We must expand // the source in case it is shared (this pass of legalize must traverse it). - SDOperand SrcLo, SrcHi; - ExpandOp(Source, SrcLo, SrcHi); - Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, SrcLo, SrcHi); + if (ExpandSource) { + SDOperand SrcLo, SrcHi; + ExpandOp(Source, SrcLo, SrcHi); + Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, SrcLo, SrcHi); + } RTLIB::Libcall LC; if (SourceVT == MVT::i64) { if (DestTy == MVT::f32) LC = RTLIB::SINTTOFP_I64_F32; - else { - assert(DestTy == MVT::f64 && "Unknown fp value type!"); + else if (DestTy == MVT::f64) LC = RTLIB::SINTTOFP_I64_F64; + else if (DestTy == MVT::f80) + LC = RTLIB::SINTTOFP_I64_F80; + else { + assert(DestTy == MVT::ppcf128 && "Unknown fp value type!"); + LC = RTLIB::SINTTOFP_I64_PPCF128; } } else if (SourceVT == MVT::i128) { if (DestTy == MVT::f32) diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index 32787bcc75b..a224b036926 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -2380,6 +2380,10 @@ SDOperand PPCTargetLowering::LowerFP_ROUND_INREG(SDOperand Op, } SDOperand PPCTargetLowering::LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) { + // Don't handle ppc_fp128 here; let it be lowered to a libcall. + if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64) + return SDOperand(); + if (Op.getOperand(0).getValueType() == MVT::i64) { SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0)); SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Bits); diff --git a/test/CodeGen/PowerPC/int-fp-conv-0.ll b/test/CodeGen/PowerPC/int-fp-conv-0.ll new file mode 100644 index 00000000000..82a18268514 --- /dev/null +++ b/test/CodeGen/PowerPC/int-fp-conv-0.ll @@ -0,0 +1,17 @@ +; RUN: llvm-as < %s | llc -march=ppc64 > %t +; RUN: grep __floattitf %t +; RUN: grep __fixunstfti %t + +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128" +target triple = "powerpc64-apple-darwin9.2.0" + +define ppc_fp128 @foo(i128 %a) nounwind { +entry: + %tmp2829 = uitofp i128 %a to ppc_fp128 ; [#uses=1] + ret ppc_fp128 %tmp2829 +} +define i128 @boo(ppc_fp128 %a) nounwind { +entry: + %tmp2829 = fptoui ppc_fp128 %a to i128 ; [#uses=1] + ret i128 %tmp2829 +} diff --git a/test/CodeGen/PowerPC/int-fp-conv-1.ll b/test/CodeGen/PowerPC/int-fp-conv-1.ll new file mode 100644 index 00000000000..3d6667539f2 --- /dev/null +++ b/test/CodeGen/PowerPC/int-fp-conv-1.ll @@ -0,0 +1,11 @@ +; RUN: llvm-as < %s | llc -march=ppc64 | grep __floatditf + +define i64 @__fixunstfdi(ppc_fp128 %a) nounwind { +entry: + %tmp1213 = uitofp i64 0 to ppc_fp128 ; [#uses=1] + %tmp15 = sub ppc_fp128 %a, %tmp1213 ; [#uses=1] + %tmp2829 = fptoui ppc_fp128 %tmp15 to i32 ; [#uses=1] + %tmp282930 = zext i32 %tmp2829 to i64 ; [#uses=1] + %tmp32 = add i64 %tmp282930, 0 ; [#uses=1] + ret i64 %tmp32 +} diff --git a/test/CodeGen/PowerPC/int-fp-conv.ll b/test/CodeGen/PowerPC/int-fp-conv.ll deleted file mode 100644 index 82a18268514..00000000000 --- a/test/CodeGen/PowerPC/int-fp-conv.ll +++ /dev/null @@ -1,17 +0,0 @@ -; RUN: llvm-as < %s | llc -march=ppc64 > %t -; RUN: grep __floattitf %t -; RUN: grep __fixunstfti %t - -target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128" -target triple = "powerpc64-apple-darwin9.2.0" - -define ppc_fp128 @foo(i128 %a) nounwind { -entry: - %tmp2829 = uitofp i128 %a to ppc_fp128 ; [#uses=1] - ret ppc_fp128 %tmp2829 -} -define i128 @boo(ppc_fp128 %a) nounwind { -entry: - %tmp2829 = fptoui ppc_fp128 %a to i128 ; [#uses=1] - ret i128 %tmp2829 -}