From: Bob Wilson Date: Wed, 28 Oct 2009 00:37:03 +0000 (+0000) Subject: Add an indirect branch pattern for ARM. Testcase will be coming soon. X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=04ea6e5150dd02fd60513a3d9fd1407aea350c02;p=oota-llvm.git Add an indirect branch pattern for ARM. Testcase will be coming soon. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85355 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index 3bbf6aee481..c044f717f39 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -657,6 +657,16 @@ let isReturn = 1, isTerminator = 1, isBarrier = 1 in let Inst{27-20} = 0b00010010; } +// Indirect branches +let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { + def BRIND : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx $dst", + [(brind GPR:$dst)]> { + let Inst{7-4} = 0b0001; + let Inst{19-8} = 0b111111111111; + let Inst{27-20} = 0b00010010; + } +} + // FIXME: remove when we have a way to marking a MI with these properties. // FIXME: Should pc be an implicit operand like PICADD, etc? let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,