From: Arun Siluvery <arun.siluvery@linux.intel.com>
Date: Tue, 14 Jul 2015 14:01:27 +0000 (+0100)
Subject: drm/i915: Enable WA batch buffers for Gen9
X-Git-Tag: firefly_0821_release~176^2~721^2~33^2~227
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=0504cffc7b128dc4bd751821abe7c47203d7bd62;p=firefly-linux-kernel-4.4.55.git

drm/i915: Enable WA batch buffers for Gen9

This patch only enables support for Gen9, the actual WA will be
initialized in subsequent patches.

The WARN that we use to warn user if WA batch support is not available
for a particular Gen is replaced with DRM_ERROR as warning here doesn't
really add much value.

v2: include all infrastructure bits in this patch so that subsequent
changes only correspond the WA added (Chris)

v3: use updated macro.

Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index d7f66d289970..f1a382c685a5 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1248,6 +1248,35 @@ static int gen8_init_perctx_bb(struct intel_engine_cs *ring,
 	return wa_ctx_end(wa_ctx, *offset = index, 1);
 }
 
+static int gen9_init_indirectctx_bb(struct intel_engine_cs *ring,
+				    struct i915_wa_ctx_bb *wa_ctx,
+				    uint32_t *const batch,
+				    uint32_t *offset)
+{
+	uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
+
+	/* FIXME: Replace me with WA */
+	wa_ctx_emit(batch, index, MI_NOOP);
+
+	/* Pad to end of cacheline */
+	while (index % CACHELINE_DWORDS)
+		wa_ctx_emit(batch, index, MI_NOOP);
+
+	return wa_ctx_end(wa_ctx, *offset = index, CACHELINE_DWORDS);
+}
+
+static int gen9_init_perctx_bb(struct intel_engine_cs *ring,
+			       struct i915_wa_ctx_bb *wa_ctx,
+			       uint32_t *const batch,
+			       uint32_t *offset)
+{
+	uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
+
+	wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END);
+
+	return wa_ctx_end(wa_ctx, *offset = index, 1);
+}
+
 static int lrc_setup_wa_ctx_obj(struct intel_engine_cs *ring, u32 size)
 {
 	int ret;
@@ -1289,10 +1318,11 @@ static int intel_init_workaround_bb(struct intel_engine_cs *ring)
 	WARN_ON(ring->id != RCS);
 
 	/* update this when WA for higher Gen are added */
-	if (WARN(INTEL_INFO(ring->dev)->gen > 8,
-		 "WA batch buffer is not initialized for Gen%d\n",
-		 INTEL_INFO(ring->dev)->gen))
+	if (INTEL_INFO(ring->dev)->gen > 9) {
+		DRM_ERROR("WA batch buffer is not initialized for Gen%d\n",
+			  INTEL_INFO(ring->dev)->gen);
 		return 0;
+	}
 
 	/* some WA perform writes to scratch page, ensure it is valid */
 	if (ring->scratch.obj == NULL) {
@@ -1324,6 +1354,20 @@ static int intel_init_workaround_bb(struct intel_engine_cs *ring)
 					  &offset);
 		if (ret)
 			goto out;
+	} else if (INTEL_INFO(ring->dev)->gen == 9) {
+		ret = gen9_init_indirectctx_bb(ring,
+					       &wa_ctx->indirect_ctx,
+					       batch,
+					       &offset);
+		if (ret)
+			goto out;
+
+		ret = gen9_init_perctx_bb(ring,
+					  &wa_ctx->per_ctx,
+					  batch,
+					  &offset);
+		if (ret)
+			goto out;
 	}
 
 out: