From: Arnd Bergmann Date: Thu, 28 Mar 2013 11:25:51 +0000 (+0100) Subject: Merge branch 'prima2/multiplatform' into next/multiplatform X-Git-Tag: firefly_0821_release~3680^2~604^2~16 X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=063ab6daeb2ba5ef8f47c3fc04a749936c62d5bb;p=firefly-linux-kernel-4.4.55.git Merge branch 'prima2/multiplatform' into next/multiplatform This series enables multiplatform support on the SIRF prima2/marco/atlas6 platform. The code was already quite tidy, so this is a relatively simple change, and it follows similar changes we made to other ARMv7 based platforms recently. * prima2/multiplatform: ARM: sirf: enable support in multi_v7_defconfig ARM: sirf: enable multiplatform support ARM: sirf: use clocksource_of infrastructure ARM: sirf: move debug-macro.S to include/debug/sirf.S ARM: sirf: enable sparse IRQ ARM: sirf: move irq driver to drivers/irqchip ARM: sirf: fix prima2 interrupt lookup pinctrl: sirf: convert to linear irq domain clocksource: make CLOCKSOURCE_OF_DECLARE type safe ARM/dts: prima2: add .dtsi for atlas6 and .dts for atla6-evb board arm: prima2: add new SiRFatlas6 machine in common board ARM: smp_twd: convert to use CLKSRC_OF init clocksource: tegra20: use the device_node pointer passed to init clocksource: pass DT node pointer to init functions clocksource: add empty version of clocksource_of_init Conflicts: arch/arm/configs/multi_v7_defconfig arch/arm/mach-spear/spear13xx.c Tested-by: Barry Song Signed-off-by: Arnd Bergmann --- 063ab6daeb2ba5ef8f47c3fc04a749936c62d5bb diff --cc arch/arm/Kconfig.debug index 5115ff9e8a2a,a69334d7f2b3..fd17127b4188 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@@ -605,9 -590,9 +605,10 @@@ config DEBUG_LL_INCLUD DEBUG_IMX6Q_UART default "debug/highbank.S" if DEBUG_HIGHBANK_UART default "debug/mvebu.S" if DEBUG_MVEBU_UART + default "debug/nomadik.S" if DEBUG_NOMADIK_UART default "debug/omap2plus.S" if DEBUG_OMAP2PLUS_UART default "debug/picoxcell.S" if DEBUG_PICOXCELL_UART + default "debug/sirf.S" if DEBUG_SIRFPRIMA2_UART1 || DEBUG_SIRFMARCO_UART1 default "debug/socfpga.S" if DEBUG_SOCFPGA_UART default "debug/sunxi.S" if DEBUG_SUNXI_UART0 || DEBUG_SUNXI_UART1 default "debug/vexpress.S" if DEBUG_VEXPRESS_UART0_DETECT || \ diff --cc arch/arm/configs/multi_v7_defconfig index 3bf0c543216a,44ec305c2c91..e3f2f6a5709b --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@@ -44,9 -41,10 +47,11 @@@ CONFIG_IPMI_HANDLER= CONFIG_IPMI_SI=y CONFIG_I2C=y CONFIG_I2C_DESIGNWARE_PLATFORM=y + CONFIG_I2C_SIRF=y CONFIG_SPI=y CONFIG_SPI_PL022=y + CONFIG_SPI_SIRF=y +CONFIG_GPIO_PL061=y CONFIG_FB=y CONFIG_FB_ARMCLCD=y CONFIG_FRAMEBUFFER_CONSOLE=y @@@ -66,4 -63,4 +71,5 @@@ CONFIG_RTC_CLASS= CONFIG_RTC_DRV_PL031=y CONFIG_DMADEVICES=y CONFIG_PL330_DMA=y + CONFIG_SIRF_DMA=y +CONFIG_DW_DMAC=y diff --cc arch/arm/mach-spear/spear13xx.c index 1b97e8623472,000000000000..6dd208997176 mode 100644,000000..100644 --- a/arch/arm/mach-spear/spear13xx.c +++ b/arch/arm/mach-spear/spear13xx.c @@@ -1,184 -1,0 +1,184 @@@ +/* + * arch/arm/mach-spear13xx/spear13xx.c + * + * SPEAr13XX machines common source file + * + * Copyright (C) 2012 ST Microelectronics + * Viresh Kumar + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#define pr_fmt(fmt) "SPEAr13xx: " fmt + +#include +#include ++#include +#include +#include +#include +#include +#include - #include +#include "generic.h" +#include + +#include "spear13xx-dma.h" + +/* common dw_dma filter routine to be used by peripherals */ +bool dw_dma_filter(struct dma_chan *chan, void *slave) +{ + struct dw_dma_slave *dws = (struct dw_dma_slave *)slave; + + if (chan->device->dev == dws->dma_dev) { + chan->private = slave; + return true; + } else { + return false; + } +} + +/* ssp device registration */ +static struct dw_dma_slave ssp_dma_param[] = { + { + /* Tx */ + .cfg_hi = DWC_CFGH_DST_PER(DMA_REQ_SSP0_TX), + .cfg_lo = 0, + .src_master = DMA_MASTER_MEMORY, + .dst_master = DMA_MASTER_SSP0, + }, { + /* Rx */ + .cfg_hi = DWC_CFGH_SRC_PER(DMA_REQ_SSP0_RX), + .cfg_lo = 0, + .src_master = DMA_MASTER_SSP0, + .dst_master = DMA_MASTER_MEMORY, + } +}; + +struct pl022_ssp_controller pl022_plat_data = { + .enable_dma = 1, + .dma_filter = dw_dma_filter, + .dma_rx_param = &ssp_dma_param[1], + .dma_tx_param = &ssp_dma_param[0], +}; + +/* CF device registration */ +struct dw_dma_slave cf_dma_priv = { + .cfg_hi = 0, + .cfg_lo = 0, + .src_master = 0, + .dst_master = 0, +}; + +/* dmac device registeration */ +struct dw_dma_platform_data dmac_plat_data = { + .nr_channels = 8, + .chan_allocation_order = CHAN_ALLOCATION_DESCENDING, + .chan_priority = CHAN_PRIORITY_DESCENDING, + .block_size = 4095U, + .nr_masters = 2, + .data_width = { 3, 3, 0, 0 }, +}; + +void __init spear13xx_l2x0_init(void) +{ + /* + * 512KB (64KB/way), 8-way associativity, parity supported + * + * FIXME: 9th bit, of Auxillary Controller register must be set + * for some spear13xx devices for stable L2 operation. + * + * Enable Early BRESP, L2 prefetch for Instruction and Data, + * write alloc and 'Full line of zero' options + * + */ + + writel_relaxed(0x06, VA_L2CC_BASE + L2X0_PREFETCH_CTRL); + + /* + * Program following latencies in order to make + * SPEAr1340 work at 600 MHz + */ + writel_relaxed(0x221, VA_L2CC_BASE + L2X0_TAG_LATENCY_CTRL); + writel_relaxed(0x441, VA_L2CC_BASE + L2X0_DATA_LATENCY_CTRL); + l2x0_init(VA_L2CC_BASE, 0x70A60001, 0xfe00ffff); +} + +/* + * Following will create 16MB static virtual/physical mappings + * PHYSICAL VIRTUAL + * 0xB3000000 0xFE000000 + * 0xE0000000 0xFD000000 + * 0xEC000000 0xFC000000 + * 0xED000000 0xFB000000 + */ +struct map_desc spear13xx_io_desc[] __initdata = { + { + .virtual = (unsigned long)VA_PERIP_GRP2_BASE, + .pfn = __phys_to_pfn(PERIP_GRP2_BASE), + .length = SZ_16M, + .type = MT_DEVICE + }, { + .virtual = (unsigned long)VA_PERIP_GRP1_BASE, + .pfn = __phys_to_pfn(PERIP_GRP1_BASE), + .length = SZ_16M, + .type = MT_DEVICE + }, { + .virtual = (unsigned long)VA_A9SM_AND_MPMC_BASE, + .pfn = __phys_to_pfn(A9SM_AND_MPMC_BASE), + .length = SZ_16M, + .type = MT_DEVICE + }, { + .virtual = (unsigned long)VA_L2CC_BASE, + .pfn = __phys_to_pfn(L2CC_BASE), + .length = SZ_4K, + .type = MT_DEVICE + }, +}; + +/* This will create static memory mapping for selected devices */ +void __init spear13xx_map_io(void) +{ + iotable_init(spear13xx_io_desc, ARRAY_SIZE(spear13xx_io_desc)); +} + +static void __init spear13xx_clk_init(void) +{ + if (of_machine_is_compatible("st,spear1310")) + spear1310_clk_init(VA_MISC_BASE, VA_SPEAR1310_RAS_BASE); + else if (of_machine_is_compatible("st,spear1340")) + spear1340_clk_init(VA_MISC_BASE); + else + pr_err("%s: Unknown machine\n", __func__); +} + +void __init spear13xx_timer_init(void) +{ + char pclk_name[] = "osc_24m_clk"; + struct clk *gpt_clk, *pclk; + + spear13xx_clk_init(); + + /* get the system timer clock */ + gpt_clk = clk_get_sys("gpt0", NULL); + if (IS_ERR(gpt_clk)) { + pr_err("%s:couldn't get clk for gpt\n", __func__); + BUG(); + } + + /* get the suitable parent clock for timer*/ + pclk = clk_get(NULL, pclk_name); + if (IS_ERR(pclk)) { + pr_err("%s:couldn't get %s as parent for gpt\n", __func__, + pclk_name); + BUG(); + } + + clk_set_parent(gpt_clk, pclk); + clk_put(gpt_clk); + clk_put(pclk); + + spear_setup_of_timer(); - twd_local_timer_of_register(); ++ clocksource_of_init(); +}