From: Jeff Cohen <jeffc@jolt-lang.org>
Date: Sat, 12 Nov 2005 00:59:01 +0000 (+0000)
Subject: Fix operator precedence bug caught by VC++.
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=06d9b4ab24d1a6aa94fd0c6f24ab8381e1771f93;p=oota-llvm.git

Fix operator precedence bug caught by VC++.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24318 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index ca137431a00..6cd66c7c19c 100644
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -967,8 +967,8 @@ SDOperand DAGCombiner::visitAND(SDNode *N) {
   // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
   if (N1C && N0.getOpcode() == ISD::SIGN_EXTEND_INREG) {
     unsigned ExtendBits =
-    MVT::getSizeInBits(cast<VTSDNode>(N0.getOperand(1))->getVT());
-    if (ExtendBits == 64 || (N1C->getValue() & (~0ULL << ExtendBits) == 0))
+        MVT::getSizeInBits(cast<VTSDNode>(N0.getOperand(1))->getVT());
+    if (ExtendBits == 64 || ((N1C->getValue() & (~0ULL << ExtendBits)) == 0))
       return DAG.getNode(ISD::AND, VT, N0.getOperand(0), N1);
   }
   // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF