From: Jim Grosbach <grosbach@apple.com>
Date: Wed, 13 Oct 2010 22:38:23 +0000 (+0000)
Subject: Add operand encoding bits for SMC and SVC in ARM mode.
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=06ef444e5cd85264a4e6eb0059b0c2174e4bbe61;p=oota-llvm.git

Add operand encoding bits for SMC and SVC in ARM mode.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116447 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index 470550b3be8..3d4e32c3c8b 100644
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -1295,14 +1295,18 @@ def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
 // Secure Monitor Call is a system instruction -- for disassembly only
 def SMC : ABI<0b0001, (outs), (ins i32imm:$opt), NoItinerary, "smc", "\t$opt",
               [/* For disassembly only; pattern left blank */]> {
-  let Inst{23-20} = 0b0110;
-  let Inst{7-4} = 0b0111;
+  bits<4> opt;
+  let Inst{23-4} = 0b01100000000000000111;
+  let Inst{3-0} = opt;
 }
 
 // Supervisor Call (Software Interrupt) -- for disassembly only
 let isCall = 1 in {
 def SVC : ABI<0b1111, (outs), (ins i32imm:$svc), IIC_Br, "svc", "\t$svc",
-              [/* For disassembly only; pattern left blank */]>;
+              [/* For disassembly only; pattern left blank */]> {
+  bits<24> svc;
+  let Inst{23-0} = svc;
+}
 }
 
 // Store Return State is a system instruction -- for disassembly only