From: Jim Grosbach Date: Wed, 27 Oct 2010 17:52:51 +0000 (+0000) Subject: The new LDR* instruction patterns should handle the necessary encoding of X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=093177d5cde06dcb63829320f12195c32485a6d1;p=oota-llvm.git The new LDR* instruction patterns should handle the necessary encoding of operands in the TableGen'erated bits, so we don't need to do the additional magic explicitly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117461 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/ARM/ARMCodeEmitter.cpp b/lib/Target/ARM/ARMCodeEmitter.cpp index edb9c906b1f..0ff0d5142a0 100644 --- a/lib/Target/ARM/ARMCodeEmitter.cpp +++ b/lib/Target/ARM/ARMCodeEmitter.cpp @@ -946,6 +946,13 @@ void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI, // Part of binary is determined by TableGn. unsigned Binary = getBinaryCodeForInstr(MI); + // If this is an LDRi12, LDRrs, or LDRcp, nothing more needs be done. + if (MI.getOpcode() == ARM::LDRi12 || MI.getOpcode() == ARM::LDRrs + || MI.getOpcode() == ARM::LDRcp) { + emitWordLE(Binary); + return; + } + // Set the conditional execution predicate Binary |= II->getPredicate(&MI) << ARMII::CondShift;