From: Chris Lattner <sabre@nondot.org>
Date: Fri, 7 Oct 2005 06:10:46 +0000 (+0000)
Subject: Turn sdivs into udivs when we can prove the sign bits are clear.  This
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=094c8fcd14a04a3bac12eb17e7e04276ce594e11;p=oota-llvm.git

Turn sdivs into udivs when we can prove the sign bits are clear.  This
implements CodeGen/PowerPC/div-2.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23659 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 3c5219181bf..86ee932eab2 100644
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -501,6 +501,7 @@ SDOperand DAGCombiner::visitMUL(SDNode *N) {
 SDOperand DAGCombiner::visitSDIV(SDNode *N) {
   SDOperand N0 = N->getOperand(0);
   SDOperand N1 = N->getOperand(1);
+  MVT::ValueType VT = N->getValueType(0);
   ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
   ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
 
@@ -508,6 +509,15 @@ SDOperand DAGCombiner::visitSDIV(SDNode *N) {
   if (N0C && N1C && !N1C->isNullValue())
     return DAG.getConstant(N0C->getSignExtended() / N1C->getSignExtended(),
                            N->getValueType(0));
+
+  // If we know the sign bits of both operands are zero, strength reduce to a
+  // udiv instead.  Handles (X&15) /s 4 -> X&15 >> 2
+  uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
+  if (MaskedValueIsZero(N1, SignBit, TLI) &&
+      MaskedValueIsZero(N0, SignBit, TLI))
+    return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1);
+  
+  
   return SDOperand();
 }
 
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 28215ad59b5..12cfe0077f9 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -1556,6 +1556,17 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
       return N1;
     }
     break;
+  case ISD::SDIV: {
+    if (CombinerEnabled) break;
+    
+    // If we know the sign bits of both operands are zero, strength reduce to a
+    // udiv instead.  Handles (X&15) /s 4 -> X&15 >> 2
+    uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
+    if (MaskedValueIsZero(N2, SignBit, TLI) &&
+        MaskedValueIsZero(N1, SignBit, TLI))
+      return getNode(ISD::UDIV, VT, N1, N2);
+    break;
+  }   
 
   case ISD::AND:
   case ISD::OR: