From: Chris Lattner <sabre@nondot.org>
Date: Sun, 30 Dec 2007 20:55:08 +0000 (+0000)
Subject: two register machineoperands are not identical unless their subregs match.
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=0974d9a5247a1f70ab739191ce5d768488a0f8aa;p=oota-llvm.git

two register machineoperands are not identical unless their subregs match.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45455 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/CodeGen/MachineInstr.cpp b/lib/CodeGen/MachineInstr.cpp
index f54cbe7f1c8..e8f692e15f8 100644
--- a/lib/CodeGen/MachineInstr.cpp
+++ b/lib/CodeGen/MachineInstr.cpp
@@ -153,7 +153,8 @@ bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
   switch (getType()) {
   default: assert(0 && "Unrecognized operand type");
   case MachineOperand::MO_Register:
-    return getReg() == Other.getReg() && isDef() == Other.isDef();
+    return getReg() == Other.getReg() && isDef() == Other.isDef() &&
+           getSubReg() == Other.getSubReg();
   case MachineOperand::MO_Immediate:
     return getImm() == Other.getImm();
   case MachineOperand::MO_MachineBasicBlock: