From: Ahmed Bougacha <ahmed.bougacha@gmail.com>
Date: Tue, 4 Aug 2015 01:29:38 +0000 (+0000)
Subject: [AArch64] Add isel support for f16 indexed LD/ST.
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=09ae369f4f1f27bc9393dc859b356dffba7a05ce;p=oota-llvm.git

[AArch64] Add isel support for f16 indexed LD/ST.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243935 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
index 0b848fc7b39..fdf68e3a6e3 100644
--- a/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+++ b/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
@@ -1038,6 +1038,8 @@ SDNode *AArch64DAGToDAGISel::SelectIndexedLoad(SDNode *N, bool &Done) {
       // it into an i64.
       DstVT = MVT::i32;
     }
+  } else if (VT == MVT::f16) {
+    Opcode = IsPre ? AArch64::LDRHpre : AArch64::LDRHpost;
   } else if (VT == MVT::f32) {
     Opcode = IsPre ? AArch64::LDRSpre : AArch64::LDRSpost;
   } else if (VT == MVT::f64 || VT.is64BitVector()) {
diff --git a/lib/Target/AArch64/AArch64ISelLowering.cpp b/lib/Target/AArch64/AArch64ISelLowering.cpp
index 44236c74542..03a613b1691 100644
--- a/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -442,12 +442,14 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
     setIndexedLoadAction(im, MVT::i64, Legal);
     setIndexedLoadAction(im, MVT::f64, Legal);
     setIndexedLoadAction(im, MVT::f32, Legal);
+    setIndexedLoadAction(im, MVT::f16, Legal);
     setIndexedStoreAction(im, MVT::i8, Legal);
     setIndexedStoreAction(im, MVT::i16, Legal);
     setIndexedStoreAction(im, MVT::i32, Legal);
     setIndexedStoreAction(im, MVT::i64, Legal);
     setIndexedStoreAction(im, MVT::f64, Legal);
     setIndexedStoreAction(im, MVT::f32, Legal);
+    setIndexedStoreAction(im, MVT::f16, Legal);
   }
 
   // Trap.
diff --git a/test/CodeGen/AArch64/arm64-indexed-memory.ll b/test/CodeGen/AArch64/arm64-indexed-memory.ll
index b52cddf600a..b6ab9934dbc 100644
--- a/test/CodeGen/AArch64/arm64-indexed-memory.ll
+++ b/test/CodeGen/AArch64/arm64-indexed-memory.ll
@@ -81,6 +81,17 @@ define void @truncst64to8(i8** nocapture %out, i8 %index, i64 %spacing) nounwind
 }
 
 
+define void @storef16(half** %out, half %index, half %spacing) nounwind {
+; CHECK-LABEL: storef16:
+; CHECK: str h{{[0-9+]}}, [x{{[0-9+]}}], #2
+; CHECK: ret
+  %tmp = load half*, half** %out, align 2
+  %incdec.ptr = getelementptr inbounds half, half* %tmp, i64 1
+  store half %spacing, half* %tmp, align 2
+  store half* %incdec.ptr, half** %out, align 2
+  ret void
+}
+
 define void @storef32(float** nocapture %out, float %index, float %spacing) nounwind noinline ssp {
 ; CHECK-LABEL: storef32:
 ; CHECK: str s{{[0-9+]}}, [x{{[0-9+]}}], #4
@@ -125,6 +136,17 @@ define float * @pref32(float** nocapture %out, float %spacing) nounwind noinline
   ret float *%ptr
 }
 
+define half* @pref16(half** %out, half %spacing) nounwind {
+; CHECK-LABEL: pref16:
+; CHECK: ldr x0, [x0]
+; CHECK-NEXT: str h0, [x0, #6]!
+; CHECK-NEXT: ret
+  %tmp = load half*, half** %out, align 2
+  %ptr = getelementptr inbounds half, half* %tmp, i64 3
+  store half %spacing, half* %ptr, align 2
+  ret half *%ptr
+}
+
 define i64 * @pre64(i64** nocapture %out, i64 %spacing) nounwind noinline ssp {
 ; CHECK-LABEL: pre64:
 ; CHECK: ldr     x0, [x0]
@@ -230,6 +252,17 @@ define float* @preidxf32(float* %src, float* %out) {
   ret float* %ptr
 }
 
+define half* @preidxf16(half* %src, half* %out) {
+; CHECK-LABEL: preidxf16:
+; CHECK: ldr     h0, [x0, #2]!
+; CHECK: str     h0, [x1]
+; CHECK: ret
+  %ptr = getelementptr inbounds half, half* %src, i64 1
+  %tmp = load half, half* %ptr, align 2
+  store half %tmp, half* %out, align 2
+  ret half* %ptr
+}
+
 define i64* @preidx64(i64* %src, i64* %out) {
 ; CHECK-LABEL: preidx64:
 ; CHECK: ldr     x[[REG:[0-9]+]], [x0, #8]!