From: Shawn Lin Date: Fri, 13 Jan 2017 01:56:51 +0000 (+0800) Subject: FROMLIST: arm64: dts: rockchip: add aspm-no-l0s for rk3399 X-Git-Tag: firefly_0821_release~754 X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=09c649805149bfd8dab847a00cd85c19f87557fa;p=firefly-linux-kernel-4.4.55.git FROMLIST: arm64: dts: rockchip: add aspm-no-l0s for rk3399 Per the discussion of bug fix[1], we now actually leaves the default clock choice for pcie phy is derived from 24MHz OSC to guarantee the least BER. So let's add aspm-no-l0s here and folks could delete this property from their dts. Change-Id: I5ee57a2e27d3751f6541fdf059e6745c26d0a6ef [1] https://patchwork.kernel.org/patch/9470519/ Signed-off-by: Shawn Lin (cherr picked from https://patchwork.kernel.org/patch/9477651/) --- diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index ebc229706fef..f3c7f153e276 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -1190,6 +1190,7 @@ compatible = "rockchip,rk3399-pcie"; #address-cells = <3>; #size-cells = <2>; + aspm-no-l0s; clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>, <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>; clock-names = "aclk", "aclk-perf",