From: roger <cz@rock-chips.com>
Date: Wed, 13 Aug 2014 11:05:28 +0000 (+0800)
Subject: ethernet: fix the bug of rmii not work when clock input from PHY
X-Git-Tag: firefly_0821_release~4902
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=0a23c7826b4c44a2cc62eee71e472b89e4f0839e;p=firefly-linux-kernel-4.4.55.git

ethernet: fix the bug of rmii not work when clock input from PHY
---

diff --git a/drivers/net/ethernet/rockchip/gmac/stmmac_platform.c b/drivers/net/ethernet/rockchip/gmac/stmmac_platform.c
index 9d8b2a2b59d4..96f40ca801c5 100755
--- a/drivers/net/ethernet/rockchip/gmac/stmmac_platform.c
+++ b/drivers/net/ethernet/rockchip/gmac/stmmac_platform.c
@@ -196,8 +196,10 @@ int gmac_clk_init(struct device *device)
 	}
 
 #ifdef CONFIG_GMAC_CLK_IN
+	clk_set_rate(bsp_priv->gmac_clkin, 50000000);
 	clk_set_parent(bsp_priv->clk_mac, bsp_priv->gmac_clkin);
 #else
+	clk_set_rate(bsp_priv->clk_mac_pll, 50000000);
 	clk_set_parent(bsp_priv->clk_mac, bsp_priv->clk_mac_pll);
 #endif
 	return 0;
@@ -211,9 +213,6 @@ static int gmac_clk_enable(bool enable) {
 	if (enable) {
 		if (!bsp_priv->clk_enable) {
 			if (phy_iface == PHY_INTERFACE_MODE_RMII) {
-				if (!IS_ERR(bsp_priv->clk_mac))
-					clk_set_rate(bsp_priv->clk_mac, 50000000);
-
 				if (!IS_ERR(bsp_priv->mac_clk_rx))
 					clk_prepare_enable(bsp_priv->mac_clk_rx);