From: Owen Anderson <resistor@mac.com>
Date: Fri, 12 Aug 2011 20:36:11 +0000 (+0000)
Subject: Fix some remaining issues with decoding ARM-mode memory instructions, and add another... 
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=0d09499cf3e2d927cdc53ec79895303ac12808ac;p=oota-llvm.git

Fix some remaining issues with decoding ARM-mode memory instructions, and add another batch of tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137502 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index 8641d0b26a3..9e0e56e6400 100644
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -730,7 +730,6 @@ def am3offset : Operand<i32>,
                 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
                                [], [SDNPWantRoot]> {
   let EncoderMethod = "getAddrMode3OffsetOpValue";
-  let DecoderMethod = "DecodeAddrMode3Offset";
   let PrintMethod = "printAddrMode3OffsetOperand";
   let ParserMatchClass = AM3OffsetAsmOperand;
   let MIOperandInfo = (ops GPR, i32imm);
@@ -2061,6 +2060,7 @@ multiclass AI3_ldridx<bits<4> op, string opc, InstrItinClass itin> {
     let Inst{11-8}  = addr{7-4};    // imm7_4/zero
     let Inst{3-0}   = addr{3-0};    // imm3_0/Rm
     let AsmMatchConverter = "cvtLdWriteBackRegAddrMode3";
+    let DecoderMethod = "DecodeAddrMode3Instruction";
   }
   def _POST : AI3ldstidx<op, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
                         (ins addr_offset_none:$addr, am3offset:$offset),
@@ -2074,6 +2074,7 @@ multiclass AI3_ldridx<bits<4> op, string opc, InstrItinClass itin> {
     let Inst{19-16} = addr;
     let Inst{11-8}  = offset{7-4};    // imm7_4/zero
     let Inst{3-0}   = offset{3-0};    // imm3_0/Rm
+    let DecoderMethod = "DecodeAddrMode3Instruction";
   }
 }
 
diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index b3db84947d1..5cebabc65b2 100644
--- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -129,8 +129,6 @@ static bool DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
                                uint64_t Address, const void *Decoder);
 static bool DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn,
                                uint64_t Address, const void *Decoder);
-static bool DecodeAddrMode3Offset(llvm::MCInst &Inst, unsigned Insn,
-                               uint64_t Address, const void *Decoder);
 static bool DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn,
                                uint64_t Address, const void *Decoder);
 static bool DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn,
@@ -970,6 +968,7 @@ static bool DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn,
     case ARM::LDRB_POST_IMM:
     case ARM::LDRB_POST_REG:
     case ARM::LDR_PRE:
+    case ARM::LDRB_PRE:
     case ARM::LDRBT_POST_REG:
     case ARM::LDRBT_POST_IMM:
     case ARM::LDRT_POST_REG:
@@ -1123,6 +1122,15 @@ static bool DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn,
     case ARM::LDRD:
     case ARM::LDRD_PRE:
     case ARM::LDRD_POST:
+    case ARM::LDRH:
+    case ARM::LDRH_PRE:
+    case ARM::LDRH_POST:
+    case ARM::LDRSH:
+    case ARM::LDRSH_PRE:
+    case ARM::LDRSH_POST:
+    case ARM::LDRSB:
+    case ARM::LDRSB_PRE:
+    case ARM::LDRSB_POST:
     case ARM::LDRHTr:
     case ARM::LDRSBTr:
       if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))
@@ -2451,23 +2459,6 @@ static bool DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
   return true;
 }
 
-static bool DecodeAddrMode3Offset(llvm::MCInst &Inst, unsigned Val,
-                                  uint64_t Address, const void *Decoder) {
-  bool isImm = fieldFromInstruction32(Val, 9, 1);
-  bool isAdd = fieldFromInstruction32(Val, 8, 1);
-  unsigned imm = fieldFromInstruction32(Val, 0, 8);
-
-  if (!isImm) {
-    if (!DecodeGPRRegisterClass(Inst, imm, Address, Decoder)) return false;
-    Inst.addOperand(MCOperand::CreateImm(!isAdd << 8));
-  } else {
-    Inst.addOperand(MCOperand::CreateReg(0));
-    Inst.addOperand(MCOperand::CreateImm(imm | (!isAdd << 8)));
-  }
-
-  return true;
-}
-
 static bool DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val,
                                    uint64_t Address, const void *Decoder) {
   switch (Val) {
diff --git a/test/MC/Disassembler/ARM/memory-arm-instructions.txt b/test/MC/Disassembler/ARM/memory-arm-instructions.txt
new file mode 100644
index 00000000000..aba0ba412c0
--- /dev/null
+++ b/test/MC/Disassembler/ARM/memory-arm-instructions.txt
@@ -0,0 +1,471 @@
+# RUN: llvm-mc -triple=armv7-apple-darwin -disassemble < %s | FileCheck %s
+
+#------------------------------------------------------------------------------
+# LDR (immediate)
+#------------------------------------------------------------------------------
+# CHECK: ldr r5, [r7]
+# CHECK: ldr r6, [r3, #63]
+# CHECK: ldr r2, [r4, #4095]!
+# CHECK: ldr r1, [r2], #30
+# CHECK: ldr r3, [r1], #-30
+
+0x00 0x50 0x97 0xe5
+0x3f 0x60 0x93 0xe5
+0xff 0x2f 0xb4 0xe5
+0x1e 0x10 0x92 0xe4
+0x1e 0x30 0x11 0xe4
+
+#------------------------------------------------------------------------------
+# FIXME: LDR (literal)
+#------------------------------------------------------------------------------
+# label operands currently assert the show-encoding asm comment helper due
+# to the use of non-contiguous bit ranges for fixups in ARM. Once that's
+# cleaned up, we can write useful assembly testcases for these sorts of
+# instructions.
+
+#------------------------------------------------------------------------------
+# LDR (register)
+#------------------------------------------------------------------------------
+# CHECK: ldr r3, [r8, r1]
+# CHECK: ldr r2, [r5, -r3]
+# CHECK: ldr r1, [r5, r9]!
+# CHECK: ldr r6, [r7, -r8]!
+# CHECK: ldr r1, [r0, r2, lsr #3]!
+# CHECK: ldr r5, [r9], r2
+# CHECK: ldr r4, [r3], -r6
+# CHECK: ldr r3, [r8, -r2, lsl #15
+# CHECK: ldr r1, [r5], r3, asr #15
+
+0x01 0x30 0x98 0xe7
+0x03 0x20 0x15 0xe7
+0x09 0x10 0xb5 0xe7
+0x08 0x60 0x37 0xe7
+0xa2 0x11 0xb0 0xe7
+0x02 0x50 0x99 0xe6
+0x06 0x40 0x13 0xe6
+0x82 0x37 0x18 0xe7
+0xc3 0x17 0x95 0xe6
+
+
+#------------------------------------------------------------------------------
+# LDRB (immediate)
+#------------------------------------------------------------------------------
+# CHECK: ldrb r3, [r8]
+# CHECK: ldrb r1, [sp, #63]
+# CHECK: ldrb r9, [r3, #4095]!
+# CHECK: ldrb r8, [r1], #22
+# CHECK: ldrb r2, [r7], #-19
+
+0x00 0x30 0xd8 0xe5
+0x3f 0x10 0xdd 0xe5
+0xff 0x9f 0xf3 0xe5
+0x16 0x80 0xd1 0xe4
+0x13 0x20 0x57 0xe4
+
+
+#------------------------------------------------------------------------------
+# LDRB (register)
+#------------------------------------------------------------------------------
+# CHECK: ldrb r9, [r8, r5]
+# CHECK: ldrb r1, [r5, -r1]
+# CHECK: ldrb r3, [r5, r2]!
+# CHECK: ldrb r6, [r9, -r3]!
+# CHECK: ldrb r2, [r1], r4
+# CHECK: ldrb r8, [r4], -r5
+# CHECK: ldrb r7, [r12, -r1, lsl #15
+# CHECK: ldrb r5, [r2], r9, asr #15
+
+0x05 0x90 0xd8 0xe7
+0x01 0x10 0x55 0xe7
+0x02 0x30 0xf5 0xe7
+0x03 0x60 0x79 0xe7
+0x04 0x20 0xd1 0xe6
+0x05 0x80 0x54 0xe6
+0x81 0x77 0x5c 0xe7
+0xc9 0x57 0xd2 0xe6
+
+
+#------------------------------------------------------------------------------
+# LDRBT
+#------------------------------------------------------------------------------
+# FIXME: Optional offset operand.
+# CHECK: ldrbt r3, [r1], #4
+# CHECK: ldrbt r2, [r8], #-8
+# CHECK: ldrbt r8, [r7], r6
+# CHECK: ldrbt r1, [r2], -r6, lsl #12
+
+
+0x04 0x30 0xf1 0xe4
+0x08 0x20 0x78 0xe4
+0x06 0x80 0xf7 0xe6
+0x06 0x16 0x72 0xe6
+
+
+#------------------------------------------------------------------------------
+# LDRD (immediate)
+#------------------------------------------------------------------------------
+# CHECK: ldrd r3, r4, [r5
+# CHECK: ldrd r7, r8, [r2, #15
+# CHECK: ldrd r1, r2, [r9, #32]!
+# CHECK: ldrd r6, r7, [r1], #8
+# CHECK: ldrd r1, r2, [r8], #0
+# CHECK: ldrd r1, r2, [r8], #0
+# CHECK: ldrd r1, r2, [r8], #-0
+
+0xd0 0x30 0xc5 0xe1
+0xdf 0x70 0xc2 0xe1
+0xd0 0x12 0xe9 0xe1
+0xd8 0x60 0xc1 0xe0
+0xd0 0x10 0xc8 0xe0
+0xd0 0x10 0xc8 0xe0
+0xd0 0x10 0x48 0xe0
+
+
+#------------------------------------------------------------------------------
+# FIXME: LDRD (label)
+#------------------------------------------------------------------------------
+
+#------------------------------------------------------------------------------
+# LDRD (register)
+#------------------------------------------------------------------------------
+# CHECK: ldrd r3, r4, [r1, r3
+# CHECK: ldrd r4, r5, [r7, r2]!
+# CHECK: ldrd r1, r2, [r8], r12
+# CHECK: ldrd r1, r2, [r8], -r12
+
+0xd3 0x30 0x81 0xe1
+0xd2 0x40 0xa7 0xe1
+0xdc 0x10 0x88 0xe0
+0xdc 0x10 0x08 0xe0
+
+
+#------------------------------------------------------------------------------
+# LDRH (immediate)
+#------------------------------------------------------------------------------
+# CHECK: ldrh r3, [r4
+# CHECK: ldrh r2, [r7, #4
+# CHECK: ldrh r1, [r8, #64]!
+# CHECK: ldrh r12, [sp], #4
+
+0xb0 0x30 0xd4 0xe1
+0xb4 0x20 0xd7 0xe1
+0xb0 0x14 0xf8 0xe1
+0xb4 0xc0 0xdd 0xe0
+
+
+#------------------------------------------------------------------------------
+# FIXME: LDRH (label)
+#------------------------------------------------------------------------------
+
+
+#------------------------------------------------------------------------------
+# LDRH (register)
+#------------------------------------------------------------------------------
+# CHECK: ldrh r6, [r5, r4
+# CHECK: ldrh r3, [r8, r11]!
+# CHECK: ldrh r1, [r2, -r1]!
+# CHECK: ldrh r9, [r7], r2
+# CHECK: ldrh r4, [r3], -r2
+
+0xb4 0x60 0x95 0xe1
+0xbb 0x30 0xb8 0xe1
+0xb1 0x10 0x32 0xe1
+0xb2 0x90 0x97 0xe0
+0xb2 0x40 0x13 0xe0
+
+
+#------------------------------------------------------------------------------
+# LDRHT
+#------------------------------------------------------------------------------
+# CHECK: ldrht r9, [r7], #128
+# CHECK: ldrht r4, [r3], #-75
+# CHECK: ldrht r9, [r7], r2
+# CHECK: ldrht r4, [r3], -r2
+
+0xb0 0x98 0xf7 0xe0
+0xbb 0x44 0x73 0xe0
+0xb2 0x90 0xb7 0xe0
+0xb2 0x40 0x33 0xe0
+
+
+#------------------------------------------------------------------------------
+# LDRSB (immediate)
+#------------------------------------------------------------------------------
+# CHECK: ldrsb r3, [r4
+# CHECK: ldrsb r2, [r7, #17
+# CHECK: ldrsb r1, [r8, #255]!
+# CHECK: ldrsb r12, [sp], #9
+
+0xd0 0x30 0xd4 0xe1
+0xd1 0x21 0xd7 0xe1
+0xdf 0x1f 0xf8 0xe1
+0xd9 0xc0 0xdd 0xe0
+
+
+#------------------------------------------------------------------------------
+# FIXME: LDRSB (label)
+#------------------------------------------------------------------------------
+
+
+#------------------------------------------------------------------------------
+# LDRSB (register)
+#------------------------------------------------------------------------------
+# CHECK: ldrsb r6, [r5, r4
+# CHECK: ldrsb r3, [r8, r11]!
+# CHECK: ldrsb r1, [r2, -r1]!
+# CHECK: ldrsb r9, [r7], r2
+# CHECK: ldrsb r4, [r3], -r2
+
+
+0xd4 0x60 0x95 0xe1
+0xdb 0x30 0xb8 0xe1
+0xd1 0x10 0x32 0xe1
+0xd2 0x90 0x97 0xe0
+0xd2 0x40 0x13 0xe0
+
+
+#------------------------------------------------------------------------------
+# LDRSBT
+#------------------------------------------------------------------------------
+# CHECK: ldrsbt r5, [r6], #1
+# CHECK: ldrsbt r3, [r8], #-12
+# CHECK: ldrsbt r8, [r9], r5
+# CHECK: ldrsbt r2, [r1], -r4
+
+0xd1 0x50 0xf6 0xe0
+0xdc 0x30 0x78 0xe0
+0xd5 0x80 0xb9 0xe0
+0xd4 0x20 0x31 0xe0
+
+
+#------------------------------------------------------------------------------
+# LDRSH (immediate)
+#------------------------------------------------------------------------------
+# CHECK: ldrsh r5, [r9
+# CHECK: ldrsh r4, [r5, #7
+# CHECK: ldrsh r3, [r6, #55]!
+# CHECK: ldrsh r2, [r7], #-9
+
+0xf0 0x50 0xd9 0xe1
+0xf7 0x40 0xd5 0xe1
+0xf7 0x33 0xf6 0xe1
+0xf9 0x20 0x57 0xe0
+
+
+#------------------------------------------------------------------------------
+# FIXME: LDRSH (label)
+#------------------------------------------------------------------------------
+
+
+#------------------------------------------------------------------------------
+# LDRSH (register)
+#------------------------------------------------------------------------------
+# CHECK: ldrsh r3, [r1, r5
+# CHECK: ldrsh r4, [r6, r1]!
+# CHECK: ldrsh r5, [r3, -r6]!
+# CHECK: ldrsh r6, [r9], r8
+# CHECK: ldrsh r7, [r8], -r3
+
+0xf5 0x30 0x91 0xe1
+0xf1 0x40 0xb6 0xe1
+0xf6 0x50 0x33 0xe1
+0xf8 0x60 0x99 0xe0
+0xf3 0x70 0x18 0xe0
+
+
+#------------------------------------------------------------------------------
+# LDRSHT
+#------------------------------------------------------------------------------
+# CHECK: ldrsht r5, [r6], #1
+# CHECK: ldrsht r3, [r8], #-12
+# CHECK: ldrsht r8, [r9], r5
+# CHECK: ldrsht r2, [r1], -r4
+
+0xf1 0x50 0xf6 0xe0
+0xfc 0x30 0x78 0xe0
+0xf5 0x80 0xb9 0xe0
+0xf4 0x20 0x31 0xe0
+
+
+#------------------------------------------------------------------------------
+# STR (immediate)
+#------------------------------------------------------------------------------
+# CHECK: str r8, [r12
+# CHECK: str r7, [r1, #12
+# CHECK: str r3, [r5, #40]!
+# CHECK: str r9, [sp], #4095
+# CHECK: str r1, [r7], #-128
+
+0x00 0x80 0x8c 0xe5
+0x0c 0x70 0x81 0xe5
+0x28 0x30 0xa5 0xe5
+0xff 0x9f 0x8d 0xe4
+0x80 0x10 0x07 0xe4
+
+
+#------------------------------------------------------------------------------
+# FIXME: STR (literal)
+#------------------------------------------------------------------------------
+
+#------------------------------------------------------------------------------
+# STR (register)
+#------------------------------------------------------------------------------
+# CHECK: str r9, [r6, r3
+# CHECK: str r8, [r0, -r2
+# CHECK: str r7, [r1, r6]!
+# CHECK: str r6, [sp, -r1]!
+# CHECK: str r5, [r3], r9
+# CHECK: str r4, [r2], -r5
+# CHECK: str r3, [r4, -r2, lsl #2
+# CHECK: str r2, [r7], r3, asr #24
+
+0x03 0x90 0x86 0xe7
+0x02 0x80 0x00 0xe7
+0x06 0x70 0xa1 0xe7
+0x01 0x60 0x2d 0xe7
+0x09 0x50 0x83 0xe6
+0x05 0x40 0x02 0xe6
+0x02 0x31 0x04 0xe7
+0x43 0x2c 0x87 0xe6
+
+
+#------------------------------------------------------------------------------
+# STRB (immediate)
+#------------------------------------------------------------------------------
+# CHECK: strb r9, [r2
+# CHECK: strb r7, [r1, #3
+# CHECK: strb r6, [r4, #405]!
+# CHECK: strb r5, [r7], #72
+# CHECK: strb r1, [sp], #-1
+
+0x00 0x90 0xc2 0xe5
+0x03 0x70 0xc1 0xe5
+0x95 0x61 0xe4 0xe5
+0x48 0x50 0xc7 0xe4
+0x01 0x10 0x4d 0xe4
+
+#------------------------------------------------------------------------------
+# FIXME: STRB (literal)
+#------------------------------------------------------------------------------
+
+#------------------------------------------------------------------------------
+# STRB (register)
+#------------------------------------------------------------------------------
+# CHECK: strb r1, [r2, r9
+# CHECK: strb r2, [r3, -r8
+# CHECK: strb r3, [r4, r7]!
+# CHECK: strb r4, [r5, -r6]!
+# CHECK: strb r5, [r6], r5
+# CHECK: strb r6, [r2], -r4
+# CHECK: strb r7, [r12, -r3, lsl #5
+# CHECK: strb sp, [r7], r2, asr #12
+
+0x09 0x10 0xc2 0xe7
+0x08 0x20 0x43 0xe7
+0x07 0x30 0xe4 0xe7
+0x06 0x40 0x65 0xe7
+0x05 0x50 0xc6 0xe6
+0x04 0x60 0x42 0xe6
+0x83 0x72 0x4c 0xe7
+0x42 0xd6 0xc7 0xe6
+
+
+#------------------------------------------------------------------------------
+# STRBT
+#------------------------------------------------------------------------------
+# FIXME: Optional offset operand.
+# CHECK: strbt r6, [r2], #12
+# CHECK: strbt r5, [r6], #-13
+# CHECK: strbt r4, [r9], r5
+# CHECK: strbt r3, [r8], -r2, lsl #3
+
+0x0c 0x60 0xe2 0xe4
+0x0d 0x50 0x66 0xe4
+0x05 0x40 0xe9 0xe6
+0x82 0x31 0x68 0xe6
+
+
+#------------------------------------------------------------------------------
+# STRD (immediate)
+#------------------------------------------------------------------------------
+# CHECK: strd r1, r2, [r4
+# CHECK: strd r2, r3, [r6, #1
+# CHECK: strd r3, r4, [r7, #22]!
+# CHECK: strd r4, r5, [r8], #7
+# CHECK: strd r5, r6, [sp], #0
+# CHECK: strd r6, r7, [lr], #0
+# CHECK: strd r7, r8, [r9], #-0
+
+0xf0 0x10 0xc4 0xe1
+0xf1 0x20 0xc6 0xe1
+0xf6 0x31 0xe7 0xe1
+0xf7 0x40 0xc8 0xe0
+0xf0 0x50 0xcd 0xe0
+0xf0 0x60 0xce 0xe0
+0xf0 0x70 0x49 0xe0
+
+
+#------------------------------------------------------------------------------
+# FIXME: STRD (label)
+#------------------------------------------------------------------------------
+
+#------------------------------------------------------------------------------
+# STRD (register)
+#------------------------------------------------------------------------------
+# CHECK: strd r8, r9, [r4, r1
+# CHECK: strd r7, r8, [r3, r9]!
+# CHECK: strd r6, r7, [r5], r8
+# CHECK: strd r5, r6, [r12], -r10
+
+0xf1 0x80 0x84 0xe1
+0xf9 0x70 0xa3 0xe1
+0xf8 0x60 0x85 0xe0
+0xfa 0x50 0x0c 0xe0
+
+
+#------------------------------------------------------------------------------
+# STRH (immediate)
+#------------------------------------------------------------------------------
+# CHECK: strh r3, [r4
+# CHECK: strh r2, [r7, #4
+# CHECK: strh r1, [r8, #64]!
+# CHECK: strh r12, [sp], #4
+
+0xb0 0x30 0xc4 0xe1
+0xb4 0x20 0xc7 0xe1
+0xb0 0x14 0xe8 0xe1
+0xb4 0xc0 0xcd 0xe0
+
+
+#------------------------------------------------------------------------------
+# FIXME: STRH (label)
+#------------------------------------------------------------------------------
+
+
+#------------------------------------------------------------------------------
+# STRH (register)
+#------------------------------------------------------------------------------
+# CHECK: strh r6, [r5, r4
+# CHECK: strh r3, [r8, r11]!
+# CHECK: strh r1, [r2, -r1]!
+# CHECK: strh r9, [r7], r2
+# CHECK: strh r4, [r3], -r2
+
+0xb4 0x60 0x85 0xe1
+0xbb 0x30 0xa8 0xe1
+0xb1 0x10 0x22 0xe1
+0xb2 0x90 0x87 0xe0
+0xb2 0x40 0x03 0xe0
+
+#------------------------------------------------------------------------------
+# STRHT
+#------------------------------------------------------------------------------
+# CHECK: strht r2, [r5], #76
+# CHECK: strht r8, [r1], #-25
+# CHECK: strht r5, [r3], r4
+# CHECK: strht r6, [r8], -r0
+
+0xbc 0x24 0xe5 0xe0
+0xb9 0x81 0x61 0xe0
+0xb4 0x50 0xa3 0xe0
+0xb0 0x60 0x28 0xe0