From: Stephen Boyd <sboyd@codeaurora.org>
Date: Wed, 2 Mar 2016 01:26:48 +0000 (-0800)
Subject: clk: qcom: msm8960: Fix ce3_src register offset
X-Git-Tag: firefly_0821_release~176^2~4^2~46^2~51
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=0d50da4683464e150961142341c69ea5a578974a;p=firefly-linux-kernel-4.4.55.git

clk: qcom: msm8960: Fix ce3_src register offset

commit 0f75e1a370fd843c9e508fc1ccf0662833034827 upstream.

The offset seems to have been copied from the sata clk. Fix it so
that enabling the crypto engine source clk works.

Tested-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Fixes: 5f775498bdc4 ("clk: qcom: Fully support apq8064 global clock control")
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---

diff --git a/drivers/clk/qcom/gcc-msm8960.c b/drivers/clk/qcom/gcc-msm8960.c
index 2c83c03309cb..bdc4b2d07a23 100644
--- a/drivers/clk/qcom/gcc-msm8960.c
+++ b/drivers/clk/qcom/gcc-msm8960.c
@@ -2753,7 +2753,7 @@ static struct clk_rcg ce3_src = {
 	},
 	.freq_tbl = clk_tbl_ce3,
 	.clkr = {
-		.enable_reg = 0x2c08,
+		.enable_reg = 0x36c0,
 		.enable_mask = BIT(7),
 		.hw.init = &(struct clk_init_data){
 			.name = "ce3_src",