From: Minghuan Lian <Minghuan.Lian@freescale.com>
Date: Wed, 31 Jul 2013 02:59:07 +0000 (+0800)
Subject: powerpc/dts: fix sRIO error interrupt for b4860
X-Git-Tag: firefly_0821_release~176^2~4907^2~54^2~25
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=0e3d4373b8a7757a8f5187f5cabafb6aceff469b;p=firefly-linux-kernel-4.4.55.git

powerpc/dts: fix sRIO error interrupt for b4860

For B4 platform, MPIC EISR register is in reversed bitmap order,
instead of "Error interrupt source 0-31. Bit 0 represents SRC0."
the correct ordering is "Error interrupt source 0-31. Bit 0
represents SRC31." This patch is to fix sRIO EISR bit value
of error interrupt in dts node.

Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
---

diff --git a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
index e5cf6c81dd66..981397518fc6 100644
--- a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
@@ -41,7 +41,7 @@
 
 &rio {
 	compatible = "fsl,srio";
-	interrupts = <16 2 1 11>;
+	interrupts = <16 2 1 20>;
 	#address-cells = <2>;
 	#size-cells = <2>;
 	fsl,iommu-parent = <&pamu0>;