From: xxm <xxm@rock-chips.com>
Date: Wed, 23 Jul 2014 05:41:30 +0000 (+0800)
Subject: rk3036:update rk312x.dtsi with iommu and gpu
X-Git-Tag: firefly_0821_release~4916^2~173
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=0ea7f1bb3ff55eb37d2e159953c3f3c04a645d3d;p=firefly-linux-kernel-4.4.55.git

rk3036:update rk312x.dtsi with iommu and gpu
---

diff --git a/arch/arm/boot/dts/rk312x.dtsi b/arch/arm/boot/dts/rk312x.dtsi
index b16a85a489ee..5bed6551dcdb 100755
--- a/arch/arm/boot/dts/rk312x.dtsi
+++ b/arch/arm/boot/dts/rk312x.dtsi
@@ -207,6 +207,38 @@
 	/*	rockchip,clocks-uboot-has-init =
 			<&aclk_vio1>;*/
 	};
+	gpu {
+		compatible = "arm,mali400";
+		reg = <0x10091000 0x200>,
+		      <0x10090000 0x100>,
+		      <0x10093000 0x100>,
+		      <0x10098000 0x1100>,
+		      <0x10094000 0x100>;
+		      <0x1009A000 0x1100>,
+		      <0x10095000 0x100>;
+		
+		reg-names = "Mali_L2",
+			    "Mali_GP",
+			    "Mali_GP_MMU",
+			    "Mali_PP0",
+			    "Mali_PP0_MMU",
+			    "Mali_PP1",
+			    "Mali_PP1_MMU";
+
+	    	interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+	    		     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+			     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+	    	
+		interrupt-names = "Mali_GP_IRQ",
+	    		          "Mali_GP_MMU_IRQ",
+			          "Mali_PP0_IRQ",
+			          "Mali_PP0_MMU_IRQ";
+			          "Mali_PP1_IRQ",
+			          "Mali_PP1_MMU_IRQ";
+	  };
 
 	clocks-enable {
 		compatible = "rockchip,clocks-enable";
@@ -485,4 +517,38 @@
 		clock-names = "aclk_iep", "hclk_iep";
 		status = "okay";
 	};
+	
+	vop_mmu {
+		dbgname = "vop";
+		compatible = "iommu,vop_mmu";
+		reg = <0x1010e300 0x100>;
+		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "vop_mmu";
+	  };
+
+	  hevc_mmu {
+		dbgname = "hevc";
+		compatible = "iommu,hevc_mmu";
+		reg = <0x10104440 0x100>,
+		      <0x10104480 0x100>;
+		interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "hevc_mmu";
+	  };
+
+	  vpu_mmu {
+		dbgname = "vpu";
+		compatible = "iommu,vpu_mmu";
+		reg = <0x10104800 0x100>;
+		interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "vpu_mmu";
+	  };
+
+	  iep_mmu {
+		dbgname = "iep";
+		compatible = "iommu,iep_mmu";
+		reg = <0x10108800 0x100>;
+		interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "iep_mmu";
+	  };
+
 };