From: Chris Zhong Date: Tue, 15 Sep 2015 03:47:41 +0000 (+0800) Subject: ARM: dts: fix some code style issues X-Git-Tag: firefly_0821_release~3778 X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=0f3661b46e7dfca5223ff1a5343bb38b05ba9ff9;p=firefly-linux-kernel-4.4.55.git ARM: dts: fix some code style issues Change-Id: I3f1f5637729171079ca7d108ba59521018c9561d Signed-off-by: Chris Zhong --- diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi old mode 100755 new mode 100644 index 5fb9529c7666..f3af8822fb0d --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -191,8 +191,10 @@ timer { compatible = "arm,armv7-timer"; - interrupts = , - ; + interrupts = , + ; clock-frequency = <24000000>; }; @@ -268,7 +270,7 @@ clocks = <&clk_nandc1>, <&clk_gates5 6>, <&clk_gates7 15>; clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc"; }; - + nandc0reg: nandc0@0xff400000 { compatible = "rockchip,rk-nandc"; reg = <0xff400000 0x4000>; @@ -281,7 +283,8 @@ #address-cells = <1>; #size-cells = <0>; //pinctrl-names = "default",,"suspend"; - //pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_wp &sd0_pwr &sd0_bus1 &sd0_bus4>; + //pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_wp &sd0_pwr + // &sd0_bus1 &sd0_bus4>; clocks = <&clk_emmc>, <&clk_gates8 6>; clock-names = "clk_mmc", "hclk_mmc"; num-slots = <1>; @@ -299,7 +302,8 @@ #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default", "idle"; - pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>; + pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn + &sdmmc0_bus4>; pinctrl-1 = <&sdmmc0_gpio>; cd-gpios = <&gpio6 GPIO_C6 GPIO_ACTIVE_HIGH>;/*CD GPIO*/ clocks = <&clk_sdmmc>, <&clk_gates8 3>; @@ -319,8 +323,8 @@ #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default","idle"; - pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_wrprt &sdio0_pwr &sdio0_bkpwr - &sdio0_intn &sdio0_bus4>; + pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_wrprt &sdio0_pwr + &sdio0_bkpwr &sdio0_intn &sdio0_bus4>; pinctrl-1 = <&sdio0_gpio>; clocks = <&clk_sdio0>, <&clk_gates8 4>; clock-names = "clk_mmc", "hclk_mmc"; @@ -339,8 +343,12 @@ #address-cells = <1>; #size-cells = <0>; //pinctrl-names = "default","suspend"; - //pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_wp &sd1_bus1 &sd1_bus4>; - /*gate8_0 --hclk_sdmmc_ahb_arbi_gate_en, gate13_2 --clk_sdio1_src_gate_en*/ + //pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd + // &sd1_wp &sd1_bus1 &sd1_bus4>; + + /* gate8_0 --hclk_sdmmc_ahb_arbi_gate_en, + * gate13_2 --clk_sdio1_src_gate_en + */ clocks = <&clk_sdio1>, <&clk_gates8 5>; clock-names = "clk_mmc", "hclk_mmc"; num-slots = <1>; @@ -502,33 +510,32 @@ <&clk_i2s_pll &clk_gpll>, <&clk_spdif_pll &clk_gpll>, <&usbphy_480m &otgphy2_480m>; rockchip,clocks-init-rate = - <&clk_core 792000000>, <&clk_gpll 594000000>, - /*<&clk_cpll 47000000>,*/ <&clk_npll 1250000000>, - <&aclk_bus_src 300000000>, <&aclk_bus 300000000>, - <&hclk_bus 150000000>, <&pclk_bus 75000000>, - <&clk_crypto 150000000>, <&aclk_peri 300000000>, - <&hclk_peri 150000000>, <&pclk_peri 75000000>, - <&clk_gpu 200000000>, /*<&aclk_vio0 300000000>, - <&aclk_vio1 300000000>, <&hclk_vio 75000000>,*/ - <&pclk_pd_alive 100000000>, <&pclk_pd_pmu 100000000>, - <&aclk_hevc 400000000>, <&hclk_hevc 200000000>, + <&clk_core 792000000>, <&clk_gpll 594000000>, + /*<&clk_cpll 47000000>,*/ <&clk_npll 1250000000>, + <&aclk_bus_src 300000000>, <&aclk_bus 300000000>, + <&hclk_bus 150000000>, <&pclk_bus 75000000>, + <&clk_crypto 150000000>, <&aclk_peri 300000000>, + <&hclk_peri 150000000>, <&pclk_peri 75000000>, + <&clk_gpu 200000000>, /*<&aclk_vio0 300000000>, + <&aclk_vio1 300000000>, <&hclk_vio 75000000>,*/ + <&pclk_pd_alive 100000000>, <&pclk_pd_pmu 100000000>, + <&aclk_hevc 400000000>, <&hclk_hevc 200000000>, <&clk_hevc_cabac 300000000>, <&clk_hevc_core 300000000>, <&aclk_rga 300000000>, <&clk_rga 300000000>, <&clk_vepu 300000000>, <&clk_vdpu 300000000>, <&clk_edp 200000000>, <&clk_isp 200000000>, <&clk_isp_jpe 400000000>, <&clk_tsp 80000000>, <&clk_tspout 80000000>, <&clk_mac 125000000>; - /* rockchip,clocks-uboot-has-init = - <&aclk_vio0>; */ + /* rockchip,clocks-uboot-has-init = <&aclk_vio0>; */ }; clocks-enable { compatible = "rockchip,clocks-enable"; clocks = - /*PLL*/ + /* PLL */ <&clk_dpll>, <&clk_gpll>, - /*PD_CORE*/ + /* PD_CORE */ <&clk_gates0 2>, <&clk_core0>, <&clk_core1>, <&clk_core2>, <&clk_core3>, <&clk_l2ram>, @@ -537,73 +544,73 @@ <&clk_gates12 9>, <&clk_gates12 10>, <&clk_gates12 11>, - /*PD_BUS*/ + /* PD_BUS */ <&aclk_bus>, <&clk_gates0 3>, <&hclk_bus>, <&pclk_bus>, <&clk_gates13 8>, <&clk_gates0 7>, - /*TIMER*/ + /* TIMER */ <&clk_gates1 0>, <&clk_gates1 1>, <&clk_gates1 2>, <&clk_gates1 3>, <&clk_gates1 4>, <&clk_gates1 5>, <&pclk_pd_alive>, <&pclk_pd_pmu>, - /*PD_PERI*/ + /* PD_PERI */ <&aclk_peri>, <&hclk_peri>, <&pclk_peri>, - /*JTAG*/ - /*<&clk_gates4 14>,*/ + /* JTAG */ + /* <&clk_gates4 14>, */ - /*aclk_bus*/ - <&clk_gates10 5>,/*aclk_intmem0*/ - <&clk_gates10 6>,/*aclk_intmem1*/ - <&clk_gates10 7>,/*aclk_intmem2*/ - /*<&clk_gates10 12>,*//*aclk_dma1*/ - <&clk_gates10 13>,/*aclk_strc_sys*/ - <&clk_gates10 4>,/*aclk_intmem*/ + /* aclk_bus */ + <&clk_gates10 5>,/* aclk_intmem0 */ + <&clk_gates10 6>,/* aclk_intmem1 */ + <&clk_gates10 7>,/* aclk_intmem2 */ + /* <&clk_gates10 12>, */ /* aclk_dma1 */ + <&clk_gates10 13>,/* aclk_strc_sys */ + <&clk_gates10 4>,/* aclk_intmem */ - /*hclk_bus*/ - <&clk_gates10 9>,/*hclk_rom*/ + /* hclk_bus */ + <&clk_gates10 9>,/* hclk_rom */ - /*pclk_bus*/ - <&clk_gates10 1>,/*pclk_timer*/ - <&clk_gates10 9>,/*rom*/ - <&clk_gates10 13>,/*aclk strc*/ + /* pclk_bus */ + <&clk_gates10 1>,/* pclk_timer */ + <&clk_gates10 9>,/* rom */ + <&clk_gates10 13>,/* aclk strc */ - <&clk_gates12 8>,/*aclk strc*/ + <&clk_gates12 8>,/* aclk strc */ - /*aclk_peri*/ - <&clk_gates6 2>,/*aclk_peri_axi_matrix*/ - /*<&clk_gates6 3>,*//*aclk_dmac2*/ - <&clk_gates7 11>,/*aclk_peri_niu*/ - <&clk_gates8 12>,/*aclk_peri_mmu*/ + /* aclk_peri */ + <&clk_gates6 2>,/* aclk_peri_axi_matrix */ + /* <&clk_gates6 3>, */ /* aclk_dmac2 */ + <&clk_gates7 11>,/* aclk_peri_niu */ + <&clk_gates8 12>,/* aclk_peri_mmu */ - /*hclk_peri*/ - <&clk_gates6 0>,/*hclk_peri_matrix*/ - <&clk_gates7 10>,/*hclk_peri_ahb_arbi*/ - <&clk_gates7 12>,/*hclk_emem_peri*/ - <&clk_gates7 13>,/*hclk_mem_peri*/ + /* hclk_peri */ + <&clk_gates6 0>,/* hclk_peri_matrix */ + <&clk_gates7 10>,/* hclk_peri_ahb_arbi */ + <&clk_gates7 12>,/* hclk_emem_peri */ + <&clk_gates7 13>,/* hclk_mem_peri */ - /*pclk_peri*/ - <&clk_gates6 1>,/*pclk_peri_axi_matrix*/ + /* pclk_peri */ + <&clk_gates6 1>,/* pclk_peri_axi_matrix */ - /*pclk_pd_alive*/ - <&clk_gates14 11>,/*pclk_grf*/ - <&clk_gates14 12>,/*pclk_alive_niu*/ + /* pclk_pd_alive */ + <&clk_gates14 11>,/* pclk_grf */ + <&clk_gates14 12>,/* pclk_alive_niu */ - /*pclk_pd_pmu*/ - <&clk_gates17 0>,/*pclk_pmu*/ - <&clk_gates17 1>,/*pclk_intmem1*/ - <&clk_gates17 2>,/*pclk_pmu_niu*/ - <&clk_gates17 3>,/*pclk_sgrf*/ + /* pclk_pd_pmu */ + <&clk_gates17 0>,/* pclk_pmu */ + <&clk_gates17 1>,/* pclk_intmem1 */ + <&clk_gates17 2>,/* pclk_pmu_niu */ + <&clk_gates17 3>,/* pclk_sgrf */ - /*UART*/ - <&clk_gates11 9>,/*pclk_uart2*/ + /* UART */ + <&clk_gates11 9>,/* pclk_uart2 */ - /*480M*/ + /* 480M */ <&usbphy_480m>; }; @@ -616,7 +623,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&i2c0_sda &i2c0_scl>; pinctrl-1 = <&i2c0_gpio>; - gpios = <&gpio0 GPIO_B7 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_C0 GPIO_ACTIVE_LOW>; + gpios = <&gpio0 GPIO_B7 GPIO_ACTIVE_LOW>, + <&gpio0 GPIO_C0 GPIO_ACTIVE_LOW>; clocks = <&clk_gates10 2>; rockchip,check-idle = <1>; status = "disabled"; @@ -631,7 +639,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&i2c1_sda &i2c1_scl>; pinctrl-1 = <&i2c1_gpio>; - gpios = <&gpio8 GPIO_A4 GPIO_ACTIVE_LOW>, <&gpio8 GPIO_A5 GPIO_ACTIVE_LOW>; + gpios = <&gpio8 GPIO_A4 GPIO_ACTIVE_LOW>, + <&gpio8 GPIO_A5 GPIO_ACTIVE_LOW>; clocks = <&clk_gates6 13>; rockchip,check-idle = <1>; status = "disabled"; @@ -646,7 +655,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&i2c2_sda &i2c2_scl>; pinctrl-1 = <&i2c2_gpio>; - gpios = <&gpio6 GPIO_B1 GPIO_ACTIVE_LOW>, <&gpio6 GPIO_B2 GPIO_ACTIVE_LOW>; + gpios = <&gpio6 GPIO_B1 GPIO_ACTIVE_LOW>, + <&gpio6 GPIO_B2 GPIO_ACTIVE_LOW>; clocks = <&clk_gates10 3>; rockchip,check-idle = <1>; status = "disabled"; @@ -661,7 +671,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&i2c3_sda &i2c3_scl>; pinctrl-1 = <&i2c3_gpio>; - gpios = <&gpio2 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio2 GPIO_C0 GPIO_ACTIVE_LOW>; + gpios = <&gpio2 GPIO_C1 GPIO_ACTIVE_LOW>, + <&gpio2 GPIO_C0 GPIO_ACTIVE_LOW>; clocks = <&clk_gates6 14>; rockchip,check-idle = <1>; status = "disabled"; @@ -676,7 +687,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&i2c4_sda &i2c4_scl>; pinctrl-1 = <&i2c4_gpio>; - gpios = <&gpio7 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio7 GPIO_C2 GPIO_ACTIVE_LOW>; + gpios = <&gpio7 GPIO_C1 GPIO_ACTIVE_LOW>, + <&gpio7 GPIO_C2 GPIO_ACTIVE_LOW>; clocks = <&clk_gates6 15>; rockchip,check-idle = <1>; status = "disabled"; @@ -691,7 +703,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&i2c5_sda &i2c5_scl>; pinctrl-1 = <&i2c5_gpio>; - gpios = <&gpio7 GPIO_C3 GPIO_ACTIVE_LOW>, <&gpio7 GPIO_C4 GPIO_ACTIVE_LOW>; + gpios = <&gpio7 GPIO_C3 GPIO_ACTIVE_LOW>, + <&gpio7 GPIO_C4 GPIO_ACTIVE_LOW>; clocks = <&clk_gates7 0>; rockchip,check-idle = <1>; status = "disabled"; @@ -768,7 +781,8 @@ pinctrl-0 = <&lcdc0_lcdc>; pinctrl-1 = <&lcdc0_gpio>; status = "disabled"; - clocks = <&clk_gates15 5>, <&dclk_lcdc0>, <&clk_gates15 6>, <&pd_vop0>; + clocks = <&clk_gates15 5>, <&dclk_lcdc0>, <&clk_gates15 6>, + <&pd_vop0>; clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "pd_lcdc"; }; @@ -780,7 +794,8 @@ reg = <0xff940000 0x10000>; interrupts = ; status = "disabled"; - clocks = <&clk_gates15 7>, <&dclk_lcdc1>, <&clk_gates15 8>, <&pd_vop1>; + clocks = <&clk_gates15 7>, <&dclk_lcdc1>, <&clk_gates15 8>, + <&pd_vop1>; clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "pd_lcdc"; }; @@ -816,13 +831,14 @@ //#dma-cells = <2>; dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2s_mclk &i2s_sclk &i2s_lrckrx &i2s_lrcktx &i2s_sdi &i2s_sdo0 &i2s_sdo1 &i2s_sdo2 &i2s_sdo3>; + pinctrl-0 = <&i2s_mclk &i2s_sclk &i2s_lrckrx &i2s_lrcktx + &i2s_sdi &i2s_sdo0 &i2s_sdo1 &i2s_sdo2 &i2s_sdo3>; pinctrl-1 = <&i2s_gpio>; }; spdif: rockchip-spdif@0xff8b0000 { compatible = "rockchip-spdif"; - reg = <0xff8b0000 0x10000>; //8channel + reg = <0xff8b0000 0x10000>;//8channel //reg = ;//2channel clocks = <&clk_spdif>, <&clk_spdif_8ch>,<&clk_gates10 11>; clock-names = "spdif_mclk","spdif_8ch_mclk","spdif_hclk"; @@ -916,41 +932,45 @@ }; dvfs { - vd_arm: vd_arm { regulator_name = "vdd_arm"; suspend_volt = <1000>; //mV pd_core { clk_core_dvfs_table: clk_core { operating-points = < - /* KHz uV */ + /* KHz uV */ 312000 1100000 504000 1100000 816000 1100000 1008000 1100000 >; + channel = <0>; temp-limit-enable = <1>; target-temp = <80>; min_temp_limit = <48>; + normal-temp-limit = < - /*delta-temp delta-freq*/ + /* delta-temp delta-freq */ 3 96000 6 144000 9 192000 15 384000 >; + performance-temp-limit = < - /*temp freq*/ + /* temp freq */ 100 816000 >; - status = "okay"; + regu-mode-table = < - /*freq mode*/ + /* freq mode */ 1008000 4 0 3 - >; + >; + regu-mode-en = <0>; + status = "okay"; }; }; }; @@ -961,18 +981,20 @@ pd_ddr { clk_ddr_dvfs_table: clk_ddr { operating-points = < - /* KHz uV */ + /* KHz uV */ 200000 1200000 300000 1200000 400000 1200000 >; + bd-freq-table = < - /* bandwidth freq */ + /* bandwidth freq */ 5000 800000 3500 456000 2600 396000 2000 324000 >; + channel = <2>; status = "disabled"; }; @@ -981,10 +1003,11 @@ pd_vio { aclk_vio1_dvfs_table: aclk_vio1 { operating-points = < - /* KHz uV */ + /* KHz uV */ 100000 1100000 500000 1100000 >; + status = "okay"; }; }; @@ -996,28 +1019,32 @@ pd_gpu { clk_gpu_dvfs_table: clk_gpu { operating-points = < - /* KHz uV */ + /* KHz uV */ 200000 1200000 300000 1200000 400000 1200000 >; + channel = <1>; temp-limit-enable = <0>; target-temp = <90>; min_temp_limit = <200>; + normal-temp-limit = < - /*delta-temp delta-freq*/ + /*delta-temp delta-freq*/ 3 50000 6 150000 15 250000 >; - status = "okay"; + regu-mode-table = < - /*freq mode*/ + /*freq mode*/ 200000 4 0 3 >; + regu-mode-en = <0>; + status = "okay"; }; }; }; @@ -1033,12 +1060,14 @@ rockchip,ion_heap = <5>; reg = <0x00000000 0x00000000>; }; - ion_cma: rockchip,ion-heap@4 { /* CMA HEAP */ + ion_cma: rockchip,ion-heap@4 { + /* CMA HEAP */ compatible = "rockchip,ion-heap"; rockchip,ion_heap = <4>; reg = <0x00000000 0x28000000>; /* 640MB */ }; - rockchip,ion-heap@0 { /* VMALLOC HEAP */ + rockchip,ion-heap@0 { + /* VMALLOC HEAP */ compatible = "rockchip,ion-heap"; rockchip,ion_heap = <0>; }; @@ -1048,11 +1077,13 @@ compatible = "vpu_service"; iommu_enabled = <0>; reg = <0xff9a0000 0x800>; - interrupts = , ; + interrupts = , + ; interrupt-names = "irq_enc", "irq_dec"; clocks = <&clk_vdpu>, <&hclk_vdpu>; clock-names = "aclk_vcodec", "hclk_vcodec"; - resets = <&reset RK3288_SOFT_RST_VCODEC_H>, <&reset RK3288_SOFT_RST_VCODEC_A>; + resets = <&reset RK3288_SOFT_RST_VCODEC_H>, + <&reset RK3288_SOFT_RST_VCODEC_A>; reset-names = "video_h", "video_a"; name = "vpu_service"; dev_mode = <0>; @@ -1065,10 +1096,13 @@ reg = <0xff9c0000 0x800>; interrupts = ; interrupt-names = "irq_dec"; - clocks = <&aclk_hevc>, <&hclk_hevc>, <&clk_hevc_core>, <&clk_hevc_cabac>; - clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core", "clk_cabac"; - resets = <&reset RK3288_SOFT_RST_VCODEC_H>, <&reset RK3288_SOFT_RST_VCODEC_A>, - <&reset RK3288_SOFT_RST_HEVC>; + clocks = <&aclk_hevc>, <&hclk_hevc>, <&clk_hevc_core>, + <&clk_hevc_cabac>; + clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core", + "clk_cabac"; + resets = <&reset RK3288_SOFT_RST_VCODEC_H>, + <&reset RK3288_SOFT_RST_VCODEC_A>, + <&reset RK3288_SOFT_RST_HEVC>; reset-names = "video_h", "video_a", "video"; dev_mode = <1>; name = "hevc_service"; @@ -1097,12 +1131,16 @@ "GRF_UOC0_BASE", "GRF_UOC1_BASE", "GRF_UOC2_BASE", "GRF_UOC3_BASE", "GRF_UOC4_BASE"; - interrupts = , , - , , + + interrupts = , + , + , + , ; interrupt-names = "otg_id", "otg_bvalid", "otg_linestate", "host0_linestate", "host1_linestate"; + clocks = <&clk_gates7 9>, <&usbphy_480m>, <&otgphy1_480m>, <&otgphy2_480m>; clock-names = "hclk_usb_peri", "usbphy_480m", @@ -1129,8 +1167,9 @@ interrupts = ; clocks = <&clk_gates13 4>, <&clk_gates7 4>; clock-names = "clk_usbphy0", "hclk_usb0"; - resets = <&reset RK3288_SOFT_RST_USBOTG_H>, <&reset RK3288_SOFT_RST_USBOTGPHY>, - <&reset RK3288_SOFT_RST_USBOTGC>; + resets = <&reset RK3288_SOFT_RST_USBOTG_H>, + <&reset RK3288_SOFT_RST_USBOTGPHY>, + <&reset RK3288_SOFT_RST_USBOTGC>; reset-names = "otg_ahb", "otg_phy", "otg_controller"; /*0 - Normal, 1 - Force Host, 2 - Force Device*/ rockchip,usb-mode = <0>; @@ -1144,8 +1183,9 @@ <&usbphy_480m>; clock-names = "clk_usbphy1", "hclk_usb1", "usbphy_480m"; - resets = <&reset RK3288_SOFT_RST_USBHOST1_H>, <&reset RK3288_SOFT_RST_USBHOST1PHY>, - <&reset RK3288_SOFT_RST_USBHOST1C>; + resets = <&reset RK3288_SOFT_RST_USBHOST1_H>, + <&reset RK3288_SOFT_RST_USBHOST1PHY>, + <&reset RK3288_SOFT_RST_USBHOST1C>; reset-names = "host1_ahb", "host1_phy", "host1_controller"; }; @@ -1155,8 +1195,10 @@ interrupts = ; clocks = <&clk_gates13 5>, <&clk_gates7 6>; clock-names = "clk_usbphy2", "hclk_usb2"; - resets = <&reset RK3288_SOFT_RST_USBHOST0_H>, <&reset RK3288_SOFT_RST_USBHOST0PHY>, - <&reset RK3288_SOFT_RST_USBHOST0C>, <&reset RK3288_SOFT_RST_USB_HOST0>; + resets = <&reset RK3288_SOFT_RST_USBHOST0_H>, + <&reset RK3288_SOFT_RST_USBHOST0PHY>, + <&reset RK3288_SOFT_RST_USBHOST0C>, + <&reset RK3288_SOFT_RST_USB_HOST0>; reset-names = "ehci_ahb", "ehci_phy", "ehci_controller", "ehci"; }; @@ -1179,8 +1221,9 @@ clock-names = "ehci1phy_480m", "hclk_ehci1", "ehci1phy_12m", "usbphy_480m", "ehci1_usbphy1", "ehci1_usbphy2"; - resets = <&reset RK3288_SOFT_RST_EHCI1>, <&reset RK3288_SOFT_RST_EHCI1_AUX>, - <&reset RK3288_SOFT_RST_EHCI1PHY>; + resets = <&reset RK3288_SOFT_RST_EHCI1>, + <&reset RK3288_SOFT_RST_EHCI1_AUX>, + <&reset RK3288_SOFT_RST_EHCI1PHY>; reset-names = "ehci1_ahb", "ehci1_aux", "ehci1_phy"; }; @@ -1297,13 +1340,23 @@ compatible = "rockchip,isp"; reg = <0xff910000 0x10000>; interrupts = ; - clocks = <&clk_gates16 2>, <&clk_gates16 1>, <&clk_isp>, <&clk_isp_jpe>, <&clkin_isp>, <&clk_cif_out>, <&clk_gates5 15>, <&clk_cif_pll>, <&pd_isp>, <&clk_gates16 6>; - clock-names = "aclk_isp", "hclk_isp", "clk_isp", "clk_isp_jpe", "pclkin_isp", "clk_cif_out", "clk_mipi_24m", "clk_cif_pll", "pd_isp", "hclk_mipiphy1"; - pinctrl-names = "default", "isp_dvp8bit2", "isp_dvp10bit", "isp_dvp12bit", "isp_dvp8bit0", "isp_mipi_fl", "isp_mipi_fl_prefl","isp_flash_as_gpio","isp_flash_as_trigger_out"; + clocks = <&clk_gates16 2>, <&clk_gates16 1>, <&clk_isp>, + <&clk_isp_jpe>, <&clkin_isp>, <&clk_cif_out>, + <&clk_gates5 15>, <&clk_cif_pll>, <&pd_isp>, + <&clk_gates16 6>; + clock-names = "aclk_isp", "hclk_isp", "clk_isp", + "clk_isp_jpe", "pclkin_isp", "clk_cif_out", + "clk_mipi_24m", "clk_cif_pll", "pd_isp", + "hclk_mipiphy1"; + pinctrl-names = "default", "isp_dvp8bit2", "isp_dvp10bit", + "isp_dvp12bit", "isp_dvp8bit0", "isp_mipi_fl", + "isp_mipi_fl_prefl","isp_flash_as_gpio", + "isp_flash_as_trigger_out"; pinctrl-0 = <&isp_mipi>; pinctrl-1 = <&isp_mipi &isp_dvp_d2d9>; pinctrl-2 = <&isp_mipi &isp_dvp_d2d9 &isp_dvp_d0d1>; - pinctrl-3 = <&isp_mipi &isp_dvp_d2d9 &isp_dvp_d0d1 &isp_dvp_d10d11>; + pinctrl-3 = <&isp_mipi &isp_dvp_d2d9 &isp_dvp_d0d1 + &isp_dvp_d10d11>; pinctrl-4 = <&isp_mipi &isp_dvp_d0d7>; pinctrl-5 = <&isp_mipi>; pinctrl-6 = <&isp_mipi &isp_prelight>; @@ -1316,16 +1369,19 @@ rockchip,isp,iommu_enable = <1>; status = "okay"; }; + cif: cif@ff950000 { - compatible = "rockchip,cif"; - reg = <0xff950000 0x10000>; - interrupts = ; - clocks = <&pd_isp>,<&clk_gates15 14>,<&clk_gates15 15>,<&clkin_cif>,<&clk_gates16 0>,<&clk_cif_out>; - clock-names = "pd_cif0", "aclk_cif0","hclk_cif0","cif0_in","g_pclkin_cif","cif0_out"; - pinctrl-names = "cif_pin_all"; - pinctrl-0 = <&isp_mipi &isp_dvp_d2d9 &isp_dvp_d10d11>; - status = "okay"; - }; + compatible = "rockchip,cif"; + reg = <0xff950000 0x10000>; + interrupts = ; + clocks = <&pd_isp>,<&clk_gates15 14>,<&clk_gates15 15>, + <&clkin_cif>,<&clk_gates16 0>,<&clk_cif_out>; + clock-names = "pd_cif0", "aclk_cif0","hclk_cif0", + "cif0_in","g_pclkin_cif","cif0_out"; + pinctrl-names = "cif_pin_all"; + pinctrl-0 = <&isp_mipi &isp_dvp_d2d9 &isp_dvp_d10d11>; + status = "okay"; + }; tsadc: tsadc@ff280000 { compatible = "rockchip,tsadc";