From: Shawn Lin <shawn.lin@rock-chips.com>
Date: Mon, 9 May 2016 08:04:59 +0000 (+0800)
Subject: Documentation: rockchip-emmc-phy: add ctrl-base support
X-Git-Tag: firefly_0821_release~2654
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=12119b8fddf242dd66c2750b92cc0de4fd055512;p=firefly-linux-kernel-4.4.55.git

Documentation: rockchip-emmc-phy: add ctrl-base support

This patch adds ctrl-base which points to the digital block
to setup phy pll enabling.

Change-Id: I922dd7574229fda6b2ee51ca6ed1d7852ef87d30
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
---

diff --git a/Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt b/Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt
index a962fafc62ba..73eda5620190 100644
--- a/Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt
+++ b/Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt
@@ -8,6 +8,7 @@ Required properties:
  - #phy-cells: must be 0
  - reg-offset: PHY configure reg address offset in "general
    register files"
+ - ctrl-base: controller digital block's physical address.
 
 Optional Properties:
  - freq-sel: must match the freq of emmc clock, only support the
@@ -22,5 +23,6 @@ emmcphy: phy {
 	compatible = "rockchip,rk3399-emmc-phy";
 	rockchip,grf = <&grf>;
 	reg-offset = <0xf780>;
+	ctrl-base = <0xfe330000>;
 	#phy-cells = <0>;
 };