From: zhangqing Date: Thu, 25 Jun 2015 23:50:06 +0000 (-0700) Subject: rk3368: clk: cpll: make cpll low jitter. X-Git-Tag: firefly_0821_release~3967 X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=12a178aad255fb2380cd97e807153844c5dd87b2;p=firefly-linux-kernel-4.4.55.git rk3368: clk: cpll: make cpll low jitter. This modify is for cpll low jitter. Make the signal of clk_gmac better. Signed-off-by: zhangqing --- diff --git a/arch/arm64/boot/dts/rk3368-clocks.dtsi b/arch/arm64/boot/dts/rk3368-clocks.dtsi index 39bda43e4acc..1ef9c5c389c2 100644 --- a/arch/arm64/boot/dts/rk3368-clocks.dtsi +++ b/arch/arm64/boot/dts/rk3368-clocks.dtsi @@ -330,7 +330,7 @@ status-reg = <0x0480 3>; clocks = <&xin24m>; clock-output-names = "clk_cpll"; - rockchip,pll-type = ; + rockchip,pll-type = ; #clock-cells = <0>; #clock-init-cells = <1>; }; diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c index 210254b320c7..325eb2c9167d 100755 --- a/drivers/clk/rockchip/clk-pll.c +++ b/drivers/clk/rockchip/clk-pll.c @@ -332,6 +332,7 @@ static const struct apll_clk_set rk3368_aplll_table[] = { static const struct pll_clk_set rk3368_pll_table_low_jitter[] = { /* _khz, nr, nf, no, nb */ _RK3188PLUS_PLL_SET_CLKS_NB(1188000, 1, 99, 2, 1), + _RK3188PLUS_PLL_SET_CLKS_NB(400000, 1, 100, 6, 1), _RK3188PLUS_PLL_SET_CLKS( 0, 0, 0, 0), };