From: Evan Cheng <evan.cheng@apple.com>
Date: Tue, 11 Apr 2006 17:35:57 +0000 (+0000)
Subject: Misc. intrinsics.
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=135c6a9d838dfd85835eb7756cba81f7dc297db4;p=oota-llvm.git

Misc. intrinsics.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27590 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/include/llvm/IntrinsicsX86.td b/include/llvm/IntrinsicsX86.td
index ca154edcbf2..8bb0d95a4c5 100644
--- a/include/llvm/IntrinsicsX86.td
+++ b/include/llvm/IntrinsicsX86.td
@@ -140,7 +140,8 @@ let TargetPrefix = "x86" in {  // All intrinsics start with "llvm.x86.".
 // Cacheability support ops
 let TargetPrefix = "x86" in {  // All intrinsics start with "llvm.x86.".
   def int_x86_sse_prefetch : GCCBuiltin<"__builtin_ia32_prefetch">,
-              Intrinsic<[llvm_ptr_ty, llvm_int_ty], [IntrWriteMem]>;
+              Intrinsic<[llvm_void_ty, llvm_ptr_ty,
+                         llvm_int_ty], [IntrWriteMem]>;
   def int_x86_sse_movnt_ps : GCCBuiltin<"__builtin_ia32_movntps">,
               Intrinsic<[llvm_void_ty, llvm_ptr_ty,
                          llvm_v4f32_ty], [IntrWriteMem]>;
diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td
index 1ff7562a029..9bb1f743c16 100644
--- a/lib/Target/X86/X86InstrSSE.td
+++ b/lib/Target/X86/X86InstrSSE.td
@@ -1516,18 +1516,18 @@ def MASKMOVDQU : PDI<0xF7, RawFrm, (ops VR128:$src, VR128:$mask),
                  Imp<[EDI],[]>;
 
 // Prefetching loads
-def PREFETCHT0   : I<0x18, MRM1m, (ops i8mem:$src),
-                     "prefetcht0 $src", []>, TB,
-                   Requires<[HasSSE1]>;
-def PREFETCHT1   : I<0x18, MRM2m, (ops i8mem:$src),
-                     "prefetcht0 $src", []>, TB,
-                   Requires<[HasSSE1]>;
-def PREFETCHT2   : I<0x18, MRM3m, (ops i8mem:$src),
-                     "prefetcht0 $src", []>, TB,
-                   Requires<[HasSSE1]>;
-def PREFETCHTNTA : I<0x18, MRM0m, (ops i8mem:$src),
-                     "prefetcht0 $src", []>, TB,
-                   Requires<[HasSSE1]>;
+def PREFETCHT0   : PSI<0x18, MRM1m, (ops i8mem:$src),
+                       "prefetcht0 $src",
+                       [(int_x86_sse_prefetch addr:$src, 1)]>;
+def PREFETCHT1   : PSI<0x18, MRM2m, (ops i8mem:$src),
+                       "prefetcht1 $src",
+                       [(int_x86_sse_prefetch addr:$src, 2)]>;
+def PREFETCHT2   : PSI<0x18, MRM3m, (ops i8mem:$src),
+                       "prefetcht2 $src",
+                       [(int_x86_sse_prefetch addr:$src, 3)]>;
+def PREFETCHTNTA : PSI<0x18, MRM0m, (ops i8mem:$src),
+                       "prefetchtnta $src",
+                       [(int_x86_sse_prefetch addr:$src, 0)]>;
 
 // Non-temporal stores
 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (ops i128mem:$dst, VR128:$src),
@@ -1546,7 +1546,7 @@ def MOVNTImr  :   I<0xC3, MRMDestMem, (ops i32mem:$dst, R32:$src),
 
 // Store fence
 def SFENCE : I<0xAE, MRM7m, (ops),
-               "sfence", []>, TB, Requires<[HasSSE1]>;
+               "sfence", [(int_x86_sse_sfence)]>, TB, Requires<[HasSSE1]>;
 
 // MXCSR register
 def LDMXCSR : I<0xAE, MRM2m, (ops i32mem:$src),