From: Chris Lattner <sabre@nondot.org>
Date: Tue, 30 Aug 2005 18:37:48 +0000 (+0000)
Subject: Fix some indentation (first hunks).
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=1368721d532d0d291a03bb3fff7f94805e5919b6;p=oota-llvm.git

Fix some indentation (first hunks).

Remove code (last hunk) that miscompiled immediate and's, such as
  and uint %tmp.30, 4294958079

into

 andi. r8, r8, 56319
 andis. r8, r8, 65535

instead of:

 li r9, -9217
 and r8, r8, r9

The first always generates zero.

This fixes espresso.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23155 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
index 93e96376b59..2cbf6a2f8bb 100644
--- a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -257,34 +257,33 @@ SDNode *PPC32DAGToDAGISel::SelectBitfieldInsert(SDNode *N) {
   // Generate Mask value for Target
   if (isIntImmediate(Op0.getOperand(1), Value)) {
     switch(Op0Opc) {
-      case ISD::SHL: TgtMask <<= Value; break;
-      case ISD::SRL: TgtMask >>= Value; break;
-      case ISD::AND: TgtMask &= Value; break;
+    case ISD::SHL: TgtMask <<= Value; break;
+    case ISD::SRL: TgtMask >>= Value; break;
+    case ISD::AND: TgtMask &= Value; break;
     }
   } else {
     return 0;
   }
   
   // Generate Mask value for Insert
-  if (isIntImmediate(Op1.getOperand(1), Value)) {
-    switch(Op1Opc) {
-      case ISD::SHL:
-        SH = Value;
-        InsMask <<= SH;
-        if (Op0Opc == ISD::SRL) IsRotate = true;
-          break;
-      case ISD::SRL:
-        SH = Value;
-        InsMask >>= SH;
-        SH = 32-SH;
-        if (Op0Opc == ISD::SHL) IsRotate = true;
-          break;
-      case ISD::AND:
-        InsMask &= Value;
-        break;
-    }
-  } else {
+  if (!isIntImmediate(Op1.getOperand(1), Value))
     return 0;
+  
+  switch(Op1Opc) {
+  case ISD::SHL:
+    SH = Value;
+    InsMask <<= SH;
+    if (Op0Opc == ISD::SRL) IsRotate = true;
+    break;
+  case ISD::SRL:
+    SH = Value;
+    InsMask >>= SH;
+    SH = 32-SH;
+    if (Op0Opc == ISD::SHL) IsRotate = true;
+    break;
+  case ISD::AND:
+    InsMask &= Value;
+    break;
   }
   
   // If both of the inputs are ANDs and one of them has a logical shift by
@@ -979,15 +978,6 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
                            getI32Imm(MB), getI32Imm(ME));
       break;
     }
-    // If this is an and with an immediate that isn't a mask, then codegen it as
-    // high and low 16 bit immediate ands.
-    if (SDNode *I = SelectIntImmediateExpr(N->getOperand(0), 
-                                           N->getOperand(1),
-                                           PPC::ANDISo, PPC::ANDIo)) {
-      CurDAG->ReplaceAllUsesWith(Op, SDOperand(I, 0));
-      N = I;
-      break;
-    }
     // Finally, check for the case where we are being asked to select
     // and (not(a), b) or and (a, not(b)) which can be selected as andc.
     if (isOprNot(N->getOperand(0).Val))