From: Jason Wang Date: Sat, 21 Aug 2010 08:24:05 +0000 (+0800) Subject: ARM: imx: set cache line size to 64 bytes for i.MX5 X-Git-Tag: firefly_0821_release~9833^2~590^2~8^2 X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=14f0f512ba6f4eccc9b7cf67be47439ed2917afb;p=firefly-linux-kernel-4.4.55.git ARM: imx: set cache line size to 64 bytes for i.MX5 The core of i.MX5 series is cortex-A8, its cache line size is 64 bytes instead of 32 bytes. Refer to the OMAP3's selection, we choose 64 bytes for i.MX5, this can increase a little bit performance when perform cache operations. Signed-off-by: Jason Wang Signed-off-by: Sascha Hauer --- diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig index 0527e65318f4..6785db4179b8 100644 --- a/arch/arm/plat-mxc/Kconfig +++ b/arch/arm/plat-mxc/Kconfig @@ -43,6 +43,7 @@ config ARCH_MXC91231 config ARCH_MX5 bool "MX5-based" select CPU_V7 + select ARM_L1_CACHE_SHIFT_6 help This enables support for systems based on the Freescale i.MX51 family