From: Feng Xiao <xf@rock-chips.com>
Date: Wed, 2 Mar 2016 15:15:31 +0000 (+0800)
Subject: ARM64: dts: rockchip: rk3366: add initial clock rate for plls
X-Git-Tag: firefly_0821_release~3319
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=16a036448ac53ec1aecf44d607339c8db2666ad8;p=firefly-linux-kernel-4.4.55.git

ARM64: dts: rockchip: rk3366: add initial clock rate for plls

Change-Id: I9ea6bcac10a7b67471613aea3ea41aff44a8fe34
Signed-off-by: Feng Xiao <xf@rock-chips.com>
---

diff --git a/arch/arm64/boot/dts/rockchip/rk3366.dtsi b/arch/arm64/boot/dts/rockchip/rk3366.dtsi
index 734aa7d1300a..23e2134ec237 100644
--- a/arch/arm64/boot/dts/rockchip/rk3366.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3366.dtsi
@@ -545,6 +545,14 @@
 		rockchip,grf = <&grf>;
 		#clock-cells = <1>;
 		#reset-cells = <1>;
+		assigned-clocks =
+			<&cru PLL_CPLL>, <&cru PLL_GPLL>,
+			<&cru PLL_NPLL>, <&cru PLL_MPLL>,
+			<&cru PLL_WPLL>, <&cru PLL_BPLL>;
+		assigned-clock-rates =
+			<750000000>, <576000000>,
+			<594000000>, <594000000>,
+			<480000000>, <520000000>;
 	};
 
 	grf: syscon@ff770000 {