From: Jim Grosbach Date: Tue, 9 Nov 2010 19:22:26 +0000 (+0000) Subject: Trailing whitespace. X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=16cb3763c5a1dad7d6bcbf0fffdfc58c84b46f89;p=oota-llvm.git Trailing whitespace. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118606 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/ARM/ARMFastISel.cpp b/lib/Target/ARM/ARMFastISel.cpp index a2cce9d28df..a4d98ebf007 100644 --- a/lib/Target/ARM/ARMFastISel.cpp +++ b/lib/Target/ARM/ARMFastISel.cpp @@ -956,7 +956,7 @@ bool ARMFastISel::SelectBranch(const Instruction *I) { MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)]; // Simple branch support. - + // If we can, avoid recomputing the compare - redoing it could lead to wonky // behavior. // TODO: Factor this out. @@ -1005,13 +1005,13 @@ bool ARMFastISel::SelectBranch(const Instruction *I) { AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc)) .addReg(Arg1).addReg(Arg2)); - + // For floating point we need to move the result to a comparison register // that we can then use for branches. if (isFloat) AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::FMSTAT))); - + unsigned BrOpc = isThumb ? ARM::t2Bcc : ARM::Bcc; BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc)) .addMBB(TBB).addImm(ARMPred).addReg(ARM::CPSR); @@ -1020,7 +1020,7 @@ bool ARMFastISel::SelectBranch(const Instruction *I) { return true; } } - + unsigned CmpReg = getRegForValue(BI->getCondition()); if (CmpReg == 0) return false; @@ -1826,10 +1826,10 @@ namespace llvm { llvm::FastISel *ARM::createFastISel(FunctionLoweringInfo &funcInfo) { // Completely untested on non-darwin. const TargetMachine &TM = funcInfo.MF->getTarget(); - + // Darwin and thumb1 only for now. const ARMSubtarget *Subtarget = &TM.getSubtarget(); - if (Subtarget->isTargetDarwin() && !Subtarget->isThumb1Only() && + if (Subtarget->isTargetDarwin() && !Subtarget->isThumb1Only() && !DisableARMFastISel) return new ARMFastISel(funcInfo); return 0;