From: Simon Pilgrim Date: Thu, 19 Nov 2015 12:18:37 +0000 (+0000) Subject: [X86][AVX] Fix lowering of X86ISD::VZEXT_MOVL for 128-bit -> 256-bit extension X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=175ea25f68a3eb84a917e004dd3b12352d3ae281;p=oota-llvm.git [X86][AVX] Fix lowering of X86ISD::VZEXT_MOVL for 128-bit -> 256-bit extension The lowering patterns for X86ISD::VZEXT_MOVL for 128-bit to 256-bit vectors were just copying the lower xmm instead of actually masking off the first scalar using a blend. Fix for PR25320. Differential Revision: http://reviews.llvm.org/D14151 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253561 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td index 401fffaa22a..fd829e1b189 100644 --- a/lib/Target/X86/X86InstrSSE.td +++ b/lib/Target/X86/X86InstrSSE.td @@ -935,22 +935,6 @@ let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, IIC_SSE_MOVU_P_RR>, VEX, VEX_L; } -let Predicates = [HasAVX] in { -def : Pat<(v8i32 (X86vzmovl - (insert_subvector undef, (v4i32 VR128:$src), (iPTR 0)))), - (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>; -def : Pat<(v4i64 (X86vzmovl - (insert_subvector undef, (v2i64 VR128:$src), (iPTR 0)))), - (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>; -def : Pat<(v8f32 (X86vzmovl - (insert_subvector undef, (v4f32 VR128:$src), (iPTR 0)))), - (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>; -def : Pat<(v4f64 (X86vzmovl - (insert_subvector undef, (v2f64 VR128:$src), (iPTR 0)))), - (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>; -} - - def : Pat<(int_x86_avx_storeu_ps_256 addr:$dst, VR256:$src), (VMOVUPSYmr addr:$dst, VR256:$src)>; def : Pat<(int_x86_avx_storeu_pd_256 addr:$dst, VR256:$src), @@ -2934,7 +2918,7 @@ multiclass sse12_fp_packed_vector_logical_alias< defm V#NAME#PSY : sse12_fp_packed, PS, VEX_4V, VEX_L; - + defm V#NAME#PDY : sse12_fp_packed, PD, VEX_4V, VEX_L; @@ -4191,7 +4175,7 @@ defm VPSRADY : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai, SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L; }// Predicates = [HasAVX2] -let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift], hasSideEffects = 0 , +let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift], hasSideEffects = 0 , Predicates = [HasAVX2, NoVLX_Or_NoBWI] in { // 256-bit logical shifts. def VPSLLDQYri : PDIi8<0x73, MRM7r, diff --git a/test/CodeGen/X86/vec_extract-avx.ll b/test/CodeGen/X86/vec_extract-avx.ll index fbb84170dc8..ea34fde4a0e 100644 --- a/test/CodeGen/X86/vec_extract-avx.ll +++ b/test/CodeGen/X86/vec_extract-avx.ll @@ -5,7 +5,7 @@ target triple = "x86_64-unknown-unknown" ; When extracting multiple consecutive elements from a larger ; vector into a smaller one, do it efficiently. We should use ; an EXTRACT_SUBVECTOR node internally rather than a bunch of -; single element extractions. +; single element extractions. ; Extracting the low elements only requires using the right kind of store. define void @low_v8f32_to_v4f32(<8 x float> %v, <4 x float>* %ptr) { @@ -26,7 +26,7 @@ define void @low_v8f32_to_v4f32(<8 x float> %v, <4 x float>* %ptr) { ; CHECK-NEXT: retq } -; Extracting the high elements requires just one AVX instruction. +; Extracting the high elements requires just one AVX instruction. define void @high_v8f32_to_v4f32(<8 x float> %v, <4 x float>* %ptr) { %ext0 = extractelement <8 x float> %v, i32 4 %ext1 = extractelement <8 x float> %v, i32 5 @@ -80,3 +80,70 @@ define void @high_v4f64_to_v2f64(<4 x double> %v, <2 x double>* %ptr) { ; CHECK-NEXT: vzeroupper ; CHECK-NEXT: retq } + +; PR25320 Make sure that a widened (possibly legalized) vector correctly zero-extends upper elements. +; FIXME - Ideally these should just call VMOVD/VMOVQ/VMOVSS/VMOVSD + +define void @legal_vzmovl_2i32_8i32(<2 x i32>* %in, <8 x i32>* %out) { + %ld = load <2 x i32>, <2 x i32>* %in, align 8 + %ext = extractelement <2 x i32> %ld, i64 0 + %ins = insertelement <8 x i32> , i32 %ext, i64 0 + store <8 x i32> %ins, <8 x i32>* %out, align 32 + ret void + +; CHECK-LABEL: legal_vzmovl_2i32_8i32 +; CHECK: vpmovzxdq {{.*#+}} xmm0 = mem[0],zero,mem[1],zero +; CHECK-NEXT: vxorps %ymm1, %ymm1, %ymm1 +; CHECK-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3,4,5,6,7] +; CHECK-NEXT: vmovaps %ymm0, (%rsi) +; CHECK-NEXT: vzeroupper +; CHECK-NEXT: retq +} + +define void @legal_vzmovl_2i64_4i64(<2 x i64>* %in, <4 x i64>* %out) { + %ld = load <2 x i64>, <2 x i64>* %in, align 8 + %ext = extractelement <2 x i64> %ld, i64 0 + %ins = insertelement <4 x i64> , i64 %ext, i64 0 + store <4 x i64> %ins, <4 x i64>* %out, align 32 + ret void + +; CHECK-LABEL: legal_vzmovl_2i64_4i64 +; CHECK: vmovupd (%rdi), %xmm0 +; CHECK-NEXT: vxorpd %ymm1, %ymm1, %ymm1 +; CHECK-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3] +; CHECK-NEXT: vmovapd %ymm0, (%rsi) +; CHECK-NEXT: vzeroupper +; CHECK-NEXT: retq +} + +define void @legal_vzmovl_2f32_8f32(<2 x float>* %in, <8 x float>* %out) { + %ld = load <2 x float>, <2 x float>* %in, align 8 + %ext = extractelement <2 x float> %ld, i64 0 + %ins = insertelement <8 x float> , float %ext, i64 0 + store <8 x float> %ins, <8 x float>* %out, align 32 + ret void + +; CHECK-LABEL: legal_vzmovl_2f32_8f32 +; CHECK: vmovq {{.*#+}} xmm0 = mem[0],zero +; CHECK-NEXT: vxorps %ymm1, %ymm1, %ymm1 +; CHECK-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3,4,5,6,7] +; CHECK-NEXT: vmovaps %ymm0, (%rsi) +; CHECK-NEXT: vzeroupper +; CHECK-NEXT: retq +} + +define void @legal_vzmovl_2f64_4f64(<2 x double>* %in, <4 x double>* %out) { + %ld = load <2 x double>, <2 x double>* %in, align 8 + %ext = extractelement <2 x double> %ld, i64 0 + %ins = insertelement <4 x double> , double %ext, i64 0 + store <4 x double> %ins, <4 x double>* %out, align 32 + ret void + +; CHECK-LABEL: legal_vzmovl_2f64_4f64 +; CHECK: vmovupd (%rdi), %xmm0 +; CHECK-NEXT: vxorpd %ymm1, %ymm1, %ymm1 +; CHECK-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3] +; CHECK-NEXT: vmovapd %ymm0, (%rsi) +; CHECK-NEXT: vzeroupper +; CHECK-NEXT: retq +}