From: Bill Wendling <isanbard@gmail.com>
Date: Fri, 30 Jul 2010 22:48:39 +0000 (+0000)
Subject: Add a "Compare" flag to the target instruction descriptor. This will be used
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=1844b1a5a483b8f01f29500a8d0d552447cbb7e5;p=oota-llvm.git

Add a "Compare" flag to the target instruction descriptor. This will be used
later to identify and possibly remove superfluous compare instructions -- those
that are testing for and setting a status flag that should already be set.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109901 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/include/llvm/Target/Target.td b/include/llvm/Target/Target.td
index ad1a816a95c..809e088e2b0 100644
--- a/include/llvm/Target/Target.td
+++ b/include/llvm/Target/Target.td
@@ -198,6 +198,7 @@ class Instruction {
   bit isReturn     = 0;     // Is this instruction a return instruction?
   bit isBranch     = 0;     // Is this instruction a branch instruction?
   bit isIndirectBranch = 0; // Is this instruction an indirect branch?
+  bit isCompare    = 0;     // Is this instruction a comparison instruction?
   bit isBarrier    = 0;     // Can control flow fall through this instruction?
   bit isCall       = 0;     // Is this instruction a call instruction?
   bit canFoldAsLoad = 0;    // Can this be folded as a simple memory operand?
diff --git a/include/llvm/Target/TargetInstrDesc.h b/include/llvm/Target/TargetInstrDesc.h
index 8f0a6cb1a68..6a08e8f24c0 100644
--- a/include/llvm/Target/TargetInstrDesc.h
+++ b/include/llvm/Target/TargetInstrDesc.h
@@ -105,6 +105,7 @@ namespace TID {
     IndirectBranch,
     Predicable,
     NotDuplicable,
+    Compare,
     DelaySlot,
     FoldableAsLoad,
     MayLoad,
@@ -315,7 +316,7 @@ public:
   bool isIndirectBranch() const {
     return Flags & (1 << TID::IndirectBranch);
   }
-  
+
   /// isConditionalBranch - Return true if this is a branch which may fall
   /// through to the next instruction or may transfer control flow to some other
   /// block.  The TargetInstrInfo::AnalyzeBranch method can be used to get more
@@ -340,6 +341,11 @@ public:
     return Flags & (1 << TID::Predicable);
   }
   
+  /// isCompare - Return true if this instruction is a comparison.
+  bool isCompare() const {
+    return Flags & (1 << TID::Compare);
+  }
+  
   /// isNotDuplicable - Return true if this instruction cannot be safely
   /// duplicated.  For example, if the instruction has a unique labels attached
   /// to it, duplicating it would cause multiple definition errors.
diff --git a/utils/TableGen/CodeGenInstruction.cpp b/utils/TableGen/CodeGenInstruction.cpp
index 35b54a54271..01a1fe11f53 100644
--- a/utils/TableGen/CodeGenInstruction.cpp
+++ b/utils/TableGen/CodeGenInstruction.cpp
@@ -102,6 +102,7 @@ CodeGenInstruction::CodeGenInstruction(Record *R, const std::string &AsmStr)
   isReturn     = R->getValueAsBit("isReturn");
   isBranch     = R->getValueAsBit("isBranch");
   isIndirectBranch = R->getValueAsBit("isIndirectBranch");
+  isCompare    = R->getValueAsBit("isCompare");
   isBarrier    = R->getValueAsBit("isBarrier");
   isCall       = R->getValueAsBit("isCall");
   canFoldAsLoad = R->getValueAsBit("canFoldAsLoad");
diff --git a/utils/TableGen/CodeGenInstruction.h b/utils/TableGen/CodeGenInstruction.h
index 946c2d01a52..b02d0d38f97 100644
--- a/utils/TableGen/CodeGenInstruction.h
+++ b/utils/TableGen/CodeGenInstruction.h
@@ -123,6 +123,7 @@ namespace llvm {
     bool isReturn;
     bool isBranch;
     bool isIndirectBranch;
+    bool isCompare;
     bool isBarrier;
     bool isCall;
     bool canFoldAsLoad;
diff --git a/utils/TableGen/InstrInfoEmitter.cpp b/utils/TableGen/InstrInfoEmitter.cpp
index f28af1589d6..4d3aa5e621c 100644
--- a/utils/TableGen/InstrInfoEmitter.cpp
+++ b/utils/TableGen/InstrInfoEmitter.cpp
@@ -270,6 +270,7 @@ void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
   if (Inst.isReturn)           OS << "|(1<<TID::Return)";
   if (Inst.isBranch)           OS << "|(1<<TID::Branch)";
   if (Inst.isIndirectBranch)   OS << "|(1<<TID::IndirectBranch)";
+  if (Inst.isCompare)          OS << "|(1<<TID::Compare)";
   if (Inst.isBarrier)          OS << "|(1<<TID::Barrier)";
   if (Inst.hasDelaySlot)       OS << "|(1<<TID::DelaySlot)";
   if (Inst.isCall)             OS << "|(1<<TID::Call)";