From: Jack Carter Date: Mon, 2 Jul 2012 22:39:45 +0000 (+0000) Subject: mips32 long long register inline asm constraint support. X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=1b055ce320fa13f6f1ac81670d11b45e01f79876;p=oota-llvm.git mips32 long long register inline asm constraint support. inlineasm-cnstrnt-bad-r-1.ll is NOT supposed to fail, so it was removed. This resulted in the removal of a negative test (inlineasm-cnstrnt-bad-r-1.ll) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159610 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/Mips/MipsISelLowering.cpp b/lib/Target/Mips/MipsISelLowering.cpp index abf22bd8041..a7e2aa32fc6 100644 --- a/lib/Target/Mips/MipsISelLowering.cpp +++ b/lib/Target/Mips/MipsISelLowering.cpp @@ -3355,6 +3355,8 @@ getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const case 'r': if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) return std::make_pair(0U, &Mips::CPURegsRegClass); + if (VT == MVT::i64 && !HasMips64) + return std::make_pair(0U, &Mips::CPURegsRegClass); if (VT == MVT::i64 && HasMips64) return std::make_pair(0U, &Mips::CPU64RegsRegClass); // This will generate an error message diff --git a/test/CodeGen/Mips/inlineasm-operand-code.ll b/test/CodeGen/Mips/inlineasm-operand-code.ll index ca4f3e4c5ae..d75f7f2f806 100644 --- a/test/CodeGen/Mips/inlineasm-operand-code.ll +++ b/test/CodeGen/Mips/inlineasm-operand-code.ll @@ -41,5 +41,11 @@ entry: ;CHECK: #NO_APP tail call i32 asm sideeffect "addi $0,$1,${2:z}", "=r,r,I"(i32 7, i32 0) nounwind +; a long long in 32 bit mode (use to assert) +;CHECK: #APP +;CHECK: addi ${{[0-9]+}},${{[0-9]+}},3 +;CHECK: #NO_APP + tail call i64 asm sideeffect "addi $0,$1,$2 \0A\09", "=r,r,X"(i64 1229801703532086340, i64 3) nounwind + ret i32 0 }