From: WeiYong Bi <bivvy.bi@rock-chips.com>
Date: Mon, 27 Mar 2017 23:51:03 +0000 (+0800)
Subject: phy: rockchip-dp: fix unexpected reset 24m clock
X-Git-Tag: firefly_0821_release~212
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=1cba569fb5490254d67a5dda4886bc394aefa740;p=firefly-linux-kernel-4.4.55.git

phy: rockchip-dp: fix unexpected reset 24m clock

Reset_control_assert/reset_control_deassert will not check whether
the incoming pointer is NULL, so we need to check it before using it.

Change-Id: Ib2aeeefcb2d5d7429031bc21bf7e3df1d897a6c9
Signed-off-by: WeiYong Bi <bivvy.bi@rock-chips.com>
---

diff --git a/drivers/phy/phy-rockchip-dp.c b/drivers/phy/phy-rockchip-dp.c
index 79576e99ab3e..07136c7b1fe0 100644
--- a/drivers/phy/phy-rockchip-dp.c
+++ b/drivers/phy/phy-rockchip-dp.c
@@ -43,11 +43,13 @@ static int rockchip_set_phy_state(struct phy *phy, bool enable)
 	int ret;
 
 	if (enable) {
-		/* EDP 24m clock domain software reset request. */
-		reset_control_assert(dp->rst_24m);
-		usleep_range(20, 40);
-		reset_control_deassert(dp->rst_24m);
-		usleep_range(20, 40);
+		if (dp->rst_24m) {
+			/* EDP 24m clock domain software reset request. */
+			reset_control_assert(dp->rst_24m);
+			usleep_range(20, 40);
+			reset_control_deassert(dp->rst_24m);
+			usleep_range(20, 40);
+		}
 
 		ret = regmap_write(dp->grf, drv_data->grf_reg_offset,
 				   drv_data->siddq_on);