From: Hal Finkel <hfinkel@anl.gov>
Date: Sat, 11 Apr 2015 13:40:36 +0000 (+0000)
Subject: [PowerPC] Disable part-word atomics on the P7
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=1cea397876184dc2e200fb2c86ceff396e86d60e;p=oota-llvm.git

[PowerPC] Disable part-word atomics on the P7

As it turns out, even though these are part of ISA 2.06, the P7 does not
support them (or, at least, not any P7s we're tested so far).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234686 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/PowerPC/PPC.td b/lib/Target/PowerPC/PPC.td
index e8c82399a6f..1a02bcca936 100644
--- a/lib/Target/PowerPC/PPC.td
+++ b/lib/Target/PowerPC/PPC.td
@@ -163,12 +163,12 @@ def ProcessorFeatures {
        FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX,
        FeatureFPRND, FeatureFPCVT, FeatureISEL,
        FeaturePOPCNTD, FeatureCMPB, FeatureLDBRX,
-       Feature64Bit /*, Feature64BitRegs */, FeaturePartwordAtomic,
+       Feature64Bit /*, Feature64BitRegs */,
        FeatureBPERMD, FeatureExtDiv,
        DeprecatedMFTB, DeprecatedDST];
   list<SubtargetFeature> Power8SpecificFeatures =
       [DirectivePwr8, FeatureP8Altivec, FeatureP8Vector, FeatureP8Crypto,
-       FeatureHTM, FeatureDirectMove, FeatureICBT];
+       FeatureHTM, FeatureDirectMove, FeatureICBT, FeaturePartwordAtomic];
   list<SubtargetFeature> Power8FeatureList =
       !listconcat(Power7FeatureList, Power8SpecificFeatures);
 }
diff --git a/test/CodeGen/PowerPC/atomic-2.ll b/test/CodeGen/PowerPC/atomic-2.ll
index 9130921a0f1..b4b95a2baab 100644
--- a/test/CodeGen/PowerPC/atomic-2.ll
+++ b/test/CodeGen/PowerPC/atomic-2.ll
@@ -1,6 +1,6 @@
 ; RUN: llc < %s -march=ppc64 | FileCheck %s
-; RUN: llc < %s -march=ppc64 -mcpu=pwr7 | FileCheck %s -check-prefix=CHECK-P7U
-; RUN: llc < %s -march=ppc64 -mcpu=pwr8 | FileCheck %s -check-prefix=CHECK-P7U
+; RUN: llc < %s -march=ppc64 -mcpu=pwr7 | FileCheck %s
+; RUN: llc < %s -march=ppc64 -mcpu=pwr8 | FileCheck %s -check-prefix=CHECK-P8U
 
 define i64 @exchange_and_add(i64* %mem, i64 %val) nounwind {
 ; CHECK-LABEL: exchange_and_add:
@@ -12,17 +12,17 @@ define i64 @exchange_and_add(i64* %mem, i64 %val) nounwind {
 
 define i8 @exchange_and_add8(i8* %mem, i8 %val) nounwind {
 ; CHECK-LABEL: exchange_and_add8:
-; CHECK-P7U: lbarx
+; CHECK-P8U: lbarx
   %tmp = atomicrmw add i8* %mem, i8 %val monotonic
-; CHECK-P7U: stbcx.
+; CHECK-P8U: stbcx.
   ret i8 %tmp
 }
 
 define i16 @exchange_and_add16(i16* %mem, i16 %val) nounwind {
 ; CHECK-LABEL: exchange_and_add16:
-; CHECK-P7U: lharx
+; CHECK-P8U: lharx
   %tmp = atomicrmw add i16* %mem, i16 %val monotonic
-; CHECK-P7U: sthcx.
+; CHECK-P8U: sthcx.
   ret i16 %tmp
 }
 
@@ -38,21 +38,21 @@ define i64 @exchange_and_cmp(i64* %mem) nounwind {
 
 define i8 @exchange_and_cmp8(i8* %mem) nounwind {
 ; CHECK-LABEL: exchange_and_cmp8:
-; CHECK-P7U: lbarx
+; CHECK-P8U: lbarx
   %tmppair = cmpxchg i8* %mem, i8 0, i8 1 monotonic monotonic
   %tmp = extractvalue { i8, i1 } %tmppair, 0
-; CHECK-P7U: stbcx.
-; CHECK-P7U: stbcx.
+; CHECK-P8U: stbcx.
+; CHECK-P8U: stbcx.
   ret i8 %tmp
 }
 
 define i16 @exchange_and_cmp16(i16* %mem) nounwind {
 ; CHECK-LABEL: exchange_and_cmp16:
-; CHECK-P7U: lharx
+; CHECK-P8U: lharx
   %tmppair = cmpxchg i16* %mem, i16 0, i16 1 monotonic monotonic
   %tmp = extractvalue { i16, i1 } %tmppair, 0
-; CHECK-P7U: sthcx.
-; CHECK-P7U: sthcx.
+; CHECK-P8U: sthcx.
+; CHECK-P8U: sthcx.
   ret i16 %tmp
 }
 
@@ -66,17 +66,17 @@ define i64 @exchange(i64* %mem, i64 %val) nounwind {
 
 define i8 @exchange8(i8* %mem, i8 %val) nounwind {
 ; CHECK-LABEL: exchange8:
-; CHECK-P7U: lbarx
+; CHECK-P8U: lbarx
   %tmp = atomicrmw xchg i8* %mem, i8 1 monotonic
-; CHECK-P7U: stbcx.
+; CHECK-P8U: stbcx.
   ret i8 %tmp
 }
 
 define i16 @exchange16(i16* %mem, i16 %val) nounwind {
 ; CHECK-LABEL: exchange16:
-; CHECK-P7U: lharx
+; CHECK-P8U: lharx
   %tmp = atomicrmw xchg i16* %mem, i16 1 monotonic
-; CHECK-P7U: sthcx.
+; CHECK-P8U: sthcx.
   ret i16 %tmp
 }