From: Chris Lattner
Date: Wed, 6 Apr 2011 00:45:11 +0000 (+0000)
Subject: distribute content out to the appropriate sections
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=1efe27eb797144ba4488e7b771fdd9611ee5cd0e;p=oota-llvm.git
distribute content out to the appropriate sections
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128968 91177308-0d34-0410-b5e6-96231b3b80d8
---
diff --git a/docs/ReleaseNotes.html b/docs/ReleaseNotes.html
index b25f1ae1423..719346992b7 100644
--- a/docs/ReleaseNotes.html
+++ b/docs/ReleaseNotes.html
@@ -102,7 +102,7 @@ standards, fast compilation, and low memory use. Like LLVM, Clang provides a
modular, library-based architecture that makes it suitable for creating or
integrating with other development tools. Clang is considered a
production-quality compiler for C, Objective-C, C++ and Objective-C++ on x86
-(32- and 64-bit), and for darwin-arm targets.
+(32- and 64-bit), and for darwin/arm targets.
In the LLVM 2.9 time-frame, the Clang team has made many improvements in C,
C++ and Objective-C support. C++ support is now generally rock solid, has
@@ -293,137 +293,80 @@ in this section.
LLVM 2.9 includes several major new capabilities:
-New Nvidia PTX backend, not generally useful in 2.9 though.
+
-Much better debug info generated, particularly in optimized code situations.
+
+
-ARM Fast ISel
+
+
LLVM IR has several new features for better support of new targets and that
+expose new optimization opportunities:
-ELF MC support: on by default in clang. There are still known missing features
- for human written assembly.
+
+- udiv, ashr, lshr, shl now have exact and nuw/nsw bits:
+ PR8862 / LangRef.html
+
+ unnamed_addr + PR8927
-X86: Reimplemented all of MMX to introduce a new LLVM IR x86_mmx type. Now
- random types like <2 x i32> are not iseld to mmx without emms. The
- -disable-mmx flag is gone now.
+ new 'hotpatch' attribute: LangRef.html#fnattrs
-Some basic internals documentation for MC.
-
-MC Assembler support for .file and .loc.
-
-
-inline asm multiple alternative constraint support.
-
-LoopIdiom: memset/memcpy formation and memset_pattern on darwin. Build with
- -ffreestanding or -fno-builtin if your memcpy is being compiled into infinite
- recursion.
-
+
-TargetLibraryInfo
-
-X86 support for FS/GS relative loads and stores using address space 256/257 are
- reliable now.
-
-ARM: New code placement pass.
-
-unnamed_addr + PR8927
-
-PointerTracking has been removed from mainline, moved to ClamAV.
-
-EarlyCSE pass.
-LoopInstSimplify pass.
+
-- DIBuilder provides simpler interface for front ends like Clang to encode debug info in LLVM IR.
- - This interface hides implementation details (e.g. DIDerivedType, existence of compile unit etc..) that any front end should not know about.
- For example, DIFactory DebugFactory;
- Ty = DebugFactory.CreateDerivedType(DW_TAG_volatile_type,
- findRegion(TYPE_CONTEXT(type)),
- StringRef(),
- getOrCreateFile(main_input_filename),
- 0 /*line no*/,
- NodeSizeInBits(type),
- NodeAlignInBits(type),
- 0 /*offset */,
- 0 /* flags */,
- MainTy);
- can be replaced by
- DbgTy = DBuilder.createQualifiedType(DW_TAG_volatile_type, MainTy);
-DIFactory is gone now.
-
-PPC: Switched to MCInstPrinter, and MCCodeEmitter. Ready to implement support
- for directly writing out mach-o object files, but noone seems interested.
+
+
-ARM: Improved code generation for Cortex-A8 and Cortex-A9 CPUs.
-
-Scheduler now models operand latency and pipeline forwarding.
-
-Can optimize printf to iprintf when no floating point is used, for embedded
- targets with smaller iprintf implementation.
-
-error_code + libsystem + PathV2 changes
- The system_error header from C++0x was added.
- * Use if (error_code ec = function()) to check for error conditions
- from functions which return it.
- * error_code::message returns a human readable description of the error.
-
- PathV1 has been deprecated in favor of PathV2 (sorry I didn't finish
- this before the release).
- * No Path class, use a r-value convertible to a twine instead.
- * Assumes all paths are UTF-8.
-
-new macho-dump tool
+
-Major regalloc rewrite, not on by default for 2.9 and not advised to use it.
- * New basic register allocator that can be used as a safe fallback when
- debugging. Enable with -regalloc=basic.
- * New infrastructure for live range splitting. SplitKit can break a live
- interval into smaller pieces while preserving SSA form, and SpillPlacement
- can help find the best split points. This is a work in progress so the API
- is changing quickly.
- * The inline spiller has learned to clean up after live range splitting. It
- can hoist spills out of loops, and it can eliminate redundant spills.
- Rematerialization works with live range splitting.
- * New greedy register allocator using live range splitting. This will be the
- default register allocator in the next LLVM release, but it is not turned on
- by default in 2.9.
+
In addition to a large array of minor performance tweaks and bug fixes, this
+release includes a few major enhancements and additions to the optimizers:
-ARM: __builtin_prefetch turns into prefetch instructions.
-
-MC assembler support for 3dNow! and 3DNowA instructions.
+
+ - LTO has been improved to use MC for parsing inline asm and now
+ can build large programs like Firefox 4 on both OS X and Linux.
-tblgen support for assembler aliases: MnemonicAlias and InstAlias
-LoopIndexSplit pass was removed, unmaintained.
-LiveValues, SimplifyHalfPowrLibCalls, and GEPSplitter were removed.
+ LoopIdiom: memset/memcpy formation and memset_pattern on darwin. Build with
+ -ffreestanding or -fno-builtin if your memcpy is being compiled into infinite
+ recursion.
-include/llvm/System merged into include/llvm/Support.
-
-Win32 PE-COFF support in the MC assembler has made a lot of progress in the 2.9
- timeframe, but is still not generally useful. Please see
- "http://llvm.org/bugs/showdependencytree.cgi?id=9100&hide_resolved=1" for open bugs?
-
+ TargetLibraryInfo
+
+ EarlyCSE pass.
+ LoopInstSimplify pass.
+
New RegionPass infrastructure
for region-based optimizations.
-MicroBlaze: major updates for aggressive delay slot filler, MC-based assembly
- printing, assembly instruction parsing, ELF .o file emission, and MC
- instruction disassembler.
-
-Countless ARM microoptimizations.
+ Can optimize printf to iprintf when no floating point is used, for embedded
+ targets with smaller iprintf implementation.
Speedups to various mid-level passes:
GVN is much faster on functions with deep dominator trees / lots of BBs.
@@ -431,18 +374,9 @@ Speedups to various mid-level passes:
more passes (so they are computed less often)
SRoA is also much faster and doesn't use DominanceFrontier.
-
-new 'hotpatch' attribute: LangRef.html#fnattrs
-
-APInt API changes, see PR5207.
-
DSE is more aggressive with stores of different types: e.g. a large store
following a small one to the same address.
-New naming rules in coding standards: CodingStandards.html#ll_naming
-
-LiveDebugVariables is a new pass that keeps track of debugging information for
- user variables that are kept in registers in optimized builds.
We now optimize various idioms for overflow detection into check of the flag
register on various CPUs, e.g.:
@@ -452,69 +386,7 @@ We now optimize various idioms for overflow detection into check of the flag
addq %rdi, %rbx
jno LBB0_2
-X86: Much better codegen for several cases using adc/sbb instead of cmovs for
- conditional increment and other idioms.
-
-MVT::Flag renamed to MVT::Glue
-
-Removed the PartialSpecialization pass, it was unmaintained and buggy.
-
-SPARC: Many improvements, including using the Y registers for multiplications
- and addition of a simple delay slot filler.
-
-
-udiv, ashr, lshr, shl now have exact and nuw/nsw bits: PR8862 / LangRef.html
-
-lib/Object and llvm-objdump
-
-
- Target Independent Code Gen:
- The pre-register-allocation (preRA) instruction scheduler models register pressure
- much more accurately in some cases. This allows the adoption of more
- aggressive scheduling heuristics.
- The X86 backend has adopted a new preRA scheduling
- mode, "list-ilp", to shorten the height of instruction schedules
- without inducing register spills.
-
- The ARM backend preRA scheduler now models machine resources at cycle
- granularity. This allows the scheduler to both accurately model
- instruction latency and avoid overcommitting functional units.
-
-
-
-
-
-
-
-
-
-
-
-
LLVM IR has several new features for better support of new targets and that
-expose new optimization opportunities:
-
-
-
-
-
-
-
-
-
-
-
In addition to a large array of minor performance tweaks and bug fixes, this
-release includes a few major enhancements and additions to the optimizers:
-
-
- - TBAA.
- - LTO has been improved to use MC for parsing inline asm and now
- can build large programs like Firefox 4 on both OS X and Linux.
-FastISel for ARM.
+
+
The pre-register-allocation (preRA) instruction scheduler models register
+ pressure much more accurately in some cases. This allows the adoption of more
+ aggressive scheduling heuristics.
+
+
+ LiveDebugVariables is a new pass that keeps track of debugging information for
+ user variables that are kept in registers in optimized builds.
+
+
+Scheduler now models operand latency and pipeline forwarding.
+
+Major regalloc rewrite, not on by default for 2.9 and not advised to use it.
+ * New basic register allocator that can be used as a safe fallback when
+ debugging. Enable with -regalloc=basic.
+ * New infrastructure for live range splitting. SplitKit can break a live
+ interval into smaller pieces while preserving SSA form, and SpillPlacement
+ can help find the best split points. This is a work in progress so the API
+ is changing quickly.
+ * The inline spiller has learned to clean up after live range splitting. It
+ can hoist spills out of loops, and it can eliminate redundant spills.
+ Rematerialization works with live range splitting.
+ * New greedy register allocator using live range splitting. This will be the
+ default register allocator in the next LLVM release, but it is not turned on
+ by default in 2.9.
+
+
+
@@ -583,6 +515,30 @@ FastISel for ARM.
+-
+X86: Reimplemented all of MMX to introduce a new LLVM IR x86_mmx type. Now
+ random types like <2 x i32> are not iseld to mmx without emms. The
+ -disable-mmx flag is gone now.
+
+
+ -
+X86 support for FS/GS relative loads and stores using address space 256/257 are
+ reliable now.
+
+
+ -
+X86: Much better codegen for several cases using adc/sbb instead of cmovs for
+ conditional increment and other idioms.
+
+
+ -
+ The X86 backend has adopted a new preRA scheduling
+ mode, "list-ilp", to shorten the height of instruction schedules
+ without inducing register spills.
+
+
+ MC assembler support for 3dNow! and 3DNowA instructions.
+
- Several bugs have been fixed for Windows x64 code generator.
@@ -598,9 +554,39 @@ FastISel for ARM.
+- ARM Fast ISel
+- ARM: New code placement pass.
+- ARM: Improved code generation for Cortex-A8 and Cortex-A9 CPUs.
+- ARM: __builtin_prefetch turns into prefetch instructions.
+- Countless ARM microoptimizations.
+
+- The ARM backend preRA scheduler now models machine resources at cycle
+ granularity. This allows the scheduler to both accurately model
+ instruction latency and avoid overcommitting functional units.
+
+
+
+
+
+
+
+ PPC: Switched to MCInstPrinter, and MCCodeEmitter. Ready to implement support
+ for directly writing out mach-o object files, but noone seems interested.
+
+ MicroBlaze: major updates for aggressive delay slot filler, MC-based assembly
+ printing, assembly instruction parsing, ELF .o file emission, and MC
+ instruction disassembler.
+
+ SPARC: Many improvements, including using the Y registers for multiplications
+ and addition of a simple delay slot filler.
+
+
+
@@ -614,30 +600,78 @@ on LLVM 2.8, this section lists some "gotchas" that you may run into upgrading
from the previous release.
+ last release for llvm-gcc
+- DIBuilder provides simpler interface for front ends like Clang to encode debug info in LLVM IR.
+ - This interface hides implementation details (e.g. DIDerivedType, existence of compile unit etc..) that any front end should not know about.
+ For example, DIFactory DebugFactory;
+ Ty = DebugFactory.CreateDerivedType(DW_TAG_volatile_type,
+ findRegion(TYPE_CONTEXT(type)),
+ StringRef(),
+ getOrCreateFile(main_input_filename),
+ 0 /*line no*/,
+ NodeSizeInBits(type),
+ NodeAlignInBits(type),
+ 0 /*offset */,
+ 0 /* flags */,
+ MainTy);
+ can be replaced by
+ DbgTy = DBuilder.createQualifiedType(DW_TAG_volatile_type, MainTy);
+DIFactory is gone now.
+
+
-
In addition, many APIs have changed in this release. Some of the major LLVM
-API changes are:
-
+
+
+ LoopIndexSplit pass was removed, unmaintained.
+ LiveValues, SimplifyHalfPowrLibCalls, and GEPSplitter were removed.
+ Removed the PartialSpecialization pass, it was unmaintained and buggy.
+
+ DIFactory removed, use DIBuilder instead.
+
+ Triple::normalize is new, llvm triples are always stored in normalized form internally.
+
+ Triple x86_64--mingw64 is obsoleted. Use x86_64--mingw32 instead.
+
+ PointerTracking has been removed from mainline, moved to ClamAV.
+
-
This section lists changes to the LLVM development infrastructure. This
-mostly impacts users who actively work on LLVM or follow development on
-mainline, but may also impact users who leverage the LLVM build infrastructure
-or are interested in LLVM qualification.
+
In addition, many APIs have changed in this release. Some of the major
+ LLVM API changes are:
+
+ include/llvm/System merged into include/llvm/Support.
+
+
+ APInt API changes, see PR5207.
+
+ MVT::Flag renamed to MVT::Glue
+
+
+ error_code + libsystem + PathV2 changes
+ The system_error header from C++0x was added.
+ * Use if (error_code ec = function()) to check for error conditions
+ from functions which return it.
+ * error_code::message returns a human readable description of the error.
+
+ PathV1 has been deprecated in favor of PathV2 (sorry I didn't finish
+ this before the release).
+ * No Path class, use a r-value convertible to a twine instead.
+ * Assumes all paths are UTF-8.
+
+